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1.

Problem: Logic Function Extraction


n-channel transistors produce a logic 0 at the output when a logic 1 is apllied on
its gate.
a)
4. Exercise: CMOS and Pass Transistor x = a ⋅b + c
x = a ⋅ b + c = a ⋅ b ⋅ c = (a + b )c = a c + bc
Logic
Solution Suggestions

y = a ⋅ b + d (a ⋅ f + c )
b) x = a⋅c + y
⇒ x = (a + c )y = (a + c )(a ⋅ b + d (a ⋅ f + c ))
VLSI- Design of Integrated Circuits = a ⋅c ⋅d + a ⋅b⋅c + a ⋅c ⋅d ⋅ f

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Microelectronic 4. Exercise: CMOS and Microelectronic
Systems Pass Transistor Logic Systems 2

Problem 2: CMOS Logic 1. Way


8 transistors required
Z = A⊕ B ⊕C ⊕ D
A XOR function with two variables can be implemented in two ways: + 4 for the negation of a and b

1. Way
For the implementation of the function
a) Implementation of the logic ‘1’ of the function with PMOS network, with Z=a⊕b⊕c⊕d, a total of 8x3+4x3=36
inverted input variables (because of the PMOS transistors) transistors are required.
b) Implementation of the logic ‘0’ with NMOS network:
A more efficient sollution is to use “gated logic”
parallel PMOS → series NMOS • One variable is used as controll variable
series PMOS → parallel NMOS f = a⊕b
2. Way • Using ‘a’ as the controll variable:
a) Transformation f → f’ 2+4 transistors required
b) Implementation of f’ in a NMOS network with positive variables Issue: the output level
c) Implementation of f’ in a PMOS network (series ⇔ parallel)
Institute of Institute of
4. Exercise: CMOS and Microelectronic 4. Exercise: CMOS and Microelectronic
Pass Transistor Logic Systems 3 Pass Transistor Logic Systems 4
That’s why additional PMOS transistors are required Problem 3: Full Adder

Only 4+4 transistors are required


instead of 8+4. S = A⊕ B ⊕C
b
= abc + abc + abc + abc
= c(ab + ab ) + c(ab + ab )

p network n network

Cout = Cin A + Cin B + AB

p network n network
Institute of Institute of
4. Exercise: CMOS and Microelectronic 4. Exercise: CMOS and Microelectronic
Pass Transistor Logic Systems 5 Pass Transistor Logic Systems 6

Problem4: CMOS Logic


Implementation of Cout using pass transistor logic

2nd way:
f = ( A + B )(C + D ⋅ E ) (1)
= AC + A D E + BC + B D E (2)
Implementation using the first equation is more efficient, since it requires
fewer transistors:
Cout = f = A ⋅ C ⋅ B + A ⋅ C ⋅1 + A ⋅ C ⋅ B + A ⋅ C ⋅ 0

Institute of Institute of
4. Exercise: CMOS and Microelectronic 4. Exercise: CMOS and Microelectronic
Pass Transistor Logic Systems 7 Pass Transistor Logic Systems 8
5. Problem: Circuit Reconstruction c) The pass transistor implementation needs 6 transistors (4 pass
f =1 +4 transistors and 2 for the inverter).
a) A4
S2 3=1
BS A4
S2⋅4
BS
3
(1) (2 ) Advantages & disadvantages of transmission-gate logic:
Advantages: fewer transistors
Disadvantages: lower speed
time-skew problems can lead to short circuits

20 transistors 14 transistors

b) f = AS + BS
f = ( A + S ) ⋅ (B + S )
8 transistors
+ 6 (inverters for
A,B,S)
= 14 transistors
Institute of Institute of
4. Exercise: CMOS and Microelectronic 4. Exercise: CMOS and Microelectronic
Pass Transistor Logic Systems 9 Pass Transistor Logic Systems 10

6. Problem: Pass Transistor Logic


c′d ′ + ac
F = a{ ′cb′ + a{
{ d + a{ ′c′b

It’s more convenient to chose ‘a’ and ‘c’ as control variables:

Institute of
4. Exercise: CMOS and Microelectronic
Pass Transistor Logic Systems 11

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