LT1619

Low Voltage Current Mode

PWM Controller
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FEATURES DESCRIPTIO
■ Wide VIN Range: 1.9V to 18V The LT ®1619 is a fixed frequency PWM controller for
■ 300kHz Fixed Frequency Current Mode Control implementing current mode DC/DC converters with mini-
■ 1A Rail-to-Rail N-Channel MOSFET Driver mum external parts. The LT1619 operates with input
■ Low 53mV Current Limit Threshold Voltage voltages ranging from 1.9V to 18V and is suitable for a
Improves Efficiency variety of battery-powered and distributed DC/DC con-
■ Implements Boost, SEPIC and Flyback Converters verters. The internal rail-to-rail N-channel MOSFET driver
Requiring Low Side Power Transistors operates either from the input in the nonbootstrapped
■ Internal Current Sense Amplifier mode or from the output in bootstrapped operation. The
with Leading Edge Blanking driver is designed to drive a low side power transistor in
■ Up to 500kHz External Synchronization boost, SEPIC, flyback and other topologies.
■ Burst Mode® Operation for High Efficiency Converter efficiency is improved at heavy loads with a
at Light Load 53mV current sense voltage and at light load with Burst
■ 140µA Quiescent Current Mode operation. The operating frequency is internally set
■ 15µA Shutdown Current at 300kHz. The oscillator can also be synchronized exter-
■ 8-Lead MSOP and SO Packages nally up to 500kHz. No load quiescent current is 140µA and
U shutdown current is 15µA.
APPLICATIO S The LT1619 is available in 8-lead MSOP and SO packages.
■ 3.3V to 5V DC/DC Converters , LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
■ Distributed Power Supplies
■ Isolated Power Supplies

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TYPICAL APPLICATIO
VIN Efficiency
3.3V
95

1 8 L1 90
37.4k S/S VIN + C1 5.6µH
0.1µF 5A
EFFICIENCY (%)

12.4k 2 7 22µF
FB DRV VOUT 85
LT1619 0.1µF 5V
3 6 M1 2.2A
VC GATE D1 80
Si9804
75k
+ COUT
4 5
220pF GND SENSE 440µF
75
15nF RSENSE
0.01Ω
1619 F01 70
C1: PANASONIC EEFCDOK220R 1 10 100 1000
COUT: KEMET T495X227K010AS (×2)
LOAD CURRENT (mA)
D1: MBRD835L
L1: COILCRAFT DO5022P-562 1619 F01a

Figure 1. High Efficiency 3.3V to 5V DC/DC Converter

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LT1619
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ABSOLUTE AXI U RATI GS (Note 1)

Input Voltage (VIN) ................................... – 0.3V to 20V
Gate Drive Supply Voltage (DRV) ............. – 0.3V to 20V
Shutdown/Synch Voltage (S/S) ................ – 0.3V to 20V
Feedback Voltage (FB) .............................................. VIN
Compensation Voltage (VC) ...................................... 3V
Gate Drive Output Current (GATE) ........................ ±1.5A
Current Sense Voltage (SENSE) ................. – 0.5V to VIN
Operating Temperature Range (Note 2) .. – 40°C to 85°C
Junction Temperature (Note 3) ............................. 125°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C

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PACKAGE/ORDER I FOR ATIO
ORDER PART ORDER PART
NUMBER TOP VIEW NUMBER
TOP VIEW
S/S 1 8 VIN
S/S 1 8 VIN LT1619EMS8 LT1619ES8
FB 2 7 DRV FB 2 7 DRV
VC 3 6 GATE
VC 3 6 GATE
GND 4 5 SENSE
GND 4 5 SENSE
MS8 PACKAGE
8-LEAD PLASTIC MSOP
MS8 PART MARKING S8 PART MARKING
S8 PACKAGE
TJMAX = 125°C, θJA = 200°C/ W LTHC 8-LEAD PLASTIC SO
1619
TJMAX = 125°C, θJA = 120°C/ W

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VIN = VDRV = 2.5V, VS/S = VIN, COMP open, VSENSE = 0V unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference Voltage Measured at the FB Pin ● 1.22 1.24 1.26 V
Reference Line Regulation 1.9V ≤ VIN ≤ 18V 0.004 0.05 %/V
FB Input Bias Current VFB = VREF 10 25 nA
Error Amplifier Transconductance 80 170 260 µΩ –1
Error Amplifier Output Source Current VFB = 1V, VCOMP = 1V 4 8.7 14 µA
Error Amplifier Output Sink Current VFB = 1.5V, VCOMP = 1V 4 8.7 14 µA
Error Amplifier Clamp Voltage VFB = 1V 1.6 2.2 V
Undervoltage Lockout Threshold 1.65 1.85 V
Input Voltage Range ● 1.9 18 V
Switching Frequency 1.9V ≤ VIN ≤ 18V ● 220 300 360 kHz
Synchronization Frequency Range 370 500 kHz
Maximum Duty Cycle ● 88 92 %
Current Limit Threshold ● 40 53 66 mV
Burst Mode Operation Current Limit 10 mV

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 LT1619
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VIN = VDRV = 2.5V, VS/S = VIN, COMP open, VSENSE = 0V unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Current Sense Input Current VSENSE = 0V ● – 90 – 120 – 150 µA
Current Limit Delay 150 ns
Driver Output Rise Time CL = 3300pF 30 ns
Driver Output Fall Time CL = 3300pF 35 ns
Driver Output High Level IOUT = – 20mA VDRV – 0.6 VDRV – 0.35 V
IOUT = – 200mA VDRV – 1.6 VDRV – 1.2 V
Driver Output Low Level IOUT = 20mA 100 200 mV
IOUT = 200mA 0.5 0.7 V
Shutdown Driver Output Level VS/S = 0V, IOUT = 20mA 100 200 mV
Idle Mode Driver Output Level VS/S = VIN, VFB = 1.5V, IOUT = 20mA 100 200 mV
S/S Pin Current VS/S = VIN 4 µA
VS/S = 0V –2 µA
Operating Supply Current VFB = 1V 9 mA
Quiescent Supply Current VS/S = VIN, VFB = 1.5V ● 140 220 µA
Shutdown Supply Current VS/S = 0V 15 19 µA
VS/S = 0V, VIN = 18V, TA = 85°C 40 µA
Shutdown Threshold 0.45 1.2 V
Shutdown Delay 12 17 33 µs

Note 1: Absolute Maximum Ratings are those values beyond which the life Note 3: TJ is calculated from the ambient temperature TA, the power
of the device may be impaired. dissipation PD and the thermal resistance θJA of the package according to
Note 2: The LT1619E is guaranteed to meet performance specifications the formula:
from 0°C to 70°C. Specifications over the – 40°C to 85°C operating TJ = TA + PD • θJA
temperature range are assured by design, characterization and correlation
with statistical process controls.

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TYPICAL PERFOR A CE CHARACTERISTICS
Bandgap Voltage vs Temperature IS/S vs VS/S S/S Pin Current vs Temperature
1.245 5 5
VIN = 2.5V TA = –40°C
1.243 4 4
1.241 TA = 25°C VS/S = 2.5V
3 3
BANDGAP VOLTAGE (V)

S/S PIN CURRENT (µA)

1.239 TA = 85°C
1.237 2 2
IS/S (µA)

1.235 1 1
1.233 0 0
1.231
–1 –1 VS/S = 0V
1.229
1.227 –2 –2

1.225 –3 –3
–40 –20 0 20 40 60 80 100 120 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –40 –20 0 20 40 60 80 100 120
TEMPERATURE (°C) VS/S (V) TEMPERATURE (°C)
1619 G01 1619 G02 1619 G03

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 LT1619
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TYPICAL PERFOR A CE CHARACTERISTICS
Shutdown Supply Current Idle Mode Supply Current Frequency Deviation from
vs Input Voltage vs Temperature Nominal vs Temperature
45 200 10

DEVIATION FROM NOMINAL FREQUENCY (%)

VIN = 2.5V VIN = 2.5V
8 NOMINAL FREQUENCY = 300kHz
40

IDLE MODE SUPPLY CURRENT (µA)

190 6
35
SUPPLY CURRENT (µA)

TA = –40°C 4
180
30 2
TA = 25°C
25 170 0
TA = 85°C –2
20
160
–4
15
–6
150
10 –8
5 140 –10
0 2 4 6 8 10 12 14 16 18 20 –40 –20 0 20 40 60 80 100 120 – 40 – 20 0 20 40 60 80 100
INPUT VOLTAGE (V) TEMPERATURE (°C) TEMPERATURE (°C)
1619 G04 1619 G05 1619 G06

Maximum Duty Ratio Deviation from Nominal Current Limit Threshold

vs Temperature Frequency vs Input Voltage vs Temperature
95 8 58
VIN = 2.5V TA = 25°C VIN = 2.5V
NOMINAL FREQUENCY = 300kHZ 57

CURRENT LIMIT THRESHOLD (mV)

94 6
FREQUENCY DEVIATION (%)

56
DUTY RATIO (%)

4
93 55

2 54
92
53
0
52
91
–2
51

90 –4 50
–40 –20 0 20 40 60 80 100 0 2 4 6 8 10 12 14 16 18 20 –40 – 20 0 20 40 60 80 100
TEMPERATURE (°C) INPUT VOLTAGE (V) TEMPERATURE (°C)
1619 G07 1619 G08 1619 G09

Burst Mode Operation Current SENSE Pin Input Bias Current SENSE Pin Input Bias Current
Limit Threshold vs Temperature vs Temperature vs Sense Voltage
14 –115 – 90
VIN = 2.5V VSENSE = 0V TA = 25°C
–117
12 DUTY CYCLE = 0 – 95
CURRENT LIMIT THRESHOLD (mV)

–119
SENSE PIN CURRENT (µA)
SENSE PIN CURRENT (µA)

–100
10 –121
–123 –105
8
–125 –110
6 –127
–115
4 –129
–120
–131
2 –125
–133
0 –135 –130
–40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100 –10 0 10 20 30 40 50 60
TEMPERATURE (°C) TEMPERATURE (°C) VSENSE (mV)
1619 G10 1619 G11 1619 G12

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PI FU CTIO S
S/S (Pin 1): Shutdown and Synchronization. Shutdown is
active low with a typical threshold voltage of 0.9V. For
normal operation, the S/S pin is tied to VIN. To externally
synchronize the controller, drive the S/S pin with pulses.
FB (Pin 2): The inverting Input of the Error Amplifier.
Connect the resistor divider tap here. Set VOUT according
to VOUT = 1.24(1 + R1/R2). See Figure 1.
VC (Pin 3): Compensation Pin for the Error Amplifier. VC is
the output of the transconductance amplifier. Overall loop
is compensated with an RC network from this pin to the
ground.
GND (Pin 4): Ground. Connect to local ground plane.
LT1619
SENSE (Pin 5): The Input of the Current Sense Amplifier.
The SENSE pin is connected to the source of the N-channel
MOSFET and to a sense resistor to the ground. The current
limit threshold is internally set at 53mV, giving a maximum
switch current of 53mV/RSENSE.
GATE (Pin 6): The Output of the MOSFET Driver.
DRV (Pin 7): The Pull-Up Supply of the MOSFET Driver. Tie
this pin to VIN (Pin 8) for nonbootstrapped operation or to
the converter output for bootstrapped operation.
VIN (Pin 8): Supply or Battery Input. Must be closely
bypassed to the ground plane.

W
BLOCK DIAGRA
VC VIN
3 8 –
UVLO
A2
1.8V +
ERROR
AMPLIFIER
1.24V +
gm –
IDLE
FB 2 – A1
VB +
VIN

DRV
7
–
C1
+ S GATE
Q DRIVER 6
R
LOAD
SENSE
+ + 5
Σ
RSENSE
CLK
– GND
RAMP COMP 4
CURRENT 280ns
300kHz
S/S 1 SYNC SENSE
OSCILLATOR LEADING
AMP+
EDGE
BLANKING
+

SHUTDOWN
DELAY
REF/BIAS CURRENT – ILIM
LIMIT
1619 F02
COMPARATOR

Figure 2. LT1619 Block Diagram

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LT1619
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OPERATIO
The LT1619 is a fixed frequency current mode switching
regulator PWM controller that can be used in boost, SEPIC
or flyback modes. The device operates from an input
supply range of 1.9V to 18V, and has a separate supply pin
(DRV) for the gate driver. The DRV pin can be bootstrapped
to VOUT for additional gate enhancement in low voltage
applications like 3.3V to 5V boost converters, or con-
nected to the input supply for higher voltage inputs.
To best understand operation of the LT1619, please refer
to Figure 2, the Block Diagram. The gate drive circuit turns
on the external MOSFET at the trailing edge of oscillator
output signal CLK. MOSFET current is sensed with an
external resistor (RSENSE of Figure 1). A leading edge
blanking circuit disables the current sense amplifier for
280ns immediately following switch turn-on, preventing
gate charging current from prematurely tripping the PWM
comparator. A slope compensating ramp, derived from
the oscillator, is added to the current sense output. The
driver turns off the MOSFET when this sum exceeds the
error amplifier output VC. The switch current is limited
with a separate comparator. The compensating ramp is a
progressive nonlinear function of the operating duty ratio
whereas the current limit does not vary with the duty ratio.
Error amplifier output VC determines the peak switch cur-
rent required to regulate the output voltage. VC can be
considered a measure of output current. At heavy loads,
VC is in its upper range. Average and peak inductor cur-
rents are high. In this range, the inductor tends to run in
continuous conduction mode (CCM), where current is al-
ways flowing in the inductor. As load current decreases,
average and peak inductor current decreases. When the
average inductor current falls below 1/2 of the peak-to-peak
inductor current ripple, the converter enters discontinu-
ous conduction mode (DCM), where current in the induc-
tor reaches zero sometime during the discharge phase.
Further reduction in output current moves VC towards its
lower operating range, decreasing inductor current. Hys-
teretic comparator A1 determines if VC is too low for the
LT1619 to operate efficiently. As VC falls below the trip
voltage VB, A1’s output goes high, turning off all blocks
except the error amplifier, A1 and A2. The LT1619 enters
the idle state and switching stops. The device draws just
140µA from the input in the idle state. Output load current
6
discharges the output capacitor, causing the output volt-
age to decrease. As VOUT decreases, VC increases. As VC
increases above VB, switching action begins, delivering
power to the output. The switch current sense threshold is
about 10mV in this VC region. If the output load remains
light, the output voltage will rise and VC will fall, causing
the converter to idle again. This is known as Burst Mode
operation. The burst frequency depends on input voltage,
output voltage, inductance and output capacitance. Out-
put voltage ripple during Burst Mode operation is usually
higher than when the converter is switching continuously.
Burst Mode operation increases light load efficiency be-
cause it delivers more energy per clock cycle than possible
with discontinuous mode operation and extremely low
peak switch current, allowing fewer switching cycles to
maintain a given output. IC supply current therefore be-
comes a small fraction of the total input current.
Setting Output Voltage
The output voltage of the LT1619 is set with resistive
divider R1 and R2 connected from the output to ground as
detailed in Figure 3. The divider tap is tied to the device FB
pin. Current through R2 should be significantly higher
than the FB pin bias current of 25nA. With R2 = 10k, the
input bias current of the error amplifier is 0.02% of the
current in R2.
VO
LT1619
R1
( )
VO = 1.24V 1 + R1
R2
( )
FB
VO
R1 = R2 –1
R2 1.24
1619 F03
Figure 3. Feedback Resistive Divider
Synchronization and Shutdown
The S/S pin (Pin 1) can be used to synchronize the
oscillator to an external source. The S/S pin is tied to the
input (VIN > 1.9V) for normal operation. The oscillator in
the LT1619 can be externally synchronized by driving the
S/S pin with a pulse train with an amplitude of at least 1V.
The maximum allowable rise time is a function of the
pulse amplitude, as shown in Table 1. Rise times equal to
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 LT1619
U
OPERATIO
or less than the number specified in Table 1 are accept- more than 33µs. This shutdown delay is reset whenever
able. The maximum duty cycle is essentially unaffected by the S/S pin voltage rises above the shutdown threshold.
synchronization. Applying a logic low signal at the S/S pin causes the gate
The device will go into shutdown mode if the S/S pin drive output to go low. Although all circuits in the LT1619
voltage stays below the shutdown threshold of 0.45V for are disabled, the pull-down circuit in the MOSFET buffer is
still biased on. It is capable of shunting any leakage or
Table 1. Maximum Allowable Rise Time of Synchronization transient current at the GATE pin to ground, eliminating
Pulse. Rise Time Can Be Slower if Clock Amplitude is Higher the need for an external bleed resistor. The LT1619 con-
SYNCHRONIZATION MAXIMUM ALLOWABLE sumes 15µA in shutdown.
AMPLITUDE (V) RISE TIME (ns)
The LT1619 is guaranteed to start with a minimum VIN of
1.2 120
1.85V. Comparator A2 senses the input voltage and gen-
1.5 220
erates an undervoltage lockout (UVLO) signal if VIN falls
2.0 350
below this minimum. While in undervoltage lockout, VC is
2.5 470 pulled low and the LT1619 stops switching. The supply
3.0 530 current drawn by the device falls to 140µA.

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APPLICATIO S I FOR ATIO
Inductor pin (DRV) for design flexibility. In a boost converter
design, the DRV pin can be tied to the converter output if
The value of the inductor is usually selected so that the
the minimum input voltage is insufficient to fully enhance
peak-to-peak ripple current is less than 30% of the maxi-
the power MOSFET. During start-up, the MOSFET is driven
mum inductor current. The inductor should be able to
with a gate voltage starting from VIN – VD (VD is the
handle the maximum inductor current at full load without
forward voltage of the rectifying diode). As the output
saturation. Powder iron cores are not suitable for high
voltage rises, the gate drive also increases until steady
frequency switch mode power supply applications be-
state is reached. If the steady-state converter output
cause of their high core losses. Ferrite cores have very low
voltage exceeds the maximum allowable gate source
core losses and are the material of choice for high fre-
voltage and the input voltage is sufficient to enhance the
quency DC/DC converters.
MOSFET, the DRV pin is tied to the input supply. For a
Power MOSFET Driver SEPIC converter, the DRV pin can be tied to the input or
diode OR’ed from the input and the output (Figure 4).
The LT1619 is capable of driving a low side N-channel
power MOSFET with up to 60nC of total gate charge (Qg).
VOUT
An external driver is recommended for MOSFETs with •
+

VIN
greater than 80nC of total gate charge. The peak gate drive
current varies from 0.5A with VDRV = 2.5V to 1.2A with DRV
+
VDRV = 10V. The MOSFET driver is capable of charging the LT1619

gate of the power MOSFET to within 350mV of the upper GND

RS
•
gate drive supply rail (DRV). It can also pull the gate of the 1619 F03

MOSFET to within 100mV of ground during turnoff. The

upper supply rail of the gate drive is brought out as a device Figure 4. SEPIC Converter with Diode OR’ed Gate Drive Supply

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LT1619
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APPLICATIO S I FOR ATIO
Power MOSFET
MOSFET power dissipation can be separated into fre-
quency independent and frequency dependent compo-
nents. The RDS(ON) loss in the switch is the product of the
mean square switch current and switch RDS(ON) and it
does not vary with the operating frequency.
The frequency-dependent switching losses consist of 1)
switch transition loss due to finite rise and fall times of the
drain source voltage and the drain current 2) gate switch-
ing loss, i.e., a packet of charge Qg (the total gate charge)
which is moved from the gate drive power supply to
ground in every switch cycle, and 3) the drain switching
loss, charge stored on the parasitic drain capacitance,
COSS is dumped to ground as the switch is turned on. The
transistor loss can be expressed as:
PLOSS = IDRMS2 RDS(ON) + transition loss + QgVGfS
+ 1/2COSSVDS(OFF)2fS
where the transition loss can be estimated with:
2
CRSSVDS(OFF) fS
Transition Loss = ID
IG(AVG)
Qg = The total gate charge
VG = Gate drive voltage ≈ VDRV
IG(AVG) = The average MOSFET buffer output current
fS = Operating frequency
CRSS = The average CGD between VDS = 0V
and VDS = VDS(OFF)
At low VDS(OFF) (≤12V) and operating frequencies below
500kHz, the ohmic losses often dominate. For high voltage
converters, the transition loss and COSS charge dumping
loss can dramatically impact the converter efficiency.
MOSFETs with lower parasitic capacitances but higher
RDS(ON) may actually provide better efficiency in these
situations.
Capacitors
In a switch mode DC/DC converter, output ripple voltage
is the product of the equivalent series resistance (ESR) of
8
the output capacitor and the peak-to-peak capacitor
current. Depending on topology, current feeding the out-
put capacitor can be continuous or discontinuous. The input
current can also be continuous or discontinuous even if the
inductor current itself is continuous. In boost topology, the
inductor is in series with the input source so the input
current is continuous and the output current is discontinu-
ous. In buck-boost or flyback converters, the inductor is
not in series with the input source nor the output, so nei-
ther the input current nor output current is continuous.
Whenever a terminal current is discontinuous, the capaci-
tor at that terminal should be chosen to handle the ripple
current. Capacitor reliability will be adversely affected if
the ripple current exceeds the maximum allowable rat-
ings. This maximum rating is specified as the RMS ripple
current. Several capacitors may be mounted in parallel to
meet the size and ripple current requirements.
Besides the ripple voltage requirements, the output ca-
pacitor also needs to be sized for acceptable output
voltage variation under load transients.
Current Sensing Resistor RSENSE
The LT1619 drives a low side N-channel MOSFET switch.
The switch current is sensed with an external resistor
RSENSE connected between the source of the MOSFET and
ground. The internal blanking circuit blocks the voltage
spike developed across RSENSE for 280ns at switch turn-
on. The switch is turned off when the instantaneous
voltage across RSENSE exceeds the current limit threshold,
VSENSE. Allowing variations in VSENSE yields:
VSENSE(MIN)
RSENSE =
IL(MAX)
The current limit threshold is constant and does not vary
with duty ratio.
Due to low signal level of the sense voltage, low inductance
sense resistors are required to reduce switching noise.
Low TC resistors maintain constant current limit over
temperature. Dale WSL and IRC series sense resistors
meet these criteria.
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APPLICATIO S I FOR ATIO
Diode
Schottky diodes are recommended for low output voltage
applications because of their low forward voltage. Since
Schottky diodes have negligible stored charge, charge
dumping loss is also reduced. The reverse breakdown
voltage of the diode should exceed the maximum reverse
voltage stress of the topology used. The diode should also
be able to carry the peak diode current with acceptable
foward voltage. For the boost converter in Figure 1, the
peak inductor current is approximately 5A. A Motorola
MBRD835 is used due to its low forward voltage.
Lowering Burst Mode Operation Current Limit
The LT1619 automatically enters Burst Mode operation as
VC voltage falls below VB. The corresponding switch
current is the Burst Mode operation switch current thresh-
old, ID(BURST).
The effective Burst Mode operation current threshold can
be lowered by adding an offset to the input of the current
sense amplifier so that the switch current appears higher
to the PWM comparator. This has the effect of shifting the
VC operating range above VB. Although Burst Mode opera-
tion is not entirely disabled, the peak switch current before
entering Burst Mode operation is greatly reduced due to
the offset of the current sense amplifier. The peak switch
current is also determined by the current sense amplifier
blanking.
To lower the Burst Mode operation current sense thresh-
old, a resistor ROS is added between the SENSE pin and
the sense resistor RSENSE (Figure 5). The input bias
current IBIAS of the current sense amplifier, which has a
CURRENT
ID
SENSE
AMPLIFIER
– +
IBIAS = 120µA IBIAS = 120µA
5 with corner frequency about 5 times the switching
ROS
SENSE RSENSE
4 switching transients. In Figure 6 the lowpass filter ROS and
GND 1619 F05
Figure 5. Lowering Burst Mode Operation Current Limit
LT1619
tolerance of ±25% and is temperature stable, develops an
offset voltage at the sense input. The value of ROS required
for non-Burst Mode operation can be obtained with the
expression:
IBIASROS ≥ VSENSE(BURST)
where
VSENSE(BURST) = (Burst Mode operation peak switch
current, ID(BURST)) • RSENSE
For example, if IBIAS = 120µA and VSENSE(BURST) = 10mV:
10mV
ROS ≥ = 83Ω
120µA
Allowing for 25% and 30% variations in IBAIS and
VSENSE(BURST) respectively:
ROS = (1.25)(1.3)(83Ω)
Choose ROS = 137Ω to completely disable Burst Mode
operation. Lower values of ROS (for example, 50Ω to
100Ω) can be used to lower the effective Burst Mode
current limit.
The value of the sense resistor is then adjusted to compen-
sate for the reduced full-scale sense voltage.
IBIASROS + IL(MAX)RSENSE = 40mV
Filtering Current Sense Signal
In a current mode converter, the current sense circuit
senses the switch current and terminates the switch
conduction. In the LT1619, the current sense amplifier
has a full-scale input voltage range from the ground to the
current limit threshold (53mV). Due to high speed switch-
ing transients and parasitic trace inductances, the current
sense signal VSENSE tends to be noisy. If the VSENSE
switching transient is excessive, the current sense ampli-
fier will amplify the spurious transient instead, resulting in
jittery operation. In situations where the internal leading
edge blanking is inadequate, a lowpass filter (Figure 6)
frequency can be used to further attenuate high speed
CS has a corner frequency of:
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LT1619
U U W U
APPLICATIO S I FOR ATIO
1 VIN
fCORNER = ≈ 5fS VZ
2πROSCS 1
S/S VIN
8

(The input impedance of the sense amplifier at the SENSE

IS/S
2
FB DRV
7 ( IS/S
VS/S = 0 ) R3 < SHUTDOWN THRESHOLD

pin is 2500Ω and ROS is typically less than 137Ω.) Typical R3

3
LT1619
6
UVLO THRESHOLD = VZ + SHUTDOWN
THRESHOLD ≈ VZ + VBE
VC GATE
values for ROS and CS are 100Ω and 1nF. The 100Ω value IS/S ≈ –2µA
VS/S = 0
for ROS reduces Burst Mode threshold; use 10Ω and 10nF 4
GND SENSE
5

when this is not desireable. 1619 F07

Figure 7. Implementing Undervoltage Lockout

LT1619 ID
PWM CURRENT
COMPARATOR SENSE I
AMPLIFIER
ROS ZENER AVALANCHE
SENSE
+ 5
+ DIODE DIODE
CS RSENSE
+
VSENSE I V
– 4
GND – –
1619 F06

V
Figure 6. Current Sense Filter for Improving Jitter Performance 0 BV < 5V

Figure 8. I-V Characteristics of Zener

and Avalanche Breakdown Diodes
Use of Shutdown Function to
Modify Undervoltage Lockout VIN

The LT1619 is designed to operate from an input supply

with voltage as low as 1.85V. Shutdown is activated when R4
1 8
the S/S pin is pulled below 0.45V. The shutdown threshold S/S VIN
is slightly greater than one junction diode forward voltage 2 7
FB DRV
and has the temperature characteristics of a junction
LT1619
C1 R3
diode. The S/S pin is normally tied to the input when 3
VC GATE
6

operating from a low voltage input source. 4 5

GND SENSE
Consider the 12V to – 65V isolated flyback converter (see 1619 F09

Typical Applications). The converter draws 3A at low line

while delivering 0.4A to the output. If the S/S pin is tied to
the input, then the LT1619 will start switching as soon as
VIN exceeds the internal UVLO threshold. With full load,
the converter can draw much higher than the steady-state
3A from the input source during start-up. If the input
source is current limited, the input voltage will collapse
and latch low.
The start-up problem can be prevented by adding a zener
diode and a resistor to the S/S pin (Figure 7). This is
equivalent to increasing undervoltage lockout voltage of
the controller. Before VIN exceeds the zener voltage VZ, the
S/S pin current is shunted to the ground through the
Figure 9. Filtering Input Voltage Ripple in UVLO Circuit
resistor R3. The voltage developed across R3 due to IS/S
should be less than the shutdown threshold. The LT1619
remains off until VIN exceeds the sum of VZ and the
shutdown threshold. True zener diodes (BV < 5V) and
higher voltage avalanche diodes have different I-V charac-
teristics (Figure 8). They need to be biased appropriately
(value of R3) in order to obtain correct UVLO threshold.
When implementing UVLO with converters with high input
ripple voltages (such as flyback and forward), the circuit
in Figure 7 is modified and shown in Figure 9.
1619fa

10
 LT1619
U U W U
APPLICATIO S I FOR ATIO
Here the input voltage ripple is filtered with R3, R4 and C1 The collector votage of Q2 is made about 1.4V at the VIN
so as to prevent the input ripple from falsely tripping the lower trip voltage. This is necessary to prevent the UVLO
LT1619 synchronization circuit. It is recommended that: circuit from interfering with the feedback amplifier in the
LT1619.
1
R4 ≈ R3
5 Trickle Current Start from High Voltage Supplies
1 The low shutdown and idle mode quiescent supply cur-
<< fOSC
( )
and
2π R3 || R4 C1 rents of the LT1619 can be utilized to implement trickle
current start from high voltage input sources (such as a
Implementation of Hysteretic UVLO 36V to 72V telecom bus). The trickle current start-up
with External Synchronization circuit in Figure 11 is modified from the UVLO circuit of
Figure 10. R10 is a high value resistor that charges the
The UVLO circuit shown in Figure 10 operates down to storage capacitor C2 during start-up. Before VCC reaches
0.9V supply voltage. Algebraically the UVLO trip points the upper UVLO trip point, Q2 holds the S/S pin low. The
are: LT1619 draws shutdown mode current (≈15µA) from VCC.
Q2 collector can also be tied to the VC pin through a diode
 R5  as in Figure 10. The LT1619 will then draw idle mode
VINH = VZ + VBE  1 + 
 R6 || R7  quiescent current (≈140µA) from VCC. R10 should be able
and to charge C2 while supplying current to the UVLO circuit

( ) VZ + VBE  ( )
and the LT1619. Maximizing R5 to R9 values reduces
R5 || R7 + R9 
R5 || R7 + R9
VINL = 
power dissipation in R10.
R5  R5 || R6 || R7 + R9 
  ( ) When VCC crosses the upper UVLO threshold, the LT1619
 R5  starts switching and its current consumption increases.
UVLO Hysteresis = VINH – VINL =   VZ + Before the bootstrap takes over, the LT1619 draws its
 R5 + R7 + R9  current from C2. VCC ramps towards the lower UVLO

VBE 
R5
–
R5 || R7 + R9 

( ) threshold. Increasing the value of C2 allows more time for
 R6 || R7  the bootstrap circuit to establish itself before the converter
 R6  enters undervoltage lockout.
VIN
HV VIN
R8 R9 1 8 BOOTSTRAP
CLK S/S VIN R10
30k 510k VCC WINDING
+ 2 7
8.2V R7 D1 FB DRV D2
– 51k BAT85 C2 R8 R9
1
S/S VIN
8
LT1619
3 6
VC GATE
2 7
R5 Q2 R7 FB DRV
51k 2N2222 4 5 T1
GND SENSE LT1619
Q1 3 6
2N2222 1619 F10 R5 Q2 VC GATE
R6
51k Q1 4 5
VIN UPPER TRIP POINT = 10V GND SENSE
VIN LOWER TRIP POINT = 8.4V R6 1619 F11

Figure 10. Addition of Hysteresis UVLO While Synchronizing the

LT1619. Component Values Shown are for the Upper and the
Lower VIN Trip Points of 10V and 8.4V. In UVLO, the Gate Drive Figure 11. Trickle Current Start-Up with Bootstrapped VCC
is Disabled by Pulling the VC Pin Low. Disabling the Clock Shuts
Down the LT1619. If Not Synchronized, the Collector of Q2 Can
Be Tied to the S/S Pin and the Diode D1 Can Be Eliminated
1619fa

11
LT1619
U U W U
APPLICATIO S I FOR ATIO
Increasing Ramp Compensation While Synchronizing whose peak amplitudes are made between 1/4 to 1/3 of the
current limit threshold, are developed across R13. As a
The LT1619 is synchronized by forced discharge of the
result, the effective current limit threshold is reduced by
internal timing ramp. The timing ramp amplitude de-
the sum of the compensating ramp and the offset voltage
creases as the synchronization frequency increases. Since
developed across R13 due to the SENSE pin input bias
the internal compensation ramp is derived from the timing
current (see Figure 5). Moreover, the current limit thresh-
ramp, reduced timing ramp results in diminished com-
old becomes duty cycle dependent.
pensating ramp. If the LT1619 is synchronized at frequen-
cies 20% to 30% higher than the free-running frequency, PC Board Layout and Other Practical Considerations
external ramp compensation will be required. Figures 12
and 13 show two such schemes. The following is recommended for PC board layout:
In both figures the compensating ramps are kept linear by 1. Trace lengths of the branches carrying switched cur-
making R11-C1 and R14-C2 products substantially higher rent should be kept short. For example, in the boost
than the synchronizing period. The compensation ramps, converter of Figure 1, the circuit loop formed by M1,
RSENSE, D1 and COUT carries switched current. The size
1 8
of this loop must be minimized. RSENSE and COUT
MAIN POWER
CLK S/S VIN
R11 TRANSISTOR should be grounded to a single point on a large ground
2
FB DRV
7 100k plane. This reduces switching noise and overall con-
D2 Q1
LT1619 1N4148 2N2222 verter jitter. It is also preferable to ground the input
3 6
VC GATE R12 capacitor C1 close to the common point between COUT
2200Ω
4 5 and RSENSE although this is less important.
GND SENSE
C1 R13
220pF 51Ω RSENSE 2. Keep the trace between the sense resistor and the
1619 F12 SENSE pin short. When sensing high switch current,
Kelvin connection to RSENSE is necessary.
Figure 12. Increasing Ramp Compensation. Q1 Buffers the C1
Ramp. D2 Discharges C1. Values Shown are for 10V Gate Drive
3. Bypass both the VIN and DRV pins with ceramic capaci-
and 15mV Ramp Across R13 at 90% Duty Cycle and 500kHz tors next to the IC and the ground plane.
4. Keep high voltage switching nodes, such as the drain
and gate of the MOSFET, away from the FB and VC pins.
1 8
CLK S/S VIN
R14 5. Use inductor so that its ripple current is between 1/4
2 7 8200Ω
FB DRV D2 and 1/3 of its peak current. Steeper inductor current
D3
3
LT1619
6
1N4148
1N4148 ramp results in sharper PWM comparator switching,
VC GATE
R15 hence less jitter.
4 5 2400Ω
GND SENSE
C2 R13
6. In most cases, filtering the current sense signal is not
RSENSE
2.2nF 51Ω necessary for jitter-free operation.
1619 F13

Figure 14 is the PC board layout for the 5V/8A and 12V/5A

Figure 13. Externally Increasing Ramp Compensation. Similar boost converters shown in Figures 15a and 16a.
to Figure 12 Except That C2 is Not Buffered with Transistor

1619fa

12
 LT1619
U U W U
APPLICATIO S I FOR ATIO

CDRV

CIN2
R1

RC 1 8
2 7 S S
LT1619 G
R2 3 6 G M1 M1

4 5
CZ CP
D D

RSENSE
GND
CIN1 COUT1, 2

D1
VOUT

L1
VIN

1619 F14

Figure 14. Recommended Component Placement for the Boost Converters in Figures 15a and 16a

1619fa

13
LT1619
U U W U
APPLICATIO S I FOR ATIO

VIN
3.3V
1 8
S/S VIN CIN2 L1
1µF 1µH
2 7 CERAMIC
FB DRV
CDRV + CIN1
LT1619 0.1µF 5V
3 6 300µF 8A
VC GATE CERAMIC M1
D1 R1
RC FDS6680A COUT2
4 5 ×2 37400Ω
CP 75k 10µF
150pF GND SENSE COUT1 +
CERAMIC
CZ RSENSE 220µF R2
15nF ×4
12400Ω

1619 F15a

CIN1: SANYO POSCAP 6TPB150M ×2

COUT1: SANYO POSCAP 10TPB220M ×4
D1: MOTOROLA MBRB1545CT
L1: SUMIDA CEPH149-1R0
RSENSE: PANASONIC 0.002Ω 1W

Figure 15a. 3.3V to 5V/8A Boost Converter

89
VIN = 3.3V

88

87
EFFICIENCY (%)

86

85

84

83
0.01 0.1 1 10
LOAD CURRENT (A)
1619 F15b

Figure 15b. Efficiency of the 5V/8A Boost Converter

1619fa

14
 LT1619
U U W U
APPLICATIO S I FOR ATIO

VIN
5V
1 8
S/S VIN CIN2 L1
1µF 1.8µH
2 7 CERAMIC
FB DRV
CDRV + CIN1
LT1619 0.1µF 12V
3 6 100µF 5A
VC GATE CERAMIC M1
D1 R1
RC FDS6690A COUT2
4 5 ×2 107k
CP 68.1k 10µF
47pF GND SENSE
COUT1
+
CERAMIC
CZ
RSENSE 600µF R2
2200pF
12400Ω

1619 F15a

CIN1: SANYO OS-CON 10SA100M

COUT1: SANYO OS-CON 16SA150M ×4
D1: MOTOROLA MBRB1545CT
L1: SUMIDA CDEP149-1R8
RSENSE: PANASONIC 0.002Ω 1W

Figure 16a. 5V to 12V/5A Boost Converter

95
VIN = 5V
94
93
92
EFFICIENCY (%)

91
90
89
88
87
86
85
0.01 0.1 1 10
LOAD CURRENT (A)
1619 F16b

Figure 16b. Efficiency of the 12V/5A Boost Converter

1619fa

15
LT1619
U
TYPICAL APPLICATIO S

VIN
T1
4.75V TO –48V/0.5A
5.25V •
• 470µF
35V
MBRS340T3 +
• SANYO MV-GX
1µF

+ 1500µF • • 470µF
1N749 15Ω 4.7µF
6.3V 4.3V 35V
SANYO MV-GX FILM + SANYO MV-GX

1 8
S/S VIN 4.7µF
1.1k FILM MBRS340T3
2 7
FB DRV
LT1619 10µF SUD45N05-20L 1M 12k
3 6
VC GATE 50V, 0.018Ω
30Ω
43nC 220pF
2.2nF 36k 4 5 2N5210
GND SENSE
10.5k
22nF 0.007Ω
1%
2N5210
432k
1%
1619 F17a

T1: COILTRONICS CTX02-14261, EFD20-3F3, 6 WINDINGS EACH, 12µH

Figure 17a. 5V to – 48V Cuk Converter

90
VIN = 5.25V
89
88
87
EFFICIENCY (%)

86
VIN = 5V
85
VIN = 4.75V
84
83
82
81
80
79
10 100 1000
LOAD CURRENT (mA)
1619 F17b

Figure 17b. Efficiency of the 5V to – 48V Cuk

1619fa

16
 LT1619
U
TYPICAL APPLICATIO S

10k
CNY17-3

6.2V
VIN
10.5V TO
13.7V T1 330pF 220pF 470Ω
2.2µF 100Ω
• 100V 43Ω 40V
1/4W
0.22µF 1k 62k
8.1V 43Ω W1 W3
50V 1W 470pF 121Ω LT1431
• 1 8
COLL REF
–32.5V 2 7
MBRS1100T3 NC NC
3 6
20k V+ FGND
MBRS1100T3 • W2 4
NC SGND
5
330pF W4 1µF 2.2µF 2.49k
50V 50V 40V
–65V
•
MBRS1100T3
1 8
S/S VIN
0.1µF 82k
2 7
FB DRV
T1
LT1619 10µF IRLR024N PHILIPS EFD20-3F3-A100-S
10k 3 6
150µF VC GATE 55V, 0.065Ω CORE SET (0.013" GAP, AI = 100nH/T2
20V QG = 15nC
W4 6T TRIFILAR 28AWG 2mil
SANYO 100Ω 4 5
GND SENSE W3 24T 28AWG POLYESTER
20SV150M W2 24T 28AWG FILM
(OS-CON) 1µF 0.008Ω W1 6T TRIFILAR 28AWG

1619 F18a

Figure 18a. Isolated Local SLIC Power Supply (Flyback) 20W Total Output Power (65V/0.3A or 32.5V/0.6A)

90

85

80
EFFICIENCY (%)

75

70

65

60
VIN = 13.7V
55 VIN = 12V
VIN = 10.5V
50
10 100 1000
LOAD CURRENT (mA)
1619 F18b

Figure 18b. Efficiency of the Isolated Local SLIC (Flyback)

1619fa

17
LT1619
U
PACKAGE DESCRIPTION

MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)

0.889 ± 0.127
(.035 ± .005)

5.23
(.206) 3.2 – 3.45
MIN (.126 – .136)

3.00 ± 0.102
0.42 ± 0.04 0.65 (.118 ± .004) 0.52
(.0165 ± .0015) (.0256) (NOTE 3) 8 7 6 5 (.206)
TYP BSC REF
RECOMMENDED SOLDER PAD LAYOUT

3.00 ± 0.102
4.90 ± 0.15
DETAIL “A” (.118 ± .004)
0.254 (1.93 ± .006)
NOTE 4
(.010)
0° – 6° TYP
GAUGE PLANE
1 2 3 4
0.53 ± 0.015
(.021 ± .006) 1.10 0.86
(.043) (.034)
DETAIL “A” MAX REF
0.18
(.077)
SEATING
PLANE 0.22 – 0.38 0.13 ± 0.076
(.009 – .015) (.005 ± .003)
0.65
TYP MSOP (MS8) 0802
(.0256)
NOTE:
BSC
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

1619fa

18
 LT1619
U
PACKAGE DESCRIPTION

S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)

.189 – .197
.045 ±.005 (4.801 – 5.004)
.050 BSC NOTE 3
8 7 6 5
N

N
.245
MIN .160 ±.005
.150 – .157
.228 – .244
(3.810 – 3.988)
(5.791 – 6.197)
NOTE 3
1 2 3 N/2 N/2

.030 ±.005
TYP RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4

.010 – .020
× 45° .053 – .069
(0.254 – 0.508)
(1.346 – 1.752)
.004 – .010
.008 – .010
0°– 8° TYP (0.101 – 0.254)
(0.203 – 0.254)

.016 – .050
.014 – .019 .050
(0.406 – 1.270)
(0.355 – 0.483) (1.270)
NOTE: TYP BSC
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) SO8 0502

1619fa

19
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT1619
U
TYPICAL APPLICATIO
VIN T1
4V TO 28V 7 9

C4
1.5µF R3 10 • • 12
100V 5.6k
2 1

5• •4
3 8

6• • 11
C5
1.5µF D2
100V MBRS340T3
VOUT
Q1 D3 5V
D4 FMMT3904 MBRS0530T1 0.5A
Q3
1N4687
MMFT3055VL
4.3V 8 7 6 R5
LOW LEVEL R7 R6 100Ω C6
(IZT = 50µA) VIN DRV GATE
5 30Ω 3.74k 10µF
SENSE 1% C1 10V
LT1619 0.022µF
2
FB
S/S GND VC
1 4 3 R10
C7 R8
R9 1.24k
220pF 0.015Ω
C8 2.2k 1%
1µF C9
16V 2.2nF

C4, C5: VITRAMON VJ1825Y155MXB (1825/X7R)

1619 TA01
C6: TAIYO YUDEN LMK325BJ106MN (1210/X7R)
C8: TAIYO YUDEN EMK316BJ105ML (1206/X7R)
T1: COILTRONICS VP1-0190 (ER11/5, 6 WINDINGS EACH 12.2µH)

Figure 19. 2.5W, 4VIN-28VIN to 5V/0.5A Nonisolated Supply

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1370 500kHz, 6A Switching Regulator Boost, Buck, Flyback, Forward, Inverting; 42V Switch Voltage
LT1372 500kHz, 1.5A Switching Regulator SO-8, 2.7V ≤ VIN ≤ 30V, 42V Switch Voltage
LT1613 1.4MHz, SOT-23 DC/DC Converter Fixed Frequency, 0.9V ≤ VIN ≤ 10V, 36V Switch Voltage
LTC1624 Switching Regulator Controller SO-8, Drives N-Ch MOSFET, 3.5V ≤ VIN ≤ 36V
LT1680 Synchronous Boost Controller Synchronous Operation for High Current/High Efficiency
LT1698 Isolated or Nonisolated 10W to 100W 50% Lower Cost than Quarter Brick and Half Brick Modules
Power Supply Solution with Multiple Outputs Fits the Foot Print
LTC1871 No RSENSE Boost, Flyback, SEPIC Controller 2.5V ≤ VIN ≤ 36V, Current Mode Control, 50kHz to 1MHz
Adjustabe Frequency, MSOP-10
LTC1872 SOT-23 Boost Controller 550kHz Fixed Frequency, Current Mode
LT1946 1.2MHz, 65A DC/DC Converter MSOP-8, 5V to 12V/400mA
LT3710/LT3781 Isolated or Nonisolated 10W to 100W 50% Lower Cost than Quarter Brick and Half Brick Modules
Power Supply Solution with Multiple Outputs Fits the Foot Print

1619fa

Linear Technology Corporation LT/TP 1002 1K REV A • PRINTED IN USA

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