Week 11 Slides PDF

Sequential circuits
M. B. Patil, IIT Bombay

Sequential circuits
* The digital circuits we have seen so far (gates, multiplexer, demultiplexer, encoders,
decoders) are combinatorial in nature, i.e., the output(s) depends only on the
present values of the inputs and not on their past values.

Sequential circuits
* In sequential circuits, the “state” of the circuit is crucial in determining the output
values. For a given input combination, a sequential circuit may produce different
output values, depending on its previous state.

Sequential circuits
* In other words, a sequential circuit has a memory (of its past state) whereas a
combinatorial circuit has no memory.

Sequential circuits
* In other words, a sequential circuit has a memory (of its past state) whereas a
combinatorial circuit has no memory.
* Sequential circuits (together with combinatorial circuits) make it possible to build
several useful applications, such as counters, registers, arithmetic/logic unit (ALU),
all the way to microprocessors.

NAND latch (RS latch)
A A B X1 X2
X1
1 0
0 1
1 1
X2
B
0 0
* A, B: inputs, X1 , X2 : outputs
1
A A B X1 X2
X1
1 0
0 1
1 1
0 X2
B
0 0
* Consider A = 1, B = 0.
1
A A B X1 X2
X1
1 0
0 1
1 1
0 X2
B
0 0
B = 0 ⇒ X2 = 1
1
A A B X1 X2
X1
1 0
0 1
1 1
0 X2
B 1 0 0
B = 0 ⇒ X2 = 1
1
A A B X1 X2
X1
1 0
0 1
1 1
0 X2
B 1 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
1
A 0 A B X1 X2
X1
1 0
0 1
1 1
0 X2
B 1 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
1
A 0 A B X1 X2
X1
1 0 0 1
0 1
1 1
0 X2
B 1 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
Overall, we have X1 = 0, X2 = 1.
01
A 0 A B X1 X2
X1
1 0 0 1
0 1
1 1
10 X2
B 1 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
01
A 10 A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1
10 X2
B 01 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
→ X1 = 1, X2 = 0.
10
A 10 A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1
10 X2
B 01 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
→ X1 = 1, X2 = 0.
* Consider A = B = 1.
10
A 10 A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1
10 X2
B 01 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
→ X1 = 1, X2 = 0.
X1 = A X2 = X2 , X2 = B X1 = X1 ⇒ X1 = X2
10
A X102 A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
10 X2
B X011 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
→ X1 = 1, X2 = 0.
X1 = A X2 = X2 , X2 = B X1 = X1 ⇒ X1 = X2
10
A X102 A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
10 X2
B X011 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
→ X1 = 1, X2 = 0.
X1 = A X2 = X2 , X2 = B X1 = X1 ⇒ X1 = X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.
10
A X102 A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
10 X2
B X011 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
→ X1 = 1, X2 = 0.
X1 = A X2 = X2 , X2 = B X1 = X1 ⇒ X1 = X2
Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.
10
A X102 A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
10 X2
B X011 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
→ X1 = 1, X2 = 0.
X1 = A X2 = X2 , X2 = B X1 = X1 ⇒ X1 = X2
The circuit has “latched in” the previous state.
01
A X102 A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
10 X2
B X011 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
→ X1 = 1, X2 = 0.
X1 = A X2 = X2 , X2 = B X1 = X1 ⇒ X1 = X2
* For A = B = 0, X1 and X2 are both 1. This combination of A and B is not allowed for reasons that will
become clear later.
01
A X102 A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
10 X2
B X011 0 0 1 1
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
→ X1 = 1, X2 = 0.
X1 = A X2 = X2 , X2 = B X1 = X1 ⇒ X1 = X2
* For A = B = 0, X1 and X2 are both 1. This combination of A and B is not allowed for reasons that will
become clear later.
A A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
X2
B invalid
0 0
A A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
X2
B invalid
0 0
* The combination A = 1, B = 0 serves to reset X1 to 0 (irrespective of the previous state of the latch).
A A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
X2
B invalid
0 0
* The combination A = 0, B = 1 serves to set X1 to 1 (irrespective of the previous state of the latch).
A A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
X2
B invalid
0 0
* In other words,
A = 1, B = 0 → latch gets reset to 0.
A = 0, B = 1 → latch gets set to 1.
A A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
X2
B invalid
0 0
* In other words,
* The A input is therefore called the RESET (R) input, and B is called the SET (S) input of the latch.
A A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
X2
B invalid
0 0
* In other words,
* X1 is denoted by Q, and X2 (which is X1 in all cases except for A = B = 0) is denoted by Q.
A A B X1 X2 R R S Q Q
X1 Q
1 0 0 1 1 0 0 1
0 1 1 0 0 1 1 0
1 1 previous 1 1 previous
X2 Q
B invalid S invalid
0 0 0 0
* In other words,
* X1 is denoted by Q, and X2 (which is X1 in all cases except for A = B = 0) is denoted by Q.

R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3

R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3
* Up to t = t1 , R = 0, S = 1 → Q = 1.

R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3
* Up to t = t1 , R = 0, S = 1 → Q = 1.
* At t = t1 , R goes high → R = S = 1, and the latch holds its previous state
→ no change at the output.

R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3
* Up to t = t1 , R = 0, S = 1 → Q = 1.
* At t = t2 , S goes low → R = 1, S = 0 → Q = 0.

R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3
* Up to t = t1 , R = 0, S = 1 → Q = 1.
* At t = t2 , S goes low → R = 1, S = 0 → Q = 0.
* At t = t3 , S goes high → R = S = 1, and the latch holds its previous state

R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3
R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3
Why not allow R = S = 0?

R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3

- It makes Q = Q = 1, i.e., Q and Q are not inverse of each other any more.
R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3

- More importantly, when R and S both become 1 simultaneously (starting from R = S = 0), the final
outputs Q and Q cannot be uniquely determined. We could have Q = 0, Q = 1 or Q = 1, Q = 0,
depending on the delays associated with the two NAND gates.
R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3 t4

R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3 t4

R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3 t4 t5

R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q ?
Q t
S invalid
0 0 Q ?
t
t1 t2 t3 t4 t5

R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q ?
Q t
S invalid
0 0 Q ?
t
t1 t2 t3 t4 t5


NOR latch (RS latch)
R R S Q Q
Q
1 0 0 1
0 1 1 0
0 0 previous
Q
S invalid
1 1

R R S Q Q
Q
1 0 0 1
0 1 1 0
0 0 previous
Q
S invalid
1 1
* The NOR latch is similar to the NAND latch:

When R = 1, S = 0, the latch gets reset to Q = 0.
When R = 0, S = 1, the latch gets set to Q = 1.

R R S Q Q
Q
1 0 0 1
0 1 1 0
0 0 previous
Q
S invalid
1 1

* For R = S = 0, the latch retains its previous state (i.e., the previous values of Q and Q).

R R S Q Q
Q
1 0 0 1
0 1 1 0
0 0 previous
Q
S invalid
1 1

* For R = S = 0, the latch retains its previous state (i.e., the previous values of Q and Q).
* R = S = 1 is not allowed for reasons similar to those discussed in the context of the NAND latch.

Comparison of NAND and NOR latches
R R S Q Q
Q
1 0 0 1
0 1 1 0
1 1 previous
Q
S invalid
0 0
R R S Q Q
Q
1 0 0 1
0 1 1 0
0 0 previous
Q
S invalid
1 1

NAND latch: alternative node names
R R S Q Q
Q
1 0 0 1
0 1 1 0
1 1 previous
Q
S invalid
0 0
NAND latch: alternative node names
R R S Q Q
Q
1 0 0 1
0 1 1 0
1 1 previous
Q
S invalid
0 0
Active low input nodes:
S S R Q Q
Q
1 0 0 1
0 1 1 0
1 1 previous
Q
R invalid
0 0

Chatter (bouncing) due to a mechanical switch
A
Vs R Vo
A
Vs R Vo
* When the switch is thrown from A to B, Vo is expected to go from 0 V to Vs (say, 5 V ).

B
Vo
A
Vs
Vs R Vo
t
expected

B
Vo
A
Vs
Vs R Vo
t
expected

* However, mechanical switches suffer from “chatter” or “bouncing,” i.e., the transition from A to B is not a
single, clean one. As a result, Vo oscillates between 0 V and 5 V before settling to its final value (5 V ).
B
Vo Vo
A
Vs Vs
Vs R Vo
t t
expected actual

B
Vo Vo
A
Vs Vs
Vs R Vo
t t
expected actual

* In some applications, this chatter can cause malfunction → need a way to remove the chatter.

5V
S
R S Q Q
t
R Q 1 0 0 1
B R
0 1 1 0
A t
1 1 previous
S
0 0 invalid Q
t
5V

5V
S
R S Q Q
t
R Q 1 0 0 1
B R
0 1 1 0
A t
1 1 previous
S
0 0 invalid Q
t
5V
* Because of the chatter, the S and R inputs may have multiple transitions when the switch is thrown from
A to B.

5V
S
R S Q Q
t
R Q 1 0 0 1
B R
0 1 1 0
A t
1 1 previous
S
0 0 invalid Q
t
5V
* Because of the chatter, the S and R inputs may have multiple transitions when the switch is thrown from
A to B.
* However, for S = R = 1, the previous value of Q is retained, causing a single transition in Q, as desired.

The “clock”
* Complex digital circuits are generally designed for synchronous operation, i.e., transitions in the various
signals are synchronised with the clock.

The “clock”
* Synchronous circuits are easier to design and troubleshoot because the voltages at the nodes (both output
nodes and internal nodes) can change only at specific times.

The “clock”
* A clock is a periodic signal, with a positive-going transition and a negative-going transition.
positive edge negative edge
0
t
T

The “clock”
0
t
T
* The clock frequency determines the overall speed of the circuit. For example, a processor that operates
with a 1 GHz clock is 10 times faster than one that operates with a 100 MHz clock.

The “clock”
0
t
T
* The clock frequency determines the overall speed of the circuit. For example, a processor that operates
with a 1 GHz clock is 10 times faster than one that operates with a 100 MHz clock.
Intel 80286 (IBM PC-AT): 6 MHz
Modern CPU chips: 2 to 3 GHz.

Clocked RS latch
CLK R S Q Q
S A A B Q Q
previous A
Q 0 X X Q 1 0 0 1
1 1 0 0 1
CLK 0 1 1 0
1 0 1 1 0
1 1 previous
Q 1 0 0 previous Q
B 0 0 invalid
R B invalid
1 1 1
Clocked RS latch NAND RS latch

Clocked RS latch
CLK R S Q Q
S A A B Q Q
previous A
Q 0 X X Q 1 0 0 1
1 1 0 0 1
CLK 0 1 1 0
1 0 1 1 0
1 1 previous
Q 1 0 0 previous Q
B 0 0 invalid
R B invalid
1 1 1
* When clock is inactive (0), A = B = 1, and the latch holds the previous state.

Clocked RS latch
CLK R S Q Q
S A A B Q Q
previous A
Q 0 X X Q 1 0 0 1
1 1 0 0 1
CLK 0 1 1 0
1 0 1 1 0
1 1 previous
Q 1 0 0 previous Q
B 0 0 invalid
R B invalid
1 1 1
* When clock is active (1), A = S, B = R. Using the truth table for the NAND RS latch (right), we can
construct the truth table for the clocked RS latch.

Clocked RS latch
CLK R S Q Q
S A A B Q Q
previous A
Q 0 X X Q 1 0 0 1
1 1 0 0 1
CLK 0 1 1 0
1 0 1 1 0
1 1 previous
Q 1 0 0 previous Q
B 0 0 invalid
R B invalid
1 1 1
* When clock is active (1), A = S, B = R. Using the truth table for the NAND RS latch (right), we can
construct the truth table for the clocked RS latch.
* Note that the above table is sensitive to the level of the clock (i.e., whether CLK is 0 or 1).

Clocked RS latch
CLK R S Q Q
S A
Q 0 X X previous
1 1 0 0 1
CLK
1 0 1 1 0
Q 1 0 0 previous
R B invalid
1 1 1
CLK
0 0.2 0.4 0.6 0.8

time (msec) M. B. Patil, IIT Bombay
Edge-triggered flip-flops
* The clocked RS latch seen previously is level-sensitive, i.e., if the clock is active (CLK = 1), the flip-flop
output is allowed to change, depending on the R and S inputs.

* In an edge-sensitive flip-flop, the output can change only at the active clock edge (i.e., CLK transition
from 0 to 1 or from 1 to 0).

* In an edge-sensitive flip-flop, the output can change only at the active clock edge (i.e., CLK transition
from 0 to 1 or from 1 to 0).
* Edge-sensitive flip-flops are denoted by the following symbols:
R Q R Q
CLK CLK
S Q S Q
positive edge−triggered flip−flop negative edge−triggered flip−flop

JK flip-flop: introduction
R S Q Q R
J
1 0 0 1
Q
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
Truth table for RS latch
R S Q Q R
J
1 0 0 1
Q
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
Truth table for RS latch
* When CLK = 0, we have R = S = 1, and the RS latch holds the previous Q. In other words, nothing
happens as long as CLK = 0.
CLK J K Q (Qn+1 )
R S Q Q R
J 0 X X previous (Qn )
1 0 0 1
Q
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
Truth table for RS latch Truth table for JK flip−flop
CLK J K Q (Qn+1 )
R S Q Q R
1 0 0 1
Q
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
CLK J K Q (Qn+1 )
R S Q Q R
1 0 0 1
Q
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
- J = K = 0 → R = S = 1, RS latch holds previous Q, i.e., Qn+1 = Qn , where n denotes the nth clock
pulse (This notation will become clear shortly).
CLK J K Q (Qn+1 )
R S Q Q R
1 0 0 1
Q
1 0 0 previous (Qn )
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
CLK J K Q (Qn+1 )
R S Q Q R
1 0 0 1
Q
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
- J = 0, K = 1 → R = 1, S = Qn .
CLK J K Q (Qn+1 )
R S Q Q R
1 0 0 1
Q
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
- J = 0, K = 1 → R = 1, S = Qn .
Case (i): Qn = 0 → S = 1 (i.e., R = S = 1) → Qn+1 = Qn = 0.
CLK J K Q (Qn+1 )
R S Q Q R
1 0 0 1
Q
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
- J = 0, K = 1 → R = 1, S = Qn .
Case (ii): Qn = 1 → S = 0 (i.e., R = 1, S = 0) → Qn+1 = 0.
CLK J K Q (Qn+1 )
R S Q Q R
1 0 0 1
Q
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
- J = 0, K = 1 → R = 1, S = Qn .
In either case, Qn+1 = 0 → For J = 0, K = 1, Qn+1 = 0.
CLK J K Q (Qn+1 )
R S Q Q R
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
- J = 0, K = 1 → R = 1, S = Qn .
In either case, Qn+1 = 0 → For J = 0, K = 1, Qn+1 = 0.
CLK J K Q (Qn+1 )
R S Q Q R previous (Qn )
J 0 X X
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
Q
0 0 invalid K
S
RS latch
CLK J K Q (Qn+1 )
J 0 X X
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
- Consider J = 1, K = 0 → S = 1, R = Qn = Qn .
CLK J K Q (Qn+1 )
J 0 X X
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
CLK J K Q (Qn+1 )
J 0 X X
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1 (i.e., R = 1, S = 1) → Qn+1 = Qn = 1.
CLK J K Q (Qn+1 )
J 0 X X
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
→ For J = 1, K = 0, Qn+1 = 1.
CLK J K Q (Qn+1 )
J 0 X X
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
1 1 0 1
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
→ For J = 1, K = 0, Qn+1 = 1.
CLK J K Q (Qn+1 )
J 0 X X
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
1 1 0 1
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
→ For J = 1, K = 0, Qn+1 = 1.
- Consider J = 1, K = 1 → R = Qn , S = Qn .
CLK J K Q (Qn+1 )
J 0 X X
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
1 1 0 1
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
→ For J = 1, K = 0, Qn+1 = 1.
Case (i): Qn = 0 → R = 0, S = 1 → Qn+1 = 1.
CLK J K Q (Qn+1 )
J 0 X X
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
1 1 0 1
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
→ For J = 1, K = 0, Qn+1 = 1.
Case (i): Qn = 0 → R = 0, S = 1 → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1, S = 0 → Qn+1 = 0.
CLK J K Q (Qn+1 )
J 0 X X
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
1 1 0 1
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
→ For J = 1, K = 0, Qn+1 = 1.
Case (i): Qn = 0 → R = 0, S = 1 → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1, S = 0 → Qn+1 = 0.
→ For J = 1, K = 1, Qn+1 = Qn .
CLK J K Q (Qn+1 )
J 0 X X
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
1 1 0 1
Q
0 0 invalid K
S 1 1 1 toggles (Qn )
RS latch
* When CLK = 1:
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
→ For J = 1, K = 0, Qn+1 = 1.
Case (i): Qn = 0 → R = 0, S = 1 → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1, S = 0 → Qn+1 = 0.
→ For J = 1, K = 1, Qn+1 = Qn .
CLK J K Q (Qn+1 )
R previous (Qn )
J 0 X X
Q
CLK 1 0 1 0
1 1 0 1
Q
K
RS latch
Truth table for JK flip−flop
Consider J = K = 1 and CLK = 1.

CLK J K Q (Qn+1 )
R previous (Qn )
J 0 X X
Q
CLK 1 0 1 0
1 1 0 1
Q
K
RS latch

As long as CLK = 1, Q will keep toggling! (The frequency will depend on the delay values of the various gates).

CLK J K Q (Qn+1 )
R previous (Qn )
J 0 X X
Q
CLK 1 0 1 0
1 1 0 1
Q
K
RS latch

As long as CLK = 1, Q will keep toggling! (The frequency will depend on the delay values of the various gates).
→ Use the “Master-slave” configuration.

JK flip-flop (Master-Slave)
Master Slave
J
R1 R2 Q
Q1
Q
K
S1 S2
RS latch 1 RS latch 2
CLK CLK
Master Slave
J
R1 R2 Q
Q1
Q
K
S1 S2
CLK CLK
* When CLK goes high, only the first latch is affected; the second latch retains its previous value (because
CLK = 0 → R2 = S2 = 1).
Master Slave
J
R1 R2 Q
Q1
Q
K
S1 S2
CLK CLK
CLK = 0 → R2 = S2 = 1).
* When CLK goes low, the output of the first latch (Q1 ) is retained (since R1 = S1 = 1), and Q1 can now
affect Q.
Master Slave
J
R1 R2 Q
Q1
Q
K
S1 S2
CLK CLK
CLK = 0 → R2 = S2 = 1).
affect Q.
* In other words, the effect of any changes in J and K appears at the output Q only when CLK makes a
transition from 1 to 0.
This is therefore a negative edge-triggered flip-flop.
Master Slave
CLK J K Qn+1
J
R1 R2 Q 0 0 Qn
Q1
0 1 0
1 0 1
Q
K 1 1 Qn
S1 S2
CLK CLK
CLK = 0 → R2 = S2 = 1).
affect Q.
Master Slave
CLK J K Qn+1
J
R1 R2 Q 0 0 Qn
Q1
0 1 0
1 0 1
Q
K 1 1 Qn
S1 S2
CLK CLK
CLK = 0 → R2 = S2 = 1).
affect Q.
* Note that the JK flip-flop allows all four input combinations.
Master Slave
CLK
t
J
J
R1 R2 Q
Q1 t
K
t
R1
Q
K
S1 S2 t
RS latch 1 RS latch 2 S1
t
CLK CLK Q1
t
R2
CLK J K Qn+1 t
0 0 Qn S2
0 1 0 t
Q
1 0 1
t
1 1 Qn
Master Slave
CLK
t
J
J
R1 R2 Q
Q1 t
K
t
R1
Q
K
S1 S2 t
t
CLK CLK Q1
t
R2
CLK J K Qn+1 t
0 0 Qn S2
0 1 0 t
Q
1 0 1
t
1 1 Qn
Master Slave
CLK
t
J
J
R1 R2 Q
Q1 t
K
t
R1
Q
K
S1 S2 t
t
CLK CLK Q1
t
R2
CLK J K Qn+1 t
0 0 Qn S2
0 1 0 t
Q
1 0 1
t
1 1 Qn
Master Slave
CLK
t
J
J
R1 R2 Q
Q1 t
K
t
R1
Q
K
S1 S2 t
t
CLK CLK Q1
t
R2
CLK J K Qn+1 t
0 0 Qn S2
0 1 0 t
Q
1 0 1
t
1 1 Qn
Master Slave
CLK
t
J
J
R1 R2 Q
Q1 t
K
t
R1
Q
K
S1 S2 t
t
CLK CLK Q1
t
R2
CLK J K Qn+1 t
0 0 Qn S2
0 1 0 t
Q
1 0 1
t
1 1 Qn
Master Slave
CLK
t
J
J
R1 R2 Q
Q1 t
K
t
R1
Q
K
S1 S2 t
t
CLK CLK Q1
t
R2
CLK J K Qn+1 t
0 0 Qn S2
0 1 0 t
Q
1 0 1
t
1 1 Qn
Master Slave
CLK
t
J
J
R1 R2 Q
Q1 t
K
t
R1
Q
K
S1 S2 t
t
CLK CLK Q1
t
R2
CLK J K Qn+1 t
0 0 Qn S2
0 1 0 t
Q
1 0 1
t
1 1 Qn
Master Slave
CLK
t
J
J
R1 R2 Q
Q1 t
K
t
R1
Q
K
S1 S2 t
t
CLK CLK Q1
t
R2
CLK J K Qn+1 t
0 0 Qn S2
0 1 0 t
Q
1 0 1
t
1 1 Qn
Master Slave
CLK
t
J
J
R1 R2 Q
Q1 t
K
t
R1
Q
K
S1 S2 t
t
CLK CLK Q1
t
R2
CLK J K Qn+1 t
0 0 Qn S2
0 1 0 t
Q
1 0 1
t
1 1 Qn

JK flip-flop
CLK J K Qn+1 CLK J K Qn+1

J Q Qn J Q Qn
0 0 0 0
CLK 0 1 0 CLK 0 1 0
K Q 1 0 1 K Q 1 0 1
1 1 Qn 1 1 Qn
positive edge−triggered JK flip−flop negative edge−triggered JK flip−flop

JK flip-flop

J Q Qn J Q Qn
0 0 0 0
CLK 0 1 0 CLK 0 1 0
K Q 1 0 1 K Q 1 0 1
1 1 Qn 1 1 Qn
* Both negative (e.g., 74ALS112A, CD54ACT112) and positive (e.g., 74ALS109A, CD4027) edge-triggered
JK flip-flops are available as ICs.

JK flip-flop
J Q
Q1 CLK
Master Slave
K Q
Q1 t1A t1B t2A t2B
CLK CLK
Consider a negative edge-triggered JK flip-flop.

JK flip-flop
J Q
Q1 CLK
Master Slave
K Q
Q1 t1A t1B t2A t2B
CLK CLK

* As seen earlier, when CLK is high (i.e., t1A < t < t1B , etc.), the input J and K determine the Master
latch output Q1 .
During this time, no change is visible at the flip-flop output Q.

JK flip-flop
J Q
Q1 CLK
Master Slave
K Q
Q1 t1A t1B t2A t2B
CLK CLK

latch output Q1 .
* When the clock goes low, the Slave flip-flop becomes active, making it possible for Q to change.

JK flip-flop
J Q
Q1 CLK
Master Slave
K Q
Q1 t1A t1B t2A t2B
CLK CLK

latch output Q1 .
* In short, although the flip-flop output Q can only change after the active edge, (t1B , t2B , etc.), the new Q
value is determined by J and K values just before the active edge.

JK flip-flop
J Q
Q1 CLK
Master Slave
K Q
Q1 t1A t1B t2A t2B
CLK CLK

latch output Q1 .
* In short, although the flip-flop output Q can only change after the active edge, (t1B , t2B , etc.), the new Q
value is determined by J and K values just before the active edge.
This is a very important point!

JK flip-flop
CLK J K Qn+1
J Q Qn
0 0
CLK 0 1 0
K Q 1 0 1
1 1 Qn
positive edge−triggered JK flip−flop
CLK
0 0.1 0.2 0.3 0.4 0.5 0.6

time (msec)
JK flip-flop

J Q Qn Q
0 0 J
0 0 Qn
CLK 0 1 0 CLK 0 1 0
K Q 1 0 1 1 0 1
K Q
1 1 Qn 1 1 Qn
CLK CLK
J J
K K
Q Q
0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6
time (msec) time (msec)
JK flip-flop
J1 = K1 = 1. Assume Q1 = Q2 = 0 initially.
J1 Q1 J2 CLK
1 J Q J Q Q2
t
Q1
K Q K Q
K1 K2
t
CLK Q2
CLK J K Qn+1
t
0 0 Qn t1 t2 t3 t4 t5
0 1 0
1 0 1
1 1 Qn
JK flip-flop
J1 Q1 J2 CLK
1 J Q J Q Q2
t
Q1
K Q K Q
K1 K2
t
CLK Q2
CLK J K Qn+1
t
0 0 Qn t1 t2 t3 t4 t5
0 1 0
1 0 1
1 1 Qn
* Since J1 = K1 = 1, Q1 toggles after every active clock edge.

JK flip-flop
J1 Q1 J2 CLK
1 J Q J Q Q2
t
Q1
K Q K Q
K1 K2
t
CLK Q2
CLK J K Qn+1
t
0 0 Qn t1 t2 t3 t4 t5
0 1 0
1 0 1
1 1 Qn

JK flip-flop
J1 Q1 J2 CLK
1 J Q J Q Q2
t
Q1
K Q K Q
K1 K2
t
CLK Q2
CLK J K Qn+1
t
0 0 Qn t1 t2 t3 t4 t5
0 1 0
1 0 1
1 1 Qn

* J2 = Q1 , K2 = Q1 . We need to look at J2 and K2 values just before the active edge, to determine the next value of Q2 .
JK flip-flop
J1 Q1 J2 CLK
1 J Q J Q Q2
t
Q1
K Q K Q
K1 K2
t
CLK Q2
CLK J K Qn+1
t
0 0 Qn t1 t2 t3 t4 t5
0 1 0
1 0 1
1 1 Qn

* It is convenient to construct a table listing J2 and K2 to figure out the next Q2 value.
JK flip-flop
J1 Q1 J2
1 J Q J Q Q2 CLK t J2 (t = t− −
k ) K2 (t = tk ) Q2 (t = t+
k)
t1 0 1 0
t
Q1 t2 1 0 1
K Q K Q
K1 K2 t3 0 1 0
t
CLK Q2 t4 1 0 1
CLK J K Qn+1 t5 0 1 0
t
0 0 Qn t1 t2 t3 t4 t5
0 1 0
1 0 1
1 1 Qn

JK flip-flop
J1 Q1 J2
1 J Q J Q Q2 CLK t J2 (t = t− −
k ) K2 (t = tk ) Q2 (t = t+
k)
t1 0 1 0
t
Q1 t2 1 0 1
K Q K Q
K1 K2 t3 0 1 0
t
CLK Q2 t4 1 0 1
CLK J K Qn+1 t5 0 1 0
t
0 0 Qn t1 t2 t3 t4 t5
0 1 0
1 0 1
1 1 Qn


CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
0 0 0 0 0
0 1 0
K Q K Q K Q 1 0 1
1 1 1
1 1 Qn
CLK
CLK
t
Q0
t
Q1
t
Q2
t
t1 t2 t3 t4 t5
CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
0 0 0 0 0
0 1 0
K Q K Q K Q 1 0 1
1 1 1
1 1 Qn
CLK
CLK
tk − tk +
t Q0 Q1 Q2 J0 K0 J1 K1 J2 K2 Q0 Q1 Q2 t
Q0
t1 0 0 0 1 0 1 1 0 1
t2 t
Q1
t3
t4 t
Q2
t5
t
t1 t2 t3 t4 t5
CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
0 0 0 0 0
0 1 0
K Q K Q K Q 1 0 1
1 1 1
1 1 Qn
CLK
CLK
tk − tk +
t Q0 Q1 Q2 J0 K0 J1 K1 J2 K2 Q0 Q1 Q2 t
Q0
t1 0 0 0 1 0 1 1 0 1 1 1 0
t2 t
Q1
t3
t4 t
Q2
t5
t
t1 t2 t3 t4 t5
CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
0
1 0
1 0 0 0
0 1 0
K Q K Q K Q 1 0 1
1
0 1
0 1
1 1 Qn
CLK
CLK
tk − tk +
t Q0 Q1 Q2 J0 K0 J1 K1 J2 K2 Q0 Q1 Q2 t
Q0
t1 0 0 0 1 0 1 1 0 1 1 1 0
t2 1 1 0 1 0 0 0 1 0 t
Q1
t3
t4 t
Q2
t5
t
t1 t2 t3 t4 t5
CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
0
1 0
1 0 0 0
0 1 0
K Q K Q K Q 1 0 1
1
0 1
0 1
1 1 Qn
CLK
CLK
tk − tk +
t Q0 Q1 Q2 J0 K0 J1 K1 J2 K2 Q0 Q1 Q2 t
Q0
t1 0 0 0 1 0 1 1 0 1 1 1 0
t2 1 1 0 1 0 0 0 1 0 1 1 1 t
Q1
t3
t4 t
Q2
t5
t
t1 t2 t3 t4 t5
CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
0
1 0
1 1
0 0 0
0 1 0
K Q K Q K Q 1 0 1
1
0 1
0 0
1
1 1 Qn
CLK
CLK
tk − tk +
t Q0 Q1 Q2 J0 K0 J1 K1 J2 K2 Q0 Q1 Q2 t
Q0
t1 0 0 0 1 0 1 1 0 1 1 1 0
t2 1 1 0 1 0 0 0 1 0 1 1 1 t
Q1
t3 1 1 1 1 1 0 0 1 0
t4 t
Q2
t5
t
t1 t2 t3 t4 t5
CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
0
1 0
1 1
0 0 0
0 1 0
K Q K Q K Q 1 0 1
1
0 1
0 0
1
1 1 Qn
CLK
CLK
tk − tk +
t Q0 Q1 Q2 J0 K0 J1 K1 J2 K2 Q0 Q1 Q2 t
Q0
t1 0 0 0 1 0 1 1 0 1 1 1 0
t2 1 1 0 1 0 0 0 1 0 1 1 1 t
Q1
t3 1 1 1 1 1 0 0 1 0 0 1 1
t4 t
Q2
t5
t
t1 t2 t3 t4 t5
CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
0
1 0
1 0
1 0 0
0 1 0
K Q K Q K Q 1 0 1
1
0 1
0 1
0
1 1 Qn
CLK
CLK
tk − tk +
t Q0 Q1 Q2 J0 K0 J1 K1 J2 K2 Q0 Q1 Q2 t
Q0
t1 0 0 0 1 0 1 1 0 1 1 1 0
t2 1 1 0 1 0 0 0 1 0 1 1 1 t
Q1
t3 1 1 1 1 1 0 0 1 0 0 1 1
t4 0 1 1 1 1 1 1 0 0 t
Q2
t5
t
t1 t2 t3 t4 t5
CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
0
1 0
1 0
1 0 0
0 1 0
K Q K Q K Q 1 0 1
1
0 1
0 1
0
1 1 Qn
CLK
CLK
tk − tk +
t Q0 Q1 Q2 J0 K0 J1 K1 J2 K2 Q0 Q1 Q2 t
Q0
t1 0 0 0 1 0 1 1 0 1 1 1 0
t2 1 1 0 1 0 0 0 1 0 1 1 1 t
Q1
t3 1 1 1 1 1 0 0 1 0 0 1 1
t4 0 1 1 1 1 1 1 0 0 1 0 1 t
Q2
t5
t
t1 t2 t3 t4 t5
CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
1
0 0
1 0
1 0 0
0 1 0
K Q K Q K Q 1 0 1
0
1 1
0 1
0
1 1 Qn
CLK
CLK
tk − tk +
t Q0 Q1 Q2 J0 K0 J1 K1 J2 K2 Q0 Q1 Q2 t
Q0
t1 0 0 0 1 0 1 1 0 1 1 1 0
t2 1 1 0 1 0 0 0 1 0 1 1 1 t
Q1
t3 1 1 1 1 1 0 0 1 0 0 1 1
t4 0 1 1 1 1 1 1 0 0 1 0 1 t
Q2
t5 1 0 1 1 1 0 0 1 1
t
t1 t2 t3 t4 t5
CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
1
0 0
1 0
1 0 0
0 1 0
K Q K Q K Q 1 0 1
0
1 1
0 1
0
1 1 Qn
CLK
CLK
tk − tk +
t Q0 Q1 Q2 J0 K0 J1 K1 J2 K2 Q0 Q1 Q2 t
Q0
t1 0 0 0 1 0 1 1 0 1 1 1 0
t2 1 1 0 1 0 0 0 1 0 1 1 1 t
Q1
t3 1 1 1 1 1 0 0 1 0 0 1 1
t4 0 1 1 1 1 1 1 0 0 1 0 1 t
Q2
t5 1 0 1 1 1 0 0 1 1 0 0 0
t
t1 t2 t3 t4 t5
CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
0
1 1
0 0
1 0 0
0 1 0
K Q K Q K Q 1 0 1
1
0 0
1 1
0
1 1 Qn
CLK
CLK
tk − tk +
t Q0 Q1 Q2 J0 K0 J1 K1 J2 K2 Q0 Q1 Q2 t
Q0
t1 0 0 0 1 0 1 1 0 1 1 1 0
t2 1 1 0 1 0 0 0 1 0 1 1 1 t
Q1
t3 1 1 1 1 1 0 0 1 0 0 1 1
t4 0 1 1 1 1 1 1 0 0 1 0 1 t
Q2
t5 1 0 1 1 1 0 0 1 1 0 0 0
t
t1 t2 t3 t4 t5

JK flip-flop: asynchronous inputs
Sd Rd CLK J K Qn+1
0 1 X X X 0
Rd Q 1 0 X X X 1
J
1 1 X X X invalid
CLK
0 0 0 0 Qn
K Sd Q 0 0 0 1 0 normal
0 0 1 0 1 operation
0 0 1 1 Qn

Sd Rd CLK J K Qn+1
0 1 X X X 0
Rd Q 1 0 X X X 1
J
1 1 X X X invalid
CLK
0 0 0 0 Qn
0 0 1 0 1 operation
0 0 1 1 Qn
* Clocked flip-flops are also provided with asynchronous or direct Set and Reset inputs, Sd and Rd , (also
called Preset and Clear, respectively) which override all other inputs (J, K, CLK).

Sd Rd CLK J K Qn+1
0 1 X X X 0
Rd Q 1 0 X X X 1
J
1 1 X X X invalid
CLK
0 0 0 0 Qn
0 0 1 0 1 operation
0 0 1 1 Qn
* The Sd and Rd inputs may be active low; in that case, they are denoted by Sd and Rd .

Sd Rd CLK J K Qn+1
0 1 X X X 0
Rd Q 1 0 X X X 1
J
1 1 X X X invalid
CLK
0 0 0 0 Qn
0 0 1 0 1 operation
0 0 1 1 Qn
* The Sd and Rd inputs may be active low; in that case, they are denoted by Sd and Rd .
* The asynchronous inputs are convenient for starting up a circuit in a known state.

D flip-flop
CLK
D Q D J Q t
CLK D Qn+1
D
CLK 0 0 CLK
1 1 t
Q K Q Q
positive edge−triggered D flip−flop

t
t1 t2 t3 t4 t5
CLK
D Q D J Q t
CLK D Qn+1
D
CLK 0 0 CLK
1 1 t
Q K Q Q
negative edge−triggered D flip−flop

t
t1 t2 t3 t4 t5

D flip-flop
CLK
D Q D J Q t
CLK D Qn+1
D
CLK 0 0 CLK
1 1 t
Q K Q Q

t
t1 t2 t3 t4 t5
CLK
D Q D J Q t
CLK D Qn+1
D
CLK 0 0 CLK
1 1 t
Q K Q Q

t
t1 t2 t3 t4 t5
* The D flip-flop can be used to delay the Data (D) signal by one clock period.

D flip-flop
CLK
D Q D J Q t
CLK D Qn+1
D
CLK 0 0 CLK
1 1 t
Q K Q Q

t
t1 t2 t3 t4 t5
CLK
D Q D J Q t
CLK D Qn+1
D
CLK 0 0 CLK
1 1 t
Q K Q Q

t
t1 t2 t3 t4 t5
* With J = D, K = D, we have either J = 0, K = 1 or J = 1, K = 0; the next Q is 0 in the first case, 1 in the second case.

D flip-flop
CLK
D Q D J Q t
CLK D Qn+1
D
CLK 0 0 CLK
1 1 t
Q K Q Q

t
t1 t2 t3 t4 t5
CLK
D Q D J Q t
CLK D Qn+1
D
CLK 0 0 CLK
1 1 t
Q K Q Q

t
t1 t2 t3 t4 t5
* With J = D, K = D, we have either J = 0, K = 1 or J = 1, K = 0; the next Q is 0 in the first case, 1 in the second case.
* Instead of a JK flip-flop, an RS flip-flop can also be used to make a D flip-flop, with S = D, R = D.
Shift register
Q1 Q2 Q3
D D Q D Q D Q D Q Q4 CLK D Qn+1
0 0 0 0 0 0
Q Q Q Q 1 1
CLK
CLK
Q1
Q2
Q3
Q4
Shift register
Q1 Q2 Q3
0
1 0 0 0 0 0
Q Q Q Q 1 1
CLK
CLK
Q1
Q2
Q3
Q4
Shift register
Q1 Q2 Q3
0
1 0
1 0 0 0 0
Q Q Q Q 1 1
CLK
CLK
Q1
Q2
Q3
Q4
Shift register
Q1 Q2 Q3
0
1 0
1 0
1 0 0 0
Q Q Q Q 1 1
CLK
CLK
Q1
Q2
Q3
Q4
Shift register
Q1 Q2 Q3
0
1 0
1 0
1 0
1 0 0
Q Q Q Q 1 1
CLK
CLK
Q1
Q2
Q3
Q4
Shift register
Q1 Q2 Q3
0
1 0
1 0
1 0
1 0 0
Q Q Q Q 1 1
CLK
CLK
Q1
Q2
Q3
Q4
Shift register
Q1 Q2 Q3
0
1 0
1 0
1 0
1 0 0
Q Q Q Q 1 1
CLK
CLK
Q1
Q2
Q3
Q4
Shift register
Q1 Q2 Q3
0
1 0
1 0
1 0
1 0 0
Q Q Q Q 1 1
CLK
CLK
Q1
Q2
Q3
Q4
Shift register
Q1 Q2 Q3
0
1 0
1 0
1 0
1 0 0
Q Q Q Q 1 1
CLK
CLK
Q1
Q2
Q3
Q4
Shift register
Q1 Q2 Q3
0
1 0
1 0
1 0
1 0 0
Q Q Q Q 1 1
CLK
CLK
Q1
Q2
Q3
Q4
SEQUEL file: ee101 shift reg 1.sqproj

Parallel transfer between shift registers
A3 A2 A1 A0
D Q D Q D Q D Q
Q Q Q Q
Register A A3 A2 A1 A0
B3 B2 B1 B0 Register B B3 B2 B1 B0
D Q D Q D Q D Q
Q Q Q Q
CLK

Parallel transfer between shift registers
A3 A2 A1 A0
D Q D Q D Q D Q
Q Q Q Q
Register A A3 A2 A1 A0
B3 B2 B1 B0 Register B B3 B2 B1 B0
D Q D Q D Q D Q
Q Q Q Q
CLK
* After the active clock edge, the contents of the A register (A3 A2 A1 A0 ) are copied to the B register.

Bidirectional shift register
D0 Q0 D1 Q1 D2 Q2 D3 Q3
D Q D Q D Q D Q
DR
Q Q Q Q
DL
M
CLK

D0 Q0 D1 Q1 D2 Q2 D3 Q3
D Q D Q D Q D Q
DR
Q Q Q Q
DL
M
CLK
* When the mode input (M) is 1, we have

D0 = DR , D1 = Q0 , D2 = Q1 , D3 = Q2 .

D0 Q0 D1 Q1 D2 Q2 D3 Q3
D Q D Q D Q D Q
DR
Q Q Q Q
DL
M
CLK

D0 = DR , D1 = Q0 , D2 = Q1 , D3 = Q2 .
D0 = Q1 , D1 = Q2 , D2 = Q3 , D3 = DL .

D0 Q0 D1 Q1 D2 Q2 D3 Q3
D Q D Q D Q D Q
DR
Q Q Q Q
DL
M
CLK

D0 = DR , D1 = Q0 , D2 = Q1 , D3 = Q2 .
D0 = Q1 , D1 = Q2 , D2 = Q3 , D3 = DL .
* M = 1 → shift right operation.
M = 0 → shift left operation.

Shift left operation
27 26 25 24 23 22 21 20
original dec. 13
0 0 0 0 1 1 0 1 0
number
27 26 25 24 23 22 21 20
original dec. 13
0 0 0 0 1 1 0 1 0
number
after
shift left 0 0 0 1 1 0 1 0 dec. 26
27 26 25 24 23 22 21 20
original dec. 13
0 0 0 0 1 1 0 1 0
number
after
shift left 0 0 0 1 1 0 1 0 dec. 26
Shift left → × 2

Multiplication using shift and add
1 0 1 1 A3 A2 A1 A0 (decimal 11)
1 1 0 1 B3 B2 B1 B0 (decimal 13)
1 0 1 1 since B0 = 1
0 0 0 0 Z since B1 = 0
0 1 0 1 1 addition
1 0 1 1 Z Z since B2 = 1
1 1 0 1 1 1 addition
1 0 1 1 Z Z Z since B3 = 1
1 0 0 0 1 1 1 1 addition (decimal 143)
Note that Z = 0. We use Z to denote 0s which are

independent of the numbers being multiplied.
1 0 1 1 A3 A2 A1 A0 (decimal 11) Register 2 Register 1
1 1 0 1 B3 B2 B1 B0 (decimal 13) Z Z Z Z Z Z Z Z initialize
1 0 1 1 since B0 = 1
0 0 0 0 Z since B1 = 0
0 1 0 1 1 addition
1 0 1 1 Z Z since B2 = 1
1 0 1 1 Z Z Z since B3 = 1

1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
0 1 0 1 1 addition
1 0 1 1 Z Z since B2 = 1
1 0 1 1 Z Z Z since B3 = 1

1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
1 0 1 1 Z Z Z Z add
0 1 0 1 1 addition
1 0 1 1 Z Z since B2 = 1
1 0 1 1 Z Z Z since B3 = 1

1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
1 0 1 1 Z Z Z Z add
0 1 0 1 1 addition
1 0 1 1 Z Z since B2 = 1 Z 1 0 1 1 Z Z Z shift
1 0 1 1 Z Z Z since B3 = 1

1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
1 0 1 1 Z Z Z Z add
0 1 0 1 1 addition
1 1 0 1 1 1 addition load 0000
0 0 0 0
1 0 1 1 Z Z Z since B3 = 1 since B1 = 0

1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
1 0 1 1 Z Z Z Z add
0 1 0 1 1 addition
0 0 0 0
1 0 0 0 1 1 1 1 addition (decimal 143) 0 1 0 1 1 Z Z Z add

1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
1 0 1 1 Z Z Z Z add
0 1 0 1 1 addition
0 0 0 0
Z 0 1 0 1 1 Z Z shift
1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
1 0 1 1 Z Z Z Z add
0 1 0 1 1 addition
0 0 0 0
Z 0 1 0 1 1 Z Z shift
independent of the numbers being multiplied. 1 0 1 1 load 1011
since B2 = 1
1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
1 0 1 1 Z Z Z Z add
0 1 0 1 1 addition
0 0 0 0
Z 0 1 0 1 1 Z Z shift
since B2 = 1
1 1 0 1 1 1 Z Z add
1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
1 0 1 1 Z Z Z Z add
0 1 0 1 1 addition
0 0 0 0
Z 0 1 0 1 1 Z Z shift
since B2 = 1
1 1 0 1 1 1 Z Z add
Z 1 1 0 1 1 1 Z shift
1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
1 0 1 1 Z Z Z Z add
0 1 0 1 1 addition
0 0 0 0
Z 0 1 0 1 1 Z Z shift
since B2 = 1
1 1 0 1 1 1 Z Z add
Z 1 1 0 1 1 1 Z shift
1 0 1 1 load 1011
since B3 = 1
1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
1 0 1 1 Z Z Z Z add
0 1 0 1 1 addition
0 0 0 0
Z 0 1 0 1 1 Z Z shift
since B2 = 1
1 1 0 1 1 1 Z Z add
Z 1 1 0 1 1 1 Z shift
1 0 1 1 load 1011
since B3 = 1
1 0 0 0 1 1 1 1 Z add
1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
1 0 1 1 Z Z Z Z add
0 1 0 1 1 addition
0 0 0 0
Z 0 1 0 1 1 Z Z shift
since B2 = 1
1 1 0 1 1 1 Z Z add
Z 1 1 0 1 1 1 Z shift
1 0 1 1 load 1011
since B3 = 1
1 0 0 0 1 1 1 1 Z add
Z 1 0 0 0 1 1 1 1 shift
Load
A3 A2 A1 A0
0 J
S d Q Q3 J S d Q Q2 J S d Q Q1 J Sd Q Q0
1 K Rd Q K Rd Q K Rd Q K Rd Q
Clear
CLK
Clear
t
Load
t
CLK
t
Q0 = A 0 Q0 = A1 Q0 = A 2 Q0 = A3
Load
A3 A2 A1 A0
0 J
Clear
CLK
Clear
t
Load
t
CLK
t
Q0 = A 0 Q0 = A1 Q0 = A 2 Q0 = A3
* All flip-flops are cleared in the beginning (with Rd = Clear = 1, Sd = 0).
Load
A3 A2 A1 A0
0 J
Clear
CLK
Clear
t
Load
t
CLK
t
Q0 = A 0 Q0 = A1 Q0 = A 2 Q0 = A3
* When Load = 1, Sd = Ai , Rd = 0 → Ai gets loaded into the i th flip-flop.
Load
A3 A2 A1 A0
0 J
Clear
CLK
Clear
t
Load
t
CLK
t
Q0 = A 0 Q0 = A1 Q0 = A 2 Q0 = A3
* Subsequently, with every clock pulse, the data shifts right and appears serially at the output Q0 .
→ parallel in-serial out data movement
Load
A3 A2 A1 A0
0 J
Clear
CLK
Clear
t
Load
t
CLK
t
Q0 = A 0 Q0 = A1 Q0 = A 2 Q0 = A3
Load
A3 A2 A1 A0
0 J
Clear
CLK
Clear
t
Load
t
CLK
t
Q0 = A 0 Q0 = A1 Q0 = A 2 Q0 = A3
Load
A3 A2 A1 A0
0 J
Clear
CLK
Clear 0 0
t
Load
t
CLK
t
Q0 = A 0 Q0 = A1 Q0 = A 2 Q0 = A3
Load
A3 A2 A1 A0
0 J
Clear
CLK
Clear 0 0 0
t
Load
t
CLK
t
Q0 = A 0 Q0 = A1 Q0 = A 2 Q0 = A3
Load
A3 A2 A1 A0
0 J
Clear
CLK
Clear 0 0 0 0
t
Load
t
CLK
t
Q0 = A 0 Q0 = A1 Q0 = A 2 Q0 = A3
Load
A3 A2 A1 A0
0 J
Clear
CLK
Clear 0 0 0 0 0
t
Load
t
CLK
t
Q0 = A 0 Q0 = A1 Q0 = A 2 Q0 = A3
Counters
Q0
1
Q1
k 2 Q2
Clock Counter
3 QN−1
Reset
Decoding
4
logic
State transition diagram General configuration

Counters
Q0
1
Q1
k 2 Q2
Clock Counter
3 QN−1
Reset
Decoding
4
logic
* A counter with k states is called a modulo-k (mod-k) counter.

Counters
Q0
1
Q1
k 2 Q2
Clock Counter
3 QN−1
Reset
Decoding
4
logic

* A counter can be made with flip-flops, each flip-flop serving as a memory element with two states (0 or 1).

Counters
Q0
1
Q1
k 2 Q2
Clock Counter
3 QN−1
Reset
Decoding
4
logic

* If there are N flip-flops in a counter, there are 2N possible states (since each flip-flop can have Q = 0 or
Q = 1). It is possible to exclude some of these states.
→ N flip-flops can be used to make a mod-k counter with k ≤ 2N .

Counters
Q0
1
Q1
k 2 Q2
Clock Counter
3 QN−1
Reset
Decoding
4
logic

* If there are N flip-flops in a counter, there are 2N possible states (since each flip-flop can have Q = 0 or
Q = 1). It is possible to exclude some of these states.
→ N flip-flops can be used to make a mod-k counter with k ≤ 2N .
* Typically, a reset facility is also provided, which can be used to force a certain state to initialize the
counter.
Counters: example
Q0 Q1 Q2
1 J Q J Q J Q
0 0 0
1
K Q K Q K Q
1 1 1
k 2
CLK
3 CLK
state Q0 Q1 Q2
t 1 0 0 0
Q0
4 0 1 1 0 1 0 2 1 1 0
t 3 1 1 1
Q1
0 1 1 1 0 0 4 0 1 1
State transition diagram
t 5 1 0 1
Q2
0 0 1 1 1 0 1 0 0 0
t
t1 t2 t3 t4 t5

Counters
Q0
1
Q1
k 2 Q2
Clock Counter
3 QN−1
Reset
Decoding
4
logic
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1
CLK
t
X
t
8T
X is 1 for state 3; else, it is 0.

Counters
Q0
1
Q1
k 2 Q2
Clock Counter
3 QN−1
Reset
Decoding
4
logic
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1
CLK
t
X
t
8T
* The counter outputs (i.e., the flip-flop outputs, Q0 , Q1 , · · · QN−1 ) can be decoded using appropriate logic.

Counters
Q0
1
Q1
k 2 Q2
Clock Counter
3 QN−1
Reset
Decoding
4
logic
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1
CLK
t
X
t
8T
* The counter outputs (i.e., the flip-flop outputs, Q0 , Q1 , · · · QN−1 ) can be decoded using appropriate logic.
* In particular, it is possible to have a decoder output (say, X ) which is 1 only for state i, and 0 otherwise.
→ For k clock pulses, we get a single pulse at X , i.e., the clock frequency has been divided by k. For this reason, a
mod-k counter is also called a divide-by-k counter.
A binary ripple counter
1
Q0 Q1 Q2
J Q J Q J Q
CLK FF0 FF1 FF2
K Q K Q K Q
CLK
t
Q0
t
Q1
t
Q2
t
1
Q0 Q1 Q2
J Q J Q J Q
CLK FF0 FF1 FF2
K Q K Q K Q
CLK
t
Q0
t
Q1
t
Q2
t
* J = K = 1 for all flip-flops. Let Q0 = Q1 = Q2 = 0 initially.
1
Q0 Q1 Q2
J Q J Q J Q
CLK FF0 FF1 FF2
K Q K Q K Q
CLK
t
Q0
t
Q1
t
Q2
t
* Since J = K = 1, each flip-flop will toggle when an active (in this case, negative) clock edge arrives.
1
Q0 Q1 Q2
J Q J Q J Q
CLK FF0 FF1 FF2
K Q K Q K Q
CLK
t
Q0
t
Q1
t
Q2
t
* For FF1 and FF2, Q0 and Q1 , respectively, provide the clock.
1
Q0 Q1 Q2
J Q J Q J Q
CLK FF0 FF1 FF2
K Q K Q K Q
CLK
t
Q0
t
Q1
t
Q2
t
1
Q0 Q1 Q2
J Q J Q J Q
CLK FF0 FF1 FF2
K Q K Q K Q
CLK
t
Q0
t
Q1
t
Q2
t
1
Q0 Q1 Q2
J Q J Q J Q
CLK FF0 FF1 FF2
K Q K Q K Q
CLK
t
Q0
t
Q1
t
Q2
t
1
Q0 Q1 Q2
J Q J Q J Q
CLK FF0 FF1 FF2 Q2 Q1 Q0
K Q K Q K Q 0 0 0
0 0 1
0 1 0
CLK
0 1 1
1 0 0
t
Q0 1 0 1
1 1 0
t 1 1 1
Q1
0 0 0 repeats
t
Q2
t
1
Q0 Q1 Q2
J Q J Q J Q
K Q K Q K Q 0 0 0
0 0 1
0 1 0
CLK
0 1 1
1 0 0
t
Q0 1 0 1
1 1 0
t 1 1 1
Q1
0 0 0 repeats
t
Q2
t
* Note that the direct inputs Sd and Rd (not shown) are assumed to be Sd = Rd = 0 for all flip-flops, allowing normal
flip-flip operation. M. B. Patil, IIT Bombay
1
Q0 Q1 Q2
J Q J Q J Q
K Q K Q K Q 0 0 0
0 0 1
0 1 0
CLK
0 1 1
1 0 0
t
Q0 1 0 1
1 1 0
t 1 1 1
Q1
0 0 0 repeats
t
Q2

1
Q0 Q1 Q2
J Q J Q J Q
K Q K Q K Q 0 0 0
0 0 1
0 1 0
CLK
0 1 1
1 0 0
t
Q0 1 0 1
1 1 0
t 1 1 1
Q1
0 0 0 repeats
t
Q2
t
* The counter has 8 states, Q2 Q1 Q0 = 000, 001, 010, 011, 100, 101, 110, 111.
→ it is a mod-8 counter. In particular, it is a binary, mod-8, up counter (since it counts up from 000 to 111).

1
Q0 Q1 Q2
J Q J Q J Q
K Q K Q K Q 0 0 0
0 0 1
0 1 0
CLK
0 1 1
1 0 0
t
Q0 1 0 1
1 1 0
t 1 1 1
Q1
0 0 0 repeats
t
Q2
t
* If the clock frequency is fc , the frequency at the Q0 , Q1 , Q2 outputs is fc /2, fc /4, fc /8, respectively. For this counter,
therefore, div-by-2, div-by-4, div-by-8 outputs are already available, without requiring decoding logic.
1
Q0 Q1 Q2
J Q J Q J Q
K Q K Q K Q 0 0 0
0 0 1
0 1 0
CLK
0 1 1
1 0 0
t
Q0 1 0 1
1 1 0
t 1 1 1
Q1
0 0 0 repeats
t
Q2
t
* If the clock frequency is fc , the frequency at the Q0 , Q1 , Q2 outputs is fc /2, fc /4, fc /8, respectively. For this counter,
therefore, div-by-2, div-by-4, div-by-8 outputs are already available, without requiring decoding logic.
* This type of counter is called a “ripple” counter since the clock transitions ripple through the flip-flops. M. B. Patil, IIT Bombay
1
Q0 Q1 Q2
J Q J Q J Q
K Q K Q K Q 0 0 0
1 1 1
1 1 0
CLK
1 0 1
1 0 0
t
Q0 0 1 1
0 1 0
t 0 0 1
Q1
0 0 0 repeats
t
Q2

1
Q0 Q1 Q2
J Q J Q J Q
K Q K Q K Q 0 0 0
1 1 1
1 1 0
CLK
1 0 1
1 0 0
t
Q0 0 1 1
0 1 0
t 0 0 1
Q1
0 0 0 repeats
t
Q2
* If positive edge-triggered flip-flops are used, we get a binary down counter (counting down from 111 to 000).

Binary ripple counters
1
Q0 Q1 Q2
J Q J Q J Q
CLK FF0 FF1 FF2
K Q K Q K Q
1
Q0 Q1 Q2
J Q J Q J Q
CLK FF0 FF1 FF2
K Q K Q K Q
* Home work: Sketch the waveforms (CLK, Q0 , Q1 , Q2 ), and tabulate the counter states in each case.

Up-down binary ripple counters
1
M
J Q J Q J Q
Q0 Q1 Q2
CLK FF0 FF1 FF2
K Q K Q K Q
M
M=1 M=0
CLK CLK
t t
Q0 Q0
t t
Q1 Q1
t t
Q2 Q2
t t

Up-down binary ripple counters
1
M
J Q J Q J Q
Q0 Q1 Q2
CLK FF0 FF1 FF2
K Q K Q K Q
M
M=1 M=0
CLK CLK
t t
Q0 Q0
t t
Q1 Q1
t t
Q2 Q2
t t
* When Mode (M) = 1, the counter counts up; else, it counts down. (SEQUEL file: ee101 counter 3.sqproj)
0
1 Decade counter using direct inputs
Sd Q0 Sd Q1 Sd Q2 Sd Q3
J Q J Q J Q J Q
CLK FF0 FF1 FF2 FF3
K Rd Q K Rd Q K Rd Q K Rd Q
Q3 Q2 Q1 Q0
0 0 0 0
Q0 0 0 0 1
0 0 1 0
0 0 1 1
Q1 0 1 0 0
0 1 0 1
0 1 1 0
Q2
0 1 1 1
1 0 0 0
Q3 1 0 0 1
0 0 0 0 repeats
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 SEQUEL file: ee101 counter 5.sqproj
0
J Q J Q J Q J Q * When the counter reaches
Q3 Q2 Q1 Q0 = 1010 (i.e., decimal 10),
CLK FF0 FF1 FF2 FF3 Q3 Q1 = 1, and the flip-flops are
cleared to Q3 Q2 Q1 Q0 = 0000.
K Rd Q K Rd Q K Rd Q K Rd Q
Q3 Q2 Q1 Q0
0 0 0 0
Q0 0 0 0 1
0 0 1 0
0 0 1 1
Q1 0 1 0 0
0 1 0 1
0 1 1 0
Q2
0 1 1 1
1 0 0 0
Q3 1 0 0 1
0 0 0 0 repeats
0
J Q J Q J Q J Q * When the counter reaches
Q3 Q2 Q1 Q0 = 1010 (i.e., decimal 10),
CLK FF0 FF1 FF2 FF3 Q3 Q1 = 1, and the flip-flops are
cleared to Q3 Q2 Q1 Q0 = 0000.
K Rd Q K Rd Q K Rd Q K Rd Q * The counter counts from 0000
(decimal 0) to 1001 (decimal 9)
→ “decade counter.”
Q3 Q2 Q1 Q0
0 0 0 0
Q0 0 0 0 1
0 0 1 0
0 0 1 1
Q1 0 1 0 0
0 1 0 1
0 1 1 0
Q2
0 1 1 1
1 0 0 0
Q3 1 0 0 1
0 0 0 0 repeats
A synchronous counter
J Q J Q J Q J Q
Q0 Q1 Q2 Q3
FF0 FF1 FF2 FF3
K Q K Q K Q K Q
CLK
CLK
t
Q0
t
Q1
t
Q2
t
Q3
t
J Q J Q J Q J Q
Q0 Q1 Q2 Q3
FF0 FF1 FF2 FF3
K Q K Q K Q K Q
CLK
CLK
t
Q0
t
Q1
t
Q2
t
Q3
t
* Since all flip-flops are driven by the same clock, the counter is called a “synchronous” counter.
J Q J Q J Q J Q
Q0 Q1 Q2 Q3
FF0 FF1 FF2 FF3
K Q K Q K Q K Q
CLK
CLK
t
Q0
t
Q1
t
Q2
t
Q3
t
* J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 .
J Q J Q J Q J Q
Q0 Q1 Q2 Q3
FF0 FF1 FF2 FF3
K Q K Q K Q K Q
CLK
CLK
t
Q0
t
Q1
t
Q2
t
Q3
t
* J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 .
* FF0 toggles after every active edge.
FF1 toggles if Q0 = 1 (just before the active clock edge); else, it retains its previous state. (Similarly, for FF2 and FF3)
J Q J Q J Q J Q
Q0 Q1 Q2 Q3
FF0 FF1 FF2 FF3
K Q K Q K Q K Q
CLK
CLK
t
Q0
t
Q1
t
Q2
t
Q3
t
* J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 .
J Q J Q J Q J Q
Q0 Q1 Q2 Q3
FF0 FF1 FF2 FF3
K Q K Q K Q K Q
CLK
CLK
t
Q0
t
Q1
t
Q2
t
Q3
t
* J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 .
J Q J Q J Q J Q
Q0 Q1 Q2 Q3
FF0 FF1 FF2 FF3
K Q K Q K Q K Q
CLK
CLK
t
Q0
t
Q1
t
Q2
t
Q3
t
* J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 .
J Q J Q J Q J Q
Q0 Q1 Q2 Q3
FF0 FF1 FF2 FF3
K Q K Q K Q K Q
CLK
CLK
t
Q0
t
Q1
t
Q2
t
Q3
t
* J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 .

J Q J Q J Q J Q
Q0 Q1 Q2 Q3
FF0 FF1 FF2 FF3
K Q K Q K Q K Q
CLK
CLK
t
Q0
t
Q1
t
Q2
t
Q3
t
* J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 .
* From the waveforms, we see that it is a binary up counter.
Design of synchronous counters
CLK J K Qn+1
J Q
0 0 Qn
CLK 0 1 0
K Q 1 0 1
1 1 Qn
CLK J K Qn+1 CLK Qn Qn+1 J K

J Q
0 0 Qn
CLK 0 1 0
K Q 1 0 1
1 1 Qn
* Consider the reverse problem: We are given Qn and the next desired state (Qn+1 ). What should J and K be in order to
make that happen?

J Q
0 0 Qn
CLK 0 1 0
K Q 1 0 1
1 1 Qn
make that happen?
* Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn by making J = 0, K = 0.

J Q
0 0 Qn
CLK 0 1 0
K Q 1 0 1
1 1 Qn
make that happen?
→ J = 0, K = X (i.e., K can be 0 or 1).

J Q
0 0 Qn 0 0 0 X
CLK 0 1 0
K Q 1 0 1
1 1 Qn
make that happen?
→ J = 0, K = X (i.e., K can be 0 or 1).

J Q
0 0 Qn 0 0 0 X
CLK 0 1 0
K Q 1 0 1
1 1 Qn
make that happen?
→ J = 0, K = X (i.e., K can be 0 or 1).
* Similarly, work out the other entries in the table.

J Q
0 0 Qn 0 0 0 X
CLK 0 1 0 0 1
K Q 1 0 1
1 1 Qn
make that happen?
→ J = 0, K = X (i.e., K can be 0 or 1).

J Q
0 0 Qn 0 0 0 X
CLK 0 1 0 0 1 1 X
K Q 1 0 1
1 1 Qn
make that happen?
→ J = 0, K = X (i.e., K can be 0 or 1).

J Q
0 0 Qn 0 0 0 X
CLK 0 1 0 0 1 1 X
K Q 1 0 1 1 0
1 1 Qn
make that happen?
→ J = 0, K = X (i.e., K can be 0 or 1).

J Q
0 0 Qn 0 0 0 X
CLK 0 1 0 0 1 1 X
K Q 1 0 1 1 0 X 1
1 1 Qn
make that happen?
→ J = 0, K = X (i.e., K can be 0 or 1).

J Q
0 0 Qn 0 0 0 X
CLK 0 1 0 0 1 1 X
K Q 1 0 1 1 0 X 1
1 1 Qn 1 1
make that happen?
→ J = 0, K = X (i.e., K can be 0 or 1).

J Q
0 0 Qn 0 0 0 X
CLK 0 1 0 0 1 1 X
K Q 1 0 1 1 0 X 1
1 1 Qn 1 1 X 0
make that happen?
→ J = 0, K = X (i.e., K can be 0 or 1).


J Q
0 0 Qn 0 0 0 X
CLK 0 1 0 0 1 1 X
K Q 1 0 1 1 0 X 1
1 1 Qn 1 1 X 0
make that happen?
→ J = 0, K = X (i.e., K can be 0 or 1).
* The table for a negative edge-triggered flip-flop would be identical except for the active edge.

state Q2 Q1 Q0 CLK Qn Qn+1 J K

J2 Q2 J1 Q1 J0 Q0
1 0 0 0 J Q J Q J Q 0 0 0 X
2 0 0 1
0 1 1 X
3 0 1 0
1 0 X 1
4 0 1 1 K Q K Q K Q
K2 K1 K0
5 1 0 0 1 1 X 0
CLK
1 0 0 0 repeats
Design a synchronous mod-5 counter with the given state transition table.


J2 Q2 J1 Q1 J0 Q0
1 0 0 0 J Q J Q J Q 0 0 0 X
2 0 0 1
0 1 1 X
3 0 1 0
1 0 X 1
4 0 1 1 K Q K Q K Q
K2 K1 K0
5 1 0 0 1 1 X 0
CLK
1 0 0 0 repeats
Outline of method:


J2 Q2 J1 Q1 J0 Q0
1 0 0 0 J Q J Q J Q 0 0 0 X
2 0 0 1
0 1 1 X
3 0 1 0
1 0 X 1
4 0 1 1 K Q K Q K Q
K2 K1 K0
5 1 0 0 1 1 X 0
CLK
1 0 0 0 repeats
Outline of method:
* State 1 → State 2 means
Q2 : 0 → 0,
Q1 : 0 → 0,
Q0 : 0 → 1.


J2 Q2 J1 Q1 J0 Q0
1 0 0 0 J Q J Q J Q 0 0 0 X
2 0 0 1
0 1 1 X
3 0 1 0
1 0 X 1
4 0 1 1 K Q K Q K Q
K2 K1 K0
5 1 0 0 1 1 X 0
CLK
1 0 0 0 repeats
Outline of method:
Q2 : 0 → 0,
Q1 : 0 → 0,
Q0 : 0 → 1.
* Refer to the right table. For Q2 : 0 → 0, we must have J2 = 0, K2 = X , and so on.


J2 Q2 J1 Q1 J0 Q0
1 0 0 0 J Q J Q J Q 0 0 0 X
2 0 0 1
0 1 1 X
3 0 1 0
1 0 X 1
4 0 1 1 K Q K Q K Q
K2 K1 K0
5 1 0 0 1 1 X 0
CLK
1 0 0 0 repeats
Outline of method:
Q2 : 0 → 0,
Q1 : 0 → 0,
Q0 : 0 → 1.
* When we cover all transitions in the left table, we have the truth tables for J0 , K0 , J1 , K1 , J2 , K2 in terms of Q0 , Q1 , Q2 .


J2 Q2 J1 Q1 J0 Q0
1 0 0 0 J Q J Q J Q 0 0 0 X
2 0 0 1
0 1 1 X
3 0 1 0
1 0 X 1
4 0 1 1 K Q K Q K Q
K2 K1 K0
5 1 0 0 1 1 X 0
CLK
1 0 0 0 repeats
Outline of method:
Q2 : 0 → 0,
Q1 : 0 → 0,
Q0 : 0 → 1.
* When we cover all transitions in the left table, we have the truth tables for J0 , K0 , J1 , K1 , J2 , K2 in terms of Q0 , Q1 , Q2 .
* The last step is to come up with suitable functions for J0 , K0 , J1 , K1 , J2 , K2 in terms of Q0 , Q1 , Q2 . This can be done
with K-maps. (If the number of flip-flops is more than 4, other techniques can be employed.)

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
CLK Qn Qn+1 J K
1 0 0 0
0 0 0 X
2 0 0 1
3 0 1 0 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0
0 0 0 X
2 0 0 1
3 0 1 0 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X
0 0 0 X
2 0 0 1
3 0 1 0 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X
0 0 0 X
2 0 0 1
3 0 1 0 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1
3 0 1 0 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1
3 0 1 0 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X
3 0 1 0 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X
3 0 1 0 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 1 X 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 1 X 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 1 X 0 1 1 X
4 0 1 1 1 X 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 1 X 0 1 1 X
4 0 1 1 1 X X 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 1 X 0 1 1 X
4 0 1 1 1 X X 1 X 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 1 X 0 1 1 X
4 0 1 1 1 X X 1 X 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 1 X 0 1 1 X
4 0 1 1 1 X X 1 X 1 1 0 X 1
5 1 0 0 X 1
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 1 X 0 1 1 X
4 0 1 1 1 X X 1 X 1 1 0 X 1
5 1 0 0 X 1 0 X
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 1 X 0 1 1 X
4 0 1 1 1 X X 1 X 1 1 0 X 1
5 1 0 0 X 1 0 X 0 X
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 1 X 0 1 1 X
4 0 1 1 1 X X 1 X 1 1 0 X 1
5 1 0 0 X 1 0 X 0 X
1 1 X 0
1 0 0 0
* We now have the truth tables for J0 , K0 , J1 , K1 , J2 , K2 in terms of Q0 , Q1 , Q2 . The next step is to find
logical functions for each of them.
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 1 X 0 1 1 X
4 0 1 1 1 X X 1 X 1 1 0 X 1
5 1 0 0 X 1 0 X 0 X
1 1 X 0
1 0 0 0
* We now have the truth tables for J0 , K0 , J1 , K1 , J2 , K2 in terms of Q0 , Q1 , Q2 . The next step is to find
logical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0 , Q1 , Q2 which do not
occur in the state transition table (such as Q2 Q1 Q0 = 110). We treat these as don’t care conditions.

Q2 Q1 Q2 Q1
Q0 00 01 11 10 Q0 00 01 11 10
0 0 0 X X 0 X X X 1
J2 K2
1 0 1 X X 1 X X X X
1 0 0 0 0 X 0 X 1 X Q2 Q1 Q2 Q1
2 0 0 1 0 X 1 X X 1 Q0 00 01 11 10 Q0 00 01 11 10
3 0 1 0 0 X X 0 1 X 0 0 X X 0 0 X 0 X X
J1 K1
4 0 1 1 1 X X 1 X 1
1 1 X X X 1 X 1 X X
5 1 0 0 X 1 0 X 0 X
1 0 0 0 Q2 Q1 Q2 Q1
Q0 00 01 11 10 Q0 00 01 11 10
0 1 1 X 0 0 X X X X
J0 K0
1 X X X X 1 1 1 X X

Q2 Q1 Q2 Q1
Q0 00 01 11 10 Q0 00 01 11 10
0 0 0 X X 0 X X X 1
J2 K2
1 0 1 X X 1 X X X X
1 0 0 0 0 X 0 X 1 X Q2 Q1 Q2 Q1
2 0 0 1 0 X 1 X X 1 Q0 00 01 11 10 Q0 00 01 11 10
3 0 1 0 0 X X 0 1 X 0 0 X X 0 0 X 0 X X
J1 K1
4 0 1 1 1 X X 1 X 1
1 1 X X X 1 X 1 X X
5 1 0 0 X 1 0 X 0 X
1 0 0 0 Q2 Q1 Q2 Q1
Q0 00 01 11 10 Q0 00 01 11 10
0 1 1 X 0 0 X X X X
J0 K0
1 X X X X 1 1 1 X X
* We treat the unused states (Q2 Q1 Q0 = 101, 110, 111) as (additional) don’t care conditions. Since these are different
from the don’t care conditions arising from the state transition table, we mark them with a different colour.

Q2 Q1 Q2 Q1
Q0 00 01 11 10 Q0 00 01 11 10
0 0 0 X X 0 X X X 1
J2 K2
1 0 1 X X 1 X X X X
1 0 0 0 0 X 0 X 1 X Q2 Q1 Q2 Q1
2 0 0 1 0 X 1 X X 1 Q0 00 01 11 10 Q0 00 01 11 10
3 0 1 0 0 X X 0 1 X 0 0 X X 0 0 X 0 X X
J1 K1
4 0 1 1 1 X X 1 X 1
1 1 X X X 1 X 1 X X
5 1 0 0 X 1 0 X 0 X
1 0 0 0 Q2 Q1 Q2 Q1
Q0 00 01 11 10 Q0 00 01 11 10
0 1 1 X 0 0 X X X X
J0 K0
1 X X X X 1 1 1 X X
* We will assume that a suitable initialization facility is provided to ensure that the counter starts up in one of the five
allowed states (say, Q2 Q1 Q0 = 000).

Q2 Q1 Q2 Q1
Q0 00 01 11 10 Q0 00 01 11 10
0 0 0 X X 0 X X X 1
J2 K2
1 0 1 X X 1 X X X X
1 0 0 0 0 X 0 X 1 X Q2 Q1 Q2 Q1
2 0 0 1 0 X 1 X X 1 Q0 00 01 11 10 Q0 00 01 11 10
3 0 1 0 0 X X 0 1 X 0 0 X X 0 0 X 0 X X
J1 K1
4 0 1 1 1 X X 1 X 1
1 1 X X X 1 X 1 X X
5 1 0 0 X 1 0 X 0 X
1 0 0 0 Q2 Q1 Q2 Q1
Q0 00 01 11 10 Q0 00 01 11 10
0 1 1 X 0 0 X X X X
J0 K0
1 X X X X 1 1 1 X X
* We will assume that a suitable initialization facility is provided to ensure that the counter starts up in one of the five
allowed states (say, Q2 Q1 Q0 = 000).
* From the K-maps, J2 = Q1 Q0 , K2 = 1, J1 = Q0 , K1 = Q0 , J0 = Q2 , K0 = 1.
Design of synchronous counters: verification
J2 Q2 J1 Q1 J0 Q0
J Q J Q J Q
K Q K Q K Q
K2 K1 K0
CLK
1
CLK
Q0
Q1
Q2
0.04 0.14 0.24 0.34

time (msec)
SEQUEL file: ee101 counter 6.sqproj
* J2 = Q1 Q0 ,
J2 Q2 J1 Q1 J0 Q0 K2 = 1,
J Q J Q J Q
J1 = Q0 ,
K1 = Q0 ,
J0 = Q2 ,
K Q K Q K Q
K2 K1 K0 K0 = 1.
CLK
1
CLK
Q0
Q1
Q2
0.04 0.14 0.24 0.34

time (msec)
* J2 = Q1 Q0 ,
J2 Q2 J1 Q1 J0 Q0 K2 = 1,
J Q J Q J Q
J1 = Q0 ,
K1 = Q0 ,
J0 = Q2 ,
K Q K Q K Q
K2 K1 K0 K0 = 1.
CLK * Note that the design is independent
1 of whether positive or negative
edge-triggered flip-flops are used.
CLK
Q0
Q1
Q2
0.04 0.14 0.24 0.34

time (msec)
Combination of counters: Approach 1
A1
A2
Counter 1
Clock 1 mod-k1
k1 = 4 AN1
B1
B2
Counter 2
Clock 2 mod-k2
k2 = 3 BN2
A1
A2
Counter 1 Counter 1
Clock 1 mod-k1 Clock 1 mod-k1
k1 = 4 AN1
B1 Clock 1
B2
Counter 2
Clock 2 mod-k2 Counter 1 state 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1
k2 = 3 BN2
A1
A2
Counter 1 Counter 1 Decoding Counter 2
Clock 1 mod-k1 Clock 1 mod-k1 Logic mod-k2
Clock 2
k1 = 4 AN1
B1 Clock 1
B2
Counter 2
k2 = 3 BN2 Clock 2
A1
A2
Clock 2
k1 = 4 AN1
B1 Clock 1
B2
Counter 2
k2 = 3 BN2 Clock 2
Counter 2 state 1 2 3 1
A1
A2
Clock 2
k1 = 4 AN1
B1 Clock 1
B2
Counter 2
k2 = 3 BN2 Clock 2
3 1 1 1 1 2 2 2 2 3 3 3 3 1 1 1 1 2
Combined state
4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1
A1
A2
Clock 2
k1 = 4 AN1
B1 Clock 1
B2
Counter 2
k2 = 3 BN2 Clock 2
3 1 1 1 1 2 2 2 2 3 3 3 3 1 1 1 1 2
Combined state
4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1
→ the combined counter is a mod-k1 k2 counter.

Combination of counters: example
J0 Q0 J2 Q2 J1 Q1 J0 Q0
J Q J Q J Q J Q
CLK
1 K Q K Q K Q K Q
K0 K2 K1 K0
CLK
1
CLK CLK
t t
Q0 Q0
t t
Q1
t
Q2
mod−2 counter mod−5 counter

JA QA J2 Q2 J1 Q1 J0 Q0
J Q J Q J Q J Q
CLK
1 K Q K Q K Q K Q
KA K2 K1 K0
CLK
t
QA
t
Q0
t
Q1
t
Q2
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 t

A1
A2
Counter 1
Clock 1 mod-k1
k1 = 4 AN1
B1
B2
Counter 2
Clock 2 mod-k2
k2 = 3 BN2
A1
A2
Counter 1 Counter 1
Clock 1 mod-k1 mod-k1
Clock 1
k1 = 4 AN1
B1 Clock 1
B2
Counter 2
k2 = 3 BN2
A1
A2
Counter 1 Counter 1 Clock 2 Counter 2
Clock 1 mod-k1 mod-k1 mod-k2
Clock 1
k1 = 4 AN1
B1 Clock 1
B2
Counter 2
k2 = 3 BN2
A1
A2
Clock 1
k1 = 4 AN1
B1 Clock 1
B2
Counter 2
k2 = 3 BN2 Clock 2
A1
A2
Clock 1
k1 = 4 AN1
B1 Clock 1
B2
Counter 2
k2 = 3 BN2 Clock 2
Counter 2 state 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2
A1
A2
Clock 1
k1 = 4 AN1
B1 Clock 1
B2
Counter 2
k2 = 3 BN2 Clock 2
Counter 2 state 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2
3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2
Combined state
4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1
A1
A2
Clock 1
k1 = 4 AN1
B1 Clock 1
B2
Counter 2
k2 = 3 BN2 Clock 2
Counter 2 state 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2
3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2
Combined state
4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1
→ the combined counter is a mod-k1 k2 counter.

Combination of counters: example (same as before)
J0 Q0 J2 Q2 J1 Q1 J0 Q0
J Q J Q J Q J Q
CLK
1 K Q K Q K Q K Q
K0 K2 K1 K0
CLK
1
CLK CLK
t t
Q0 Q0
t t
Q1
t
Q2
mod−2 counter mod−5 counter

JA QA J2 Q2 J1 Q1 J0 Q0
J Q J Q J Q J Q
K Q K Q K Q K Q
1 KA K2 K1 K0
CLK
1
CLK
t
QA
t
Q0
t
Q1
t
Q2
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 t

555 timer IC
The 555 timer is useful in timer, pulse generation, and oscillator applications. We will look at two common
applications.

555 timer IC
applications.
* Monostable multivibrator
Vtrigger
t
Vout
t
T

555 timer IC
applications.
* Monostable multivibrator
Vtrigger
t
Vout
t
T
* Astable multivibrator
Vout
t
T

555 timer
VCC
Threshold R Q
Out
R buffer
S Q Discharge
Trigger
R
R S Q Q
1 0 0 1
0 1 1 0
0 0 previous
555 timer
VCC
R
2 VCC
3
Threshold R Q Threshold R Q
Out Out
R buffer
S Q VCC S Q
Discharge 3
Discharge
Trigger Trigger
R
R S Q Q
1 0 0 1
0 1 1 0
0 0 previous
555 timer
VCC
R
2 VCC
3
Threshold R Q Threshold R Q
Out Out
R buffer
S Q VCC S Q
Discharge 3
Discharge
Trigger Trigger
R
R S Q Q
1 0 0 1
0 1 1 0 STOP
0 0 previous
555 monostable multivibrator
VCC
2 VCC
R
3
Threshold R Q
Out
VC C
VCC S Q Discharge
3
Trigger
VCC Trigger
2 VCC
R
3
t
Threshold R Q S
Out
VC C
VCC S Q Discharge t
3
Trigger R
t
Q
VC
t
VCC Trigger
2 VCC
R
3
t
Threshold R Q S
Out
VC C
VCC S Q Discharge t
3
Trigger R
t
Q
t
to VCC
VC
t
VCC Trigger
2 VCC
R
3
t
Threshold R Q S
Out
VC C
VCC S Q Discharge t
3
Trigger R
t
Q
t
T to VCC
2 VCC
VC 3
t
VCC Trigger
2 VCC
R
3
t
Threshold R Q S
Out
VC C
VCC S Q Discharge t
3
Trigger R
t
Q
VC (t) = VCC 1 − e −t/τ

t
T to VCC
2 VCC
VC 3
t
VCC Trigger
2 VCC
R
3
t
Threshold R Q S
Out
VC C
VCC S Q Discharge t
3
Trigger R
t
Q
VC (t) = VCC 1 − e −t/τ

t
T to VCC
2 VCC
2 VCC
VC 3
→ = VCC 1 − e −T /τ
3
t
VCC Trigger
2 VCC
R
3
t
Threshold R Q S
Out
VC C
VCC S Q Discharge t
3
Trigger R
t
Q
VC (t) = VCC 1 − e −t/τ

t
T to VCC
2 VCC
2 VCC
VC 3
→ = VCC 1 − e −T /τ
3
1
→ e −T /τ = → T = τ log 3 ≈ 1.1 τ
3
t
VCC Trigger
2 VCC
R
3
t
Threshold R Q S
Out
VC C
VCC S Q Discharge t
3
Trigger R
t
Q
VC (t) = VCC 1 − e −t/τ

t
T to VCC
2 VCC
2 VCC
VC 3
→ = VCC 1 − e −T /τ
3
1
→ e −T /τ = → T = τ log 3 ≈ 1.1 τ
3
SEQUEL file: ic555 mono 1.sqproj
t
555 astable multivibrator
2 VCC
VCC
3
Threshold
Ra R Q
Out
VCC S Q
Rb Discharge
3
Trigger
VC C
2 VCC S
VCC
3
Threshold
Ra R Q
Out t
R
VCC S Q
Rb Discharge
3
t
Q
Trigger
VC C
t
VCC
2 VCC
3
VC
VCC
3
0
t
TH TL

2 VCC S
VCC
3
Threshold
Ra R Q
Out t
R
VCC S Q
Rb Discharge
3
t
Q
Trigger
VC C
t
VCC
Charging:
VCC 2 VCC
VC (0) = , VC (∞) = VCC . 3
3
VC
VCC
3
0
t
TH TL

2 VCC S
VCC
3
Threshold
Ra R Q
Out t
R
VCC S Q
Rb Discharge
3
t
Q
Trigger
VC C
t
VCC
Charging:
VCC 2 VCC
VC (0) = , VC (∞) = VCC . 3
3
VC
Let VC (t) = A e −t/τ1 + B
VCC
2 VCC
→ B = VCC , A = − 3
3
0
t
TH TL

2 VCC S
VCC
3
Threshold
Ra R Q
Out t
R
VCC S Q
Rb Discharge
3
t
Q
Trigger
VC C
t
VCC
Charging:
VCC 2 VCC
VC (0) = , VC (∞) = VCC . 3
3
VC
VCC
2 VCC
→ B = VCC , A = − 3
3
2 VCC 2 VCC −TH /τ1
=− e + VCC
3 3 0
t
TH TL

2 VCC S
VCC
3
Threshold
Ra R Q
Out t
R
VCC S Q
Rb Discharge
3
t
Q
Trigger
VC C
t
VCC
Charging:
VCC 2 VCC
VC (0) = , VC (∞) = VCC . 3
3
VC
VCC
2 VCC
→ B = VCC , A = − 3
3
2 VCC 2 VCC −TH /τ1
=− e + VCC
3 3 0
t
→ TH = τ1 log 2, with τ1 = (Ra + Rb ) C . TH TL

2 VCC
VCC
3
Threshold
Ra R Q
Out
VCC S Q
Rb Discharge
3
Trigger
VC C
2 VCC S
VCC
3
Threshold
Ra R Q
Out t
R
VCC S Q
Rb Discharge
3
t
Q
Trigger
VC C
t
VCC
2 VCC
3
VC
VCC
3
0
t
TH TL

2 VCC S
VCC
3
Threshold
Ra R Q
Out t
R
VCC S Q
Rb Discharge
3
t
Q
Trigger
VC C
t
VCC
2 VCC
Discharging: VC (0) = , VC (∞) = 0. 2 VCC
3 3
2 VCC −t/τ2
→ VC (t) = e VC
3
VCC
3
0
t
TH TL

2 VCC S
VCC
3
Threshold
Ra R Q
Out t
R
VCC S Q
Rb Discharge
3
t
Q
Trigger
VC C
t
VCC
2 VCC
3 3
2 VCC −t/τ2
→ VC (t) = e VC
3
VCC 2 VCC −TL /τ2 VCC
= e
3 3 3
0
t
TH TL

2 VCC S
VCC
3
Threshold
Ra R Q
Out t
R
VCC S Q
Rb Discharge
3
t
Q
Trigger
VC C
t
VCC
2 VCC
3 3
2 VCC −t/τ2
→ VC (t) = e VC
3
= e
3 3 3
→ TL = τ2 log 2, with τ2 = Rb C .
0
t
TH TL

2 VCC S
VCC
3
Threshold
Ra R Q
Out t
R
VCC S Q
Rb Discharge
3
t
Q
Trigger
VC C
t
VCC
2 VCC
3 3
2 VCC −t/τ2
→ VC (t) = e VC
3
= e
3 3 3
→ TL = τ2 log 2, with τ2 = Rb C .
0
t
SEQUEL file: ic555 astable 1.sqproj TH TL

Week 11 Slides PDF

Caricato da

Informazioni sul documento

Titolo originale

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

Week 11 Slides PDF

Caricato da

Copyright:

Formati disponibili

Sequential circuits

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

Why not allow R = S = 0?

Why not allow R = S = 0?

Why not allow R = S = 0?

Why not allow R = S = 0?

Why not allow R = S = 0?

Why not allow R = S = 0?

Why not allow R = S = 0?

Why not allow R = S = 0?

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

* The NOR latch is similar to the NAND latch:

M. B. Patil, IIT Bombay

* The NOR latch is similar to the NAND latch:

M. B. Patil, IIT Bombay

* The NOR latch is similar to the NAND latch:

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

Active low input nodes:

M. B. Patil, IIT Bombay

* When the switch is thrown from A to B, Vo is expected to go from 0 V to Vs (say, 5 V ).

* When the switch is thrown from A to B, Vo is expected to go from 0 V to Vs (say, 5 V ).

* When the switch is thrown from A to B, Vo is expected to go from 0 V to Vs (say, 5 V ).

* When the switch is thrown from A to B, Vo is expected to go from 0 V to Vs (say, 5 V ).

* When the switch is thrown from A to B, Vo is expected to go from 0 V to Vs (say, 5 V ).

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

positive edge negative edge

M. B. Patil, IIT Bombay

positive edge negative edge

M. B. Patil, IIT Bombay

positive edge negative edge

M. B. Patil, IIT Bombay

Clocked RS latch NAND RS latch

M. B. Patil, IIT Bombay

Clocked RS latch NAND RS latch

M. B. Patil, IIT Bombay

Clocked RS latch NAND RS latch

M. B. Patil, IIT Bombay

Clocked RS latch NAND RS latch

M. B. Patil, IIT Bombay

0 0.2 0.4 0.6 0.8

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

positive edge−triggered flip−flop negative edge−triggered flip−flop

M. B. Patil, IIT Bombay

Consider J = K = 1 and CLK = 1.

M. B. Patil, IIT Bombay