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EEE 101 Experiment 2: Feedback Implementation

and Error Signals


Edgardo Callagon Jr., Jazzrine Tagle
Electrical and Electronics Engineering Institute
University of the Philippines Diliman
Quezon City, Philippines
edgardo.callagon@eee.upd.edu.ph
jazzrine.tagle@eee.upd.edu.ph

Abstract—The main objective of this experiment is to construct


a closed-loop system with an additional system gain to the first- A. Closing the loop
order, type-0 plant developed in the previous experiment. The The plant obtained from experiment 1, with modelled
error signal to variable controller values was tested and observed. transfer function, G(s), was implemented in a closed-loop
The variable controllers used are the proportional controller and system shown in Fig. 1.
the integral controller. The error results and step responses are
shown in this paper.

I. INTRODUCTION
A closed-loop control system, also known as a feedback
control system is a control system which uses the concept of an
open loop system as its forward path but has one or more
feedback loops or paths between its input and its output. The Fig. 1. Closed-loop system
reference to “feedback” simply means that some portion of the Vdesired is a DC voltage input with value equal 0.8*(VTEMP-
output is returned to the input to form part of the system’s
MAX), where VTEMP-MAX is the stop condition value taken from
excitation. [1] the data in experiment 1. In this case, Vdesired = 0.8*(4.54) = 3.6
Closed-loop systems are designed to automatically achieve V. A UA741 single op-amp was used to implement the
and maintain the desired output condition by comparing it with summing block in the closed-loop system. The schematic
the actual condition. It does this by generating an error signal diagram of the operational amplifier for the unity gain feedback
which is the difference between the output and the reference (i.e. E(s)= Vdesired - VTEMP) is shown in Fig. 2.
input. [1]
When the closed-loop system is properly designed, the
output will be less sensitive to disturbances, less sensitive to
plant changes, and will have a lesser steady-state error with
respect to a desired value.
Another way to get a more accurate output (i.e. smaller
steady-state error) is to increase the system type of the plant.
This technique was examined using an integral controller,
wherein given an input step function, the steady state error
theoretically must approach zero.

II. EXPERIMENT, RESULTS, AND DISCUSSION


Fig. 2. Summing Block (Difference Amplifier)
The experiment was divided into three parts. The first part
focused on converting the open-loop plant of Experiment 1 into Gc(s) in Fig.1 is a controller configuration which was varied
a closed-loop system. A proportional controller was then in the next parts of the experiment.
cascaded in the forward path of the closed-loop system. The
behaviour of the proportional controller was analysed by taking
the output voltage (VTEMP)with respect to time and the steady- B. Proportional Controller
state errors of the system given a varying constant of The controller (in this case a proportional controller) with a
proportionality (kp) equal to 1, 2, 5, and 10. Afterwards, the transfer function, Gc(s), is inserted in closed-loop system
proportional controller was replaced by an integral controller. modelled in Fig.1. To implement the proportional controller, a
The output voltage with respect to time and the steady-state UA741 single op-amp was used. The schematic diagram is
errors that were measured, and the implementation of each shown in Fig. 3.
controller is discussed in the succeeding sections.
The error signals for each gain that were obtained are plotted
in Fig. 4.

Error Results of the Proportional


Controllers
1.2

Error (Vdesired - Vtemp)


Fig. 3. Proportional Controller (Non-Inverting Amplifier)
0.8
Given that the gain for the non-inverting amplifier in Fig.3
𝑅1 𝑅 kp = 1
is given by the equation 𝐴𝑣 = 1 + = 1 + , 0.6
𝑅2 1𝑘
kp = 2
the resistor R was decided to have values 0 (or shorted) for
0.4
kp = 1, 1kΩ for kp = 2, 3.9kΩ for kp = 5, and 9.1kΩ for kp = 10. kp = 5
0.2 kp = 10
The behaviour of the proportional controller was observed
by changing the constant of proportionality (kp) – the gain of 0
the amplifier. The output voltages (VTEMP) of each gain was 0 100 200 300 400
measured every 30 seconds until steady-state and the results are -0.2
shown in Table 1. Then, the steady-state errors for each gain is Time in Seconds
measured at the output of the summing block. The steady-state
error, ess, which from Fig.1. can be defined as Vdesired - Fig. 4. Error Results of the Proportional Controller
VTEMP,STEADY-STATE, that were obtained for kp = 1, 2, 5, and 10
are 1.09 V, 0.91 V, 0.33 V, and 0.28 V respectively.
Theoretically, the steady-state error can be computed as
TABLE I
OUTPUT VOLTAGES WITH RESPECT TO TIME follows:
With the proportional controller providing simply a constant
TIME VTEMP (V) multiplier kp to the forward gain, the plant will remain to be a
(min:sec) kp = 1 kp = 2 kp = 5 kp = 10 first-order type 0 system.
0:00 2.52 2.71 2.52 2.52
Hence,
0:30 2.51 2.71 3.15 3.72 1
1:00 2.50 2.70 3.26 3.42 𝑒𝑠𝑠 = 𝑤ℎ𝑒𝑟𝑒 𝑘 = lim 𝐺𝑐(𝑠)𝐺(𝑠) .
1+𝑘 𝑠→0
1:30 2.49 2.69 3.27 3.28 From the original open loop plant in the previous experiment,
2:00 2.50 2.69 3.27 3.30
2:30 2.51 2.69 3.27 3.35 0.055
𝐺(𝑠) = 1 𝑎𝑛𝑑 𝐺𝑐(𝑠) = 𝑘𝑝
3:00 2.51 2.69 3.28 3.36 𝑠+
144.155
3:30 3.27 3.34
4:00 3.34 For 𝑘𝑝 = 1, 𝑒𝑠𝑠 =0.112
4:30 3.33
𝑘𝑝 = 2, 𝑒𝑠𝑠 =0.059
5:00 3.33
5:30 3.32 𝑘𝑝 = 5, 𝑒𝑠𝑠 =0.025
𝑘𝑝 = 10, 𝑒𝑠𝑠 =0.012.

Hence, it can be observed that the steady-state error


decreases as the gain for the proportional controller increases.
This observation matches with the experimental result shown
in Fig.4. wherein the error Vdesired - VTEMP decreases as kp
increases.
To get the theoretical error reponse, we note that,
𝑅(𝑠)
𝐸(𝑠) =
1 + 𝐺𝑐 (𝑠)𝐺(𝑠)
0.055
𝐺(𝑠) =
1
𝑠+
144.155
Since Gc(s) is a proportional controller,
𝐺𝑐 (𝑠) = 𝑘𝑝
𝑉𝑑𝑒𝑠𝑖𝑟𝑒𝑑 The theoretical step response obtained using the transfer
𝑅(𝑠) = , where Vdesired = 3.6
𝑠
function solved is shown in Fig.6.
So,
1 3.6
𝐸(𝑠) = ∙
0.055 𝑠
1 + 𝑘𝑝 ( 1 )
𝑠+
144.155
1
𝑠+ 3.6
𝐸(𝑠) = 144.155 ∙
1
𝑠+ + 𝑘𝑝 (0.055) 𝑠
144.155
The theoretical error response of the system using the
obtained E(s) is shown in Fig.5 where, again, error decreases as
kp increases.

Fig. 6. Theoretical Step Response of the System at different kp

Fig.7 shows the actual step response of the closed-loop


system with kp equal to 1,2,5 and 10. With the bulb not having
enough power to turn on, the output was measured to
correspond to the ambient temperature which is at around 25-
27C for kp=1 and kp=2. With the bulb turning on at kp=5 and
kp=10, the output follows the expected first-order step response
curve.

Fig. 5. Error Step Response of Proportional Controller From the data in Fig.7, it can be observed that the steady-
state output voltage of the system increases, which
consequently decreases the steady-state error, as kp increases.
Given that the system is still a first-order one, the expected This observation matches with the theoretical computations and
step response will be similar to the one obtained in the previous analysis provided.
experiment wherein the curve resembles an exponential
function.

Solving for the transfer function, we get,

0.055
1 𝑘𝑝 (
)
𝑉𝑡𝑒𝑚𝑝 𝐺𝑐(𝑠)𝐺(𝑠) 𝑠+
= = 144.155
𝑉𝑑𝑒𝑠𝑖𝑟𝑒𝑑 1 + 𝐺𝑐(𝑠)𝐺(𝑠) 0.055
1 + 𝑘𝑝 ( 1 )
𝑠+
144.155

𝑉𝑡𝑒𝑚𝑝 0.055𝑘𝑝
=
𝑉𝑑𝑒𝑠𝑖𝑟𝑒𝑑 𝑠 + 0.0069 + 0.055𝑘𝑝
Fig. 7. Actual Step Response of the System at different kp
C. Integral Controller The error signal was also obtained in the experiment. The
The proportional controller was replaced with an integral plot is shown in Fig. 10.
controller since the constant of proportionality (kp) needed is
only 1. A UA741 op-amp, a 1MΩ resistor and a 1µF capacitor
was used. An inverter was cascaded to the integral controller to
Error Results of the Integral Controller
compensate for the negating effect of the integrating. The 1.5

Error (Vdesired - Vtemp)


inverter was implemented by also using a UA741 op-amp. The
schematic diagram of integral controller is shown in Fig. 8. 1

0.5

0
0 90 180 270 360 450 540 630 720 810 900 990
-0.5
Time in Seconds

Fig. 10. Error Results of the Integral Controller


Fig. 8. Integral Controller (Integrator and Inverting Amplifier)

With the integral controller in cascade to the forward loop gain


The output voltage (VTEMP) was measured every 30 seconds.
of the closed-loop system, the overall transfer function can be
The results are shown in Table 2.
computed as follows:
TABLE III 1 0.055
( 1 )
𝑠 𝑠+
OUTPUT VOLTAGES WITH RESPECT TO TIME 𝑉𝑡𝑒𝑚𝑝 𝐺𝑐(𝑠)𝐺(𝑠) 144.155
= = 1 0.055
𝑉𝑑𝑒𝑠𝑖𝑟𝑒𝑑 1+𝐺𝑐(𝑠)𝐺(𝑠) 1+ ( 1 )
TIME TIME VTEMP 𝑠 𝑠+
VTEMP (V) 144.155
(min:sec) (min:sec) (V) 0.055 0.055
0:00 2.43 8:30 3.25 = =
0:30 3.93 9:00 3.22 1 1
𝑠 (𝑠 + ) + 0.055 𝑠 2 + 𝑠 + 0.055
1:00 3.46 9:30 3.39 144.155 144.155
1:30 3.41 10:00 3.34
2:00 3.39 10:30 3.37 The system is now second-order and type 1 with a transfer
2:30 3.34 11:00 3.26 function shown in Fig.11. Due to the increase in system type,
3:00 3.20 11:30 3.29 overshoot can be observed in the output step response.
3:30 3.24 12:00 3.29
4:00 3.22 12:30 3.17 Oscillations are present in the output that decrease and reach
4:30 3.22 13:00 3.15 steady-state at a value equal to Vdesired. This implies that the
5:00 3.2 13:30 3.12 steady-state error can be computed to be 0.
5:30 3.23 14:00 3.11
6:00 3.21 14:30 3.11
6:30 3.20 15:00 3.12
7:00 3.25 15:30 3.13
7:30 3.25 16:00 3.16
8:00 3.25 16:30 3.15

Fig. 11. Theoretical Step Response of the System with Integral Controller

To get the theoretical error reponse, we note that,


Fig. 9. Step Response of the Integral Controller 𝑅(𝑠)
𝐸(𝑠) =
1 + 𝐺𝑐 (𝑠)𝐺(𝑠)
From experiment 1, the VTEMP-MAX (steady-state value taken from the data in
0.055 experiment 1) may have changed which in effect changes the
𝐺(𝑠) = value of Vdesired.
1
𝑠+
144.155

Since Gc(s) is an integral controller,


1
𝐺𝑐 (𝑠) =
𝑠
𝑉𝑑𝑒𝑠𝑖𝑟𝑒𝑑
𝑅(𝑠) = , where Vdesired = 3.6
𝑠
𝑅(𝑠)
𝐸(𝑠) =
1 0.055
1 + ( )( 1 )
𝑠
𝑠+
144.155
𝑠(𝑠 + 0.0069) 3.6
𝐸(𝑠) = 2 ∙
𝑠 + 0.0069𝑠 + 0.055 𝑠

At steady-state: Fig. 13. Theoretical and Actual Error Response

𝑠(𝑠(𝑠 + 0.0069)) 3.6 0 The plot in Fig.13 shows the theoretical and actual error
𝑒𝑠𝑠 = lim 𝑠𝐸(𝑠) = lim 2
∙ = response of the system. As can be computed using the equation
𝑠→0 𝑠→0 𝑠 + 0.0069𝑠 + 0.055 𝑠 0.055 for E(s) solved in the preceding section, theoretical steady-state
=0
error should be 0 which matches the plot in Fig.13 labelled as
‘Theoretical’.The plot labelled as ‘Actual-initial’ is the error
response of the system on the first trial which matches the
theoretical response. The plot labelled as ‘Actual-final’, is the
error response of the system on the succeeding trials, as
explained before. The steady-state error deviates from the
expected value, which is theoretically 0, and experimentally
should be less than that of the proportional controller. The
cause of this deviation is the same as the explanation given with
the step response deviation.

III. CONCLUSION
The goal of the experiment was to modify the previously
constructed fully functional plant of a temperature-controlled
system into a closed-loop system. This was implemented using
Fig. 12. Theoretical and Actual Step Response a unity feedback gain, designed using a difference amplifier.
An additional forward gain was also introduced using a
The plot in Fig.12 shows the actual and theoretical step proportional controller (a non-inverting amplifier) and an
response of the system. From the computation of the error integral controller (cascade of integrator and inverting
response of the plant presented and as the plot labelled amplifiers). The latter one increases the type of the system from
‘Theoretical’ in Fig.12 shows, the steady-output should reach 0 to 1, and hence decreasing the steady state error, theoretically
the value Vdesired=3.6. The plot labelled as ‘Actual-initial’ is the to 0, given a step input. Some significant deviations from the
response of the plant with integral controller at first trial. The theoretical computations were obtained in the integral
response matches with the theoretical one in terms of the controller most likely because of the change in the behavior of
expected overshoot, oscillations, and estimated steady-state the original open loop system. This may be caused by non-
value. idealities, defective components, and/or the change in ambient
conditions.
However, on the succeeding trial, labelled as ‘Actual-final’
in Fig.12, the system’s response deviated from the expected REFERENCES
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system.html
deviated from Vdesired. The observed discrepancy may be caused [2] (2018) Electronics Tutorials Op-Amp [Online]. Available:
by a change in the plant itself. A component may have been https://www.electronics-tutorials.ws/opamp/opamp_6.html
defective, the ambient conditions may have changed, and some [3] (2018) Electronics Tutorials Op-Amp [Online]. Available:
parameters in the system may have been modified. For example, https://www.electronics-tutorials.ws/opamp/opamp_8.html