HARDWARE DESCRIPTION LANGUAGES SUCH AS VHDL HAVE SEVERAL

ADVANTAGES

 They provide precise, technology-independent descriptions of digital circuits at various

levels of abstraction
 Widely used for documentation purposes
 Can be processed by computers and so are suitable for use with computer-aided design
(CAD)
VHDL DESCRIPTION HAS TO MAIN PARTS

 Entity – A formal statement of the system’s architecture at the highest level, that is as a
single component. (block symbol)
 Architecture – specifies behavior and/or internal structure (truth table)
FLOWCHART OF AN ITERATIVE DESIGN PROCESS

THREE IMPORTANT WAYS TO THE OVERALL DESIGN PROCESS

 CAD editors or translators – convert design data into forms such as HDL descriptions or
schematic diagrams, which humans, computers, or both can efficiently process.
 Simulators – create computer models of a new design, which can mimic the design’s
behavior and help designers determine how well the design meets various performance
and cost goals.
 Synthesizers – automate the design process itself by deriving structures that implement
all or part of the some design step.
DESIGN LEVELS
  Processor level – also called architecture, behavior or system level
 Register level – also called the register-transfer level (RTL)
 Gate level – also called the logic level
THUS IF A COMPLEX SYSTEM IS TO BE DESIGNED USING SMALL SCALE ICs OR A
SINGLE IC COMPOSED OF STANDARD CELLS, THE DESIGN PROCESS MIGHT CONSIST
OF THE FOLLOWING THREE STEPS. (TOP DOWN APPROACH)

 Specify the processor-level structure of the system

 Specify the register-level structure of each component type identified in step 1
 Specify the gate-level structure of each component type identified in step 2
FOUR-BIT RIPPLE CARRY

THE MAJOR COMPONENT TYPES AT THE REGISTER LEVEL

WORD-BASED LOGICAL OPERATIONS OF THIS TYPE ARE USEFUL IN SOME ASPECTS
OF REGISTER LEVEL DESIGN. HOWEVER, THEY DO NOT BY THEMSELVES PROVIDE
AN ADEQUATE DESIGN THEORY FOR SEVERAL REASONS

 The operations performed by some basic register-level components are numerical rather
than logical; they are not easily incorporated into a Boolean frame-work
 Many of the logical operations associated with register-level components are complex
and do not have the properties of the gates-interchangeability of inputs, for example-that
simplify gate-level design.
 Although a system often has a standard word length w based on the width of some
important buses or registers, some buses carry signals with a different number of bits.
For example, the outcome of a test on a set S of w-bit words is 1 bit rather than w. The
lack of a uniform word size for all signals makes it difficult to define a useful algebra to
describe operations on these signals.
MULTIPLEXER

4-BIT D REGISTER WITH PARALLEL IO

 4-BIT, RIGHT SHIFT REGISTER

TYPES OF BUSES
  Shared bus – To reduce costs, buses are often shared, especially when they
connect many devices. A shared bus is one that can connect one of several sources
to one of several destinations. Reduces the number of connecting lines but requires
a more complex bus-control mechanisms.
 Dedicated buses – Permit simultaneous transfers between different pairs of devices
GENERAL APPROACH TO THE DESIGN PROBLEM

 Define the desired behavior by a set of sequences of register-transfer operations, such

that each operation can be implemented directly using the available design components.
This constitutes an algorithm AL to be executed.
 Analyze AL to determine the types of components and the number of each type required
for the datapath DP
 Construct a block diagram for DP using the components identified in step 2
 Analyze AL and DP to identify the control signals needed. Introduce into DP the logic or
control points necessary to apply these signals.
 Design a control CU for DP that meets all the requirements of AL
 Verify, typically by computer simulation, that the final design operates correctly and
meets all performance-cost goals.

MAJOR COMPONENTS OF A COMPUTER SYSTEM

INTERNAL ORGANIZATION OF A CPU AND CACHE MEMORY

The figure shows the essential internal organization of a CPU at the register level. The CPU
contains the logic needed to execute its particular instruction set and is divided into datapath
and control units. The control part generates the addresses of instructions and data stored in
external memory. In this particular system cache memory is interposed between the main
memory M and the CPU. The cache is a fast buffer memory designed to hold an active portion
of the system’s address space. Each memory request generated by the CPU is first directed to
the cache. If the required information is not currently assigned to the cache, the request is re-
directed to M and the cache is automatically updated from M. The I-unit fetches instructions
from the cache and decodes them to derive the control signals needed for their execution. The
CPU’s datapath (E-unit) has the arithmetic logic circuits that execute most instructions; it also ha
a set of registers for temporary data storage
THE MEMORY PART OF A COMPUTER CAN BE DIVIDED INTO SEVERAL MAJOR
SUBSYSTEMS

 Main memory M, consisting of relatively fast storage ICs connected directly to and
controlled by, the CPU
 Secondary memory, consisting of less expensive devices that have very high storage
capacity. These devices often involve mechanical motion and so are much slower than
M. They are generally connected indirectly (via M) to the CPU and form part of the
computer’s IO system.
 Many computers have a third type of memory called a cache, which is position between
the CPU and main memory. The cache is intended to further reduce the average time
taken by the CPU to access the memory system. Some or all of the cache may be
integrated on the same IC chip as the CPU itself.
 THE SYNCHRONIZATION PROBLEM CAN BE ATTRIBUTED TO SEVERAL CAUSES

 A high degree of independence exists among the components. For example, CPUs
and IOPs execute different types of programs and interact relatively infrequently and
at unpredictable times
 Component operating speeds vary over a wide range. CPUs operate from 1 to 10
times faster than main-memory devices, while main-memory speeds can be many
orders of magnitude fast than IO-device speeds
 The physical distance separating the components can be too large to permit
synchronous transmission of information between them.
THE COMMON APPROACH TO DESIGN AT THIS LEVEL IS TO TAKE A PROTOTYPE
DESIGN. THE PERFORMANCE SPECIFICATIONS USUALLY TAKE THE FOLLOWING
FORM.

 The computer should be capable of executing a instructions of type b per second.

 The computer should be able to support c memory or IO devices of type d.
 The computer should be compatible with computers of type e.
 The total cost of the system should not exceed f.
VARIOUS PERFORMANCE PARAMETERS CAN CHARACTERIZE THE STEADY-STATE
PERFORMANCE OF THE SINGLE-SERVER QUEUEING SYSTEM UDNER THE
FOREGOING ASSUMPTIONS

 The utilization p = lambda / mu of the server, that is the average fraction of time it is busy
 The average number of tasks queued in the system, including tasks waiting for service
and those actually being served. lq = p/(1-p)
 The average time that arriving tasks spend in the system, both waiting for service and
being served which is called the mean waiting time tQ. tQ = Iq / lambda