Simulation Tips and Tricks

Global Power Seminar 2007

www.fairchildsemi.com

Agenda

• A PSPICE resistor model having dynamic temperature capability

• Thermal modeling
• Simple voltage controlled reactive models
• Diode reverse recovery current waveforms: accuracy limitations
• Convergence issues
• MOSFET symbol usage
• Fairchild Semiconductor on-line tools

1
 A PSPICE Resistor Model Having Dynamic
Temperature Capability

• Dynamic temperature information can be a problem.

- PSPICE does not allow node dependent dynamic
temperature dependent resistor models.
- Resistor temperature dependence is preset in the setup
menu.
- A temperature sweep is the alternative.
- A closed loop form solution cannot be achieved.

A PSPICE Resistor Model Having Dynamic

Temperature Capability

• Expressing resistor temperature

coefficients as an analog
behavioral model (ABM)
referenced to a voltage node is
+ +
necessary.
• A voltage controlled current I I=V/R(Tj)
source permits dynamic thermal
modeling. - -

G_Resistor Node1 Node2 Value={V(node1,Node2)/

+function(V(Tj))}

2
 Agenda

• A PSPICE resistor model having dynamic temperature capability

• Thermal modeling
• Simple voltage controlled reactive models
• Diode reverse recovery current waveforms: accuracy limitations
• Convergence issues
• MOSFET symbol usage
• Fairchild Semiconductor on-line tools

Thermal Modeling

• Measurement of semiconductor
thermal response involves a
calibrated power pulse. Tjunction ZθJC Tcase ZθCS Tsink ZθSA Tambient

ΔTJ ( t ) TJ ( t ) − TJ (0)
ZθJC ( t ) = = Power Die Insulator & Heat sink

PD PD Dissipation
interface

• Semiconductor model and its G_Pdiss

electrical analog. Transistor

TJ = Tambient + G _ Pdiss • ( Z θJC + Z θCS + Z θSA )

3
 Thermal Modeling

• ZθJC is provided in data sheets.

• ZθJC may be represented using
an equivalent electrical analogy
empirical model.
• Model parameters may be
derived from the data sheet RθJC
and using the single pulse
normalized thermal transient
impedance curve data points. −t −t

Z( t ) = R 1 ⋅ (1 − e R1⋅C1 ) + K + R 6 ⋅ (1 − e R 6 ⋅C6 )

Thermal Modeling

• Junction temperature is determined with ZθJC and

G_PDISS.
- G_PDISS is device instantaneous power loss.
- TJ = junction temperature.
- G_Pdiss = instantaneous power loss (application specific).
- ZθJC = thermal impedance junction-to-case (provided by Fairchild).
- ZθCS = thermal impedance case-to-heat sink (application specific).
- ZθSA = thermal impedance heat sink-to-ambient (application specific).

Tjunction ZθJC Tcase ZθCS Tsink ZθSA Tambient

Power Die Insulator & Heat sink

interface
Dissipation

G_Pdiss

Transistor

4
 Thermal Modeling

• Thermal response to complex

waveforms may be analyzed.
• Example: a 60A/40ms fault
current pulse is applied to a
9mΩ/40V FDB8445 MOSFET
having a starting case
temperature of 120oC.
25

- ZθJC Æ R1-R6/C1-C6.

Resistance (mOhms)
20

- G6 models temperature
15

10

dependent RDS(on). 5

0
V(Vds)/ I(V4) (mOhms)

0 5 10 15 20 25 30 35 40 45 50

- G8 models instantaneous Time (ms)

power loss. 70 240

Temperature ( C)
60 220

- V(Tjunction) Æ Closed loop

o
Current (A)
50 200

40 180

30 160

junction temperature. 20
10 I(I4) (A) V(Tjunction) (C)
140

120

0 100
0 5 10 15 20 25 30 35 40 45 50
Time (ms)

Agenda

• A PSPICE resistor model having dynamic temperature capability

• Thermal modeling
• Simple voltage controlled reactive models
• Diode reverse recovery current waveforms: accuracy limitations
• Convergence issues
• MOSFET symbol usage
• Fairchild Semiconductor on-line tools

10

5
 Simple Voltage Controlled Reactive Models

• Simple implementation of non-

linear inductor and capacitor
models.
- Power supply filter inductors,
solenoid coil inductance.
- Ceramic capacitors and
MOSFET with voltage
dependent capacitance.
• PSPICE ANL_MISC.LIB library
includes such models.
- Non-linear inductor model:
ZX.LIB.
- Non-linear capacitor model:
YX.LIB.

11

Simple Voltage Controlled Reactive Models

• Non-linear inductance model.

d iLref
V3 = Lref ⋅
dt

V4 = Vcontrol ⋅ V3
d i Lref
V4 = ( Vcontrol ⋅ Lref ) ⋅
dt
iLref = iRinductor
d iRinductor
V4 = ( Vcontrol ⋅ Lref ) ⋅
dt
1.25

• Inductor voltage VL = V(4a,5)

Inductance (μH)

1.00
L = 1μ H

- includes winding resistance

0.75
Vcontrol = 1.0V
Vcontrol = 0.25V
0.50
L = 0.25μH
0.25
di
VL = ( Vcontrol ⋅ Lref ) ⋅ Rinductor + Rinductor ⋅ iRinductor
0.00
140 145 150 155 160 165
dt
Time (μs)
V(4a)/d(I(Rinductor)) (uH)

where, 2.0
Voltage or Current

1.5

VL = inductor voltage 1.0

0.5
0.0

iRinductor = inductor current

-0.5
-1.0
-1.5
-2.0
0 < Vcontrol < 1. 140 145 150 155 160 165
Time (μs)
I(Rinductor) (A) V(4a) (V)

12

6
 Saturable Inductor Model Example

• Magnetics Inc MPP 55652 60μ powder core.[16]

• Design details:
• AL = 38mH +8%
• N = 249 turns
• Lmin = 2.17mH at 0A (0 Oersted)
• Lmin = 1.04mH @ 3A (104.9 Oersteds)
• Permeability saturation expression
2 −4 3 −9 4 2
m − 1.505⋅ 10 ⋅ m ⋅ H + 6.100⋅ 10 ⋅m ⋅H
−4 −8 2 2
1 − 1.277⋅ 10 ⋅ m⋅ H + 2.740⋅ 10 ⋅m ⋅H

• Per unit Spice inductor saturation expression

3 2
3600 − 1.13652× 10 ⋅ I + 96.62895I
⋅
2
1 − 0.26787I
⋅ + 0.12057I
⋅
60

13

Saturable Inductor Model Example

1.1
1.0
Inductance (mH)

0.9
0.8
0.7
0.6
0.5
0.4
1.05mH 0.3
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2

at 3.0A Time (ms) V(4a,5)/d(i(Rinductor))

5.5

5.0
Current (A)

4.5

4.0

3.5

3.0
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Time (ms) I(Rinductor)

14

7
 Simple Voltage Controlled Reactive Models

• Non-linear capacitor model.

1
VCref =
Cref ∫
⋅ i Cref ⋅ d t

i CREF = iFCOPY

1
VCref =
Cref ∫
⋅ i FCOPY ⋅ d t

1200

1000
VCref = Vcontrol ⋅ V4

Capacitance (nF)
800 Vcontrol = 1.0V
600 Vcontrol = 0.25V C = 1μF

400
C = 0.25μH
1
V4 =
Vcontrol ⋅ Cref ∫
⋅ i FCOPY ⋅ d t 200

0
0 5 10 15 20 25

where
Time (μs) (1/V(4))*S(I(Fcopy))

V4 = non-linear capacitor voltage 0.6

Voltage or Current
0.4

iFCOPY = non-linear capacitor current 0.2

0.0

0 < Vcontrol < 1.

-0.2

-0.4

-0.6
0 5 10 15 20 25

Time (μs) I(V2) V(4)

15

Agenda

• A PSPICE resistor model having dynamic temperature capability

• Thermal modeling
• Simple voltage controlled reactive models
• Diode reverse recovery current waveforms: accuracy limitations
• Convergence issues
• MOSFET symbol usage
• Fairchild Semiconductor on-line tools

16

8
 Diode Reverse Recovery Current
Waveforms: Accuracy Limitations
25A

20A

15A

10A

• Fairchild MOSFET PSPICE 5A

models include IRM. 0A

-5A

• Modeled under data sheet

1.95us 2.00us 2.05us 2.10us 2.15us 2.20us 2.25us 2.30us
I(X1:s)
Time

Simulated FDB8441 diode reverse

conditions. recovery waveform at 25oC, 100A/μs.
• May not be accurate under wide
range of operating conditions.

Measured FDB8441 diode reverse

recovery waveform at 25oC, 100A/μs.

17

Diode Reverse Recovery Current

Waveforms: Accuracy Limitations

• Simulations show little variation

as a function of temperature and
ISD..
• The PSPICE diode model has
limited access to parameters.
• Diode modeling is limited with
SPICE based models.

18

9
 Agenda

• A PSPICE resistor model having dynamic temperature capability

• Thermal modeling
• Simple voltage controlled reactive models
• Diode reverse recovery current waveforms: accuracy limitations
• Convergence issues
• MOSFET symbol usage
• Fairchild Semiconductor on-line tools

19

Convergence Issues

• Contributors
- Large complex circuit
- Layout parasitic elements
- Incorrect initial conditions
- Simulation tolerance settings
- Complexity of macro models

20

10
 Convergence Issues

• Large complex circuit.

- Simplify where possible.
- Simple model used to replace
complex model.
• Layout parasitic elements.
- Large value resistors across R = 2π ⋅ fq ⋅ L
inductors and capacitors.
- Recommended inductors have
parallel resistor.
- Models eddy currents and
bandwidth limitation fq.

21

Convergence Issues

• Initial conditions out of range.

- Specify initial voltage on
capacitors.
- Specify initial current on
inductors.
• Simulation tolerances set too
low.
- Relax tolerances
- ABSTOL to 1μA
- CHGTOL to 1.0pC
- ITL1 to 150
- ITL2 to 150
- ITL4 to 150

22

11
 Convergence Issues

LDRAIN
1
BSIM3
Nch Spice Model 5 2
DRAIN

• Complex MOSFET model. RDRAIN

DBREAK
RLDRAIN

• Use of Fairchild’s BSIM3 based 16

MOSFET model improves 1

LGATE 17 11 DBODY
+
performance relative to previous 1
RGATE
9 6
7
-
EBREAK
+
-

LSOURCE
level 1 and level 3 models.
GATE BSIM3
1

RLGATE 7 3

• Reduced component count SOURCE

compared to level 1 model 17 RLSOURCE

36 components down to 14. IT RBREAK

• Reduced simulation time. 7

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Agenda

• A PSPICE resistor model having dynamic temperature capability

• Thermal modeling
• Simple voltage controlled reactive models
• Diode reverse recovery current waveforms: accuracy limitations
• Convergence issues
• MOSFET symbol usage
• Fairchild Semiconductor on-line tools

24

12
 MOSFET Symbol Usage

• Fairchild MOSFETsymbol.
• Compatible with OrCAD
Capture and OrCAD Schematic.
• Quick method to simulate
various models
- Only model name needs to be
changed.

25

MOSFET Symbol Usage

• Place Part window. • Simulation Settings window.

- Add library file that was saved - Browse to find library file.
to working directory. - Select “Add to Design” or “Add
- Select “Fairchild MOS Std” and as Global”.
place on schematic.

26

13
 MOSFET Symbol Usage

• Simulating a different MOSFET model.

- Select current model name on schematic.
- Enter name of new model to be simulated.
- Add library file to simulation profile.
- Required if not previously defined.

27

Agenda

• A PSPICE resistor model having dynamic temperature capability

• Thermal modeling
• Simple voltage controlled reactive models
• Diode reverse recovery current waveforms: accuracy limitations
• Convergence issues
• MOSFET symbol usage
• Fairchild Semiconductor on-line tools

28

14
Fairchild Semiconductor On-Line Tools

29

Fairchild Semiconductor On-Line Tools

30

15
Fairchild Semiconductor On-Line Tools

31

Device Analysis

32

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Device Analysis

33

Fairchild Semiconductor On-Line Tools

34

17
Application:
Synchronous rectifier buck converter

35

Application:
Synchronous rectifier buck converter

36

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 Fairchild Semiconductor On-Line Tools

37

References
1. R. H. Randall, A. Laprade, B. Wood "Characterizing IGBT Switching Losses for
Switched Mode Circuits", PCIM Europe 2000, pp. 269-275, June 2000.
2. R. H. Randall, A. Laprade, A. Craig, "Analyzing IGBT Losses by Translating Empirical
Data Into SPICE Behavioral Models", PCIM Europe 2000, pp. 263-268, June 2000.
3. Fairchild Semiconductor Corporation, Mountaintop, PA, Data Sheet HGTP12N60A4D,
http://www.fairchildsemi.com.
4. R. H. Randall, A. Laprade, “Behavioral Model Analyzes IGBT Losses in Sinusoidal
Circuits“ PCIM Europe 2001, pp. 165-170, June 2001.
5. “Exploring the Nature of Spice Convergence Problems”, OrCAD Design Network, 5/99.
6. http://www.fairchildsemi.com/models/PSPICE/Discrete/MOSFET.html
7. http://www.fairchildsemi.com/designcenter/index.html
8. http://www.transim.com/fairchild/index.html
9. http://www.fairchildsemi.com/whats_new/spm_tool.html
10. http://www.fairchildsemi.com/whats_new/offline_smps_toolkit.html
11. http://www.fairchildsemi.com/whats_new/pfc_toolkit.html
12. Fairchild Semiconductor Corporation, Mountaintop, PA, Data Sheet FDB8445,
http://www.fairchildsemi.com.
13. http://www.fairchildsemi.com/models/Pspice_Bsim3.1/Discrete/MOSFET.html
14. Fairchild Semiconductor Corporation, Mountaintop, PA, Data Sheet FDB8441,
http://www.fairchildsemi.com.
15. http://www.systat.com/products/TableCurve2D/
16. http://www.mag-inc.com/powder/2006_Powder_Core_Selection.pdf, MPP55586 design
example, page 2.

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