Int. J. Electron. Commun.

(AEÜ) 64 (2010) 47 – 55
www.elsevier.de/aeue

New CMOS DVCC realization and applications to instrumentation amplifier

and active-RC filters
Tarek M. Hassan, Soliman A. Mahmoud∗
Electrical and Electronics Engineering Department, Faculty of Information Engineering and Technology, German University in Cairo
(GUC), Egypt
Received 1 June 2008; accepted 23 November 2008

Abstract
This paper presents a novel CMOS differential voltage current conveyor (DVCC) based on a wide linear range transcon-
ductor with common mode detection. The DVCC exhibits a wide dynamic input range of ±0.9 V. It is used to realize an
instrumentation amplifier, a multiple input single output filter, and a single input multiple output universal filter. PSPICE sim-
ulations of the proposed DVCC and its based applications are given using 0.25 m CMOS technology from TMSC MOSIS
and dual supply voltages ±1.5 V.
䉷 2008 Elsevier GmbH. All rights reserved.

Keywords: Differential voltage; Current conveyor; Transconductor; Filter; Instrumentation amplifier

1. Introduction terminal device with the following properties (Fig. 1):

Since its first introduction, by Sedra and Smith [1], the
second-generation current conveyor (CCII) has proved to be
a versatile analog building block that can be used to imple-
ment numerous high frequency analog signal applications,
like filters [2–6] and current-mode oscillators [7]. However,
when it comes to applications demanding differential or
floating inputs like impedance converters and current-mode
instrumentation amplifiers, which also require two high in-
put impedance terminals, a single CCII block is no more
sufficient. In addition, most of these applications employ
floating elements in order to minimize the number of used
CCII blocks. For this reason and in order to provide two
high input impedance terminals, the differential voltage cur-
rent conveyor (DVCC) was proposed in 1997 [8] as a four
∗ Corresponding author. Fax: +20 2 7581041.
E-mail address: soliman.awad@guc.edu.eg (S.A. Mahmoud).
1434-8411/$ - see front matter 䉷 2008 Elsevier GmbH. All rights reserved.
doi:10.1016/j.aeue.2008.11.002
⎡ I ⎤ ⎡0 0 0 0⎤ ⎡ V ⎤
Y1 Y1
⎢ IY2 ⎥ ⎢ 0 0 0 0 ⎥ ⎢ VY2 ⎥
⎣ V ⎦ = ⎣ 1 −1 0 0 ⎦ ⎣ I ⎦ (1)
X X
IZ 0 0 1 0 VZ
While the X terminal voltage follows the voltage difference
of terminals Y1 and Y2, a current injected at the X terminal
is being replicated to the Z terminal. An ideal DVCC exhibits
zero input resistance at terminal X, and infinite resistance at
both Y terminals as well as the Z terminal. The flow direction
of the output current follows the input current direction with
both currents flowing either into or out of the device. Since
the DVCC exhibits two high input impedance terminals, it
shows itself suitable for handling differential input signals.
In addition, it has the advantage of minimizing the number
of floating elements inherent in many CCII applications.
In this paper a new wide range CMOS DVCC operating
under a supply voltage of ±1.5 V is proposed. The input
stage of the proposed DVCC is realized using two wide
linear range transconductors. The output stage consists of
48 T.M. Hassan, S.A. Mahmoud / Int. J. Electron. Commun. (AEÜ) 64 (2010) 47 – 55
Fig. 1. Block representation of the DVCC.
a Class-AB CMOS push–pull network, which guarantees
high current driving capability and low standby current. In
addition, this paper proposes a new multiple input single
output (MISO) filter based on the presented DVCC. Further-
more, a new single input multiple output (SIMO) universal
filter with grounded elements is demonstrated. This paper is
organized as follows: in Section 2 the proposed wide range
DVCC circuit is presented. Thereafter, DVCC applications
including the MISO and the SIMO filters are discussed in
Section 3. PSPICE simulations for all proposed circuits are
provided using 0.25 m TSMC CMOS technology.
2. Proposed DVCC CMOS circuit realization
2.1. Circuit description
range, it is well known that the differential input voltage
applied to a LTDP is limited by
− 2I SS /K < Vid < 2I SS /K (5)
Hence, in order to increase the input range of the transcon-
ductor the ratio I SS /K should be increased. Such condition
is spontaneously satisfied if the tail current is dynamically
increased as in Eq. (3), which ensures an extended differ-
ential input range. Biasing the LTDP with a constant tail
current, on the other hand, will require a high I SS /K ratio.
Unfortunately, this affects the minimum possible common
mode input voltage, whose value must maintain the tail
biasing transistor in saturation [9]. The main concern now
is how to realize Eq. (3). Considering the differential pair
currents, they are given by
K
IM1 = (VY2 − VS − VT )2 (6)
2
K
IM2 = (VY1 − VS − VT )2 (7)
2
So taking into account that the input signals of a differential
pair can be divided into a common mode voltage (VC M ) and
a differential voltage (Vid ) with VY1 = Vid /2 + VC M and
VY2 = −Vid /2 + VC M where VC M = (VY1 + VY2 )/2, then
the tail current can be expressed by
 

The circuit realization of the proposed DVCC (Fig. 2) is Vid2
I SS = IM1 +IM2 = K +(VC M −VS −VT ) 2
(8)
based on equalizing the output currents of two wide linear 2
range transconductors, formed by transistors (M1–M18). In
addition, (M19–M22) comprise a Class-AB output stage, Obviously, I SS will follow the function given in Eq. (3), if
providing current swings up to ±1 mA. Moreover, the cur- the subsequent expression is set to a constant value:
rent at the X terminal is transferred to the Z terminal with
the aid of (M23, M24), which must be – for a unity current VC M − VS − VT = c (9)
gain – matched with (M21, M22), respectively. All transis- A simple source follower (M13), whose gate is connected to
tors are assumed to be operating in saturation. The opera- the common mode voltage of the LTDP, and whose source
tion of a wide linear range transconductor relies mainly on is clamped to the differential pair coupled source, can be
biasing a long tail differential pair LTDP (M1–M2) with used to satisfy Eq. (9). In this case, the source follower
a dynamic tail current I SS that increases with Vid2 where should have a constant drain current, set by M11, so that c is
Vid = VY1 − VY2 . Since the output current produced at the equal to
drains of M2 and M6 is expressed by 
 2I B
Iout = IM1 − IM2 = −K V id I SS /K − (Vid /2)2 (2) c= (10)
K 13
where K represents the transconductance parameter of M1 As a consequence, the current equations result into
or M2, then if the tail current is set to
  2
I SS = K [(Vid /2)2 + c2 ] (3) K Vid 2I B
IM1 = − + (11)
2 2 K 13
A linear relation between the output current and the differ-
ential input voltage can be obtained with   2
K Vid 2I B
IM2 = + (12)
Iout = −K cV id (4) 2 2 K 13
Obviously, the value of c should be constant, which along
 2

Vid 2I B
with the transconductance parameter K is defining the overall Iss = K + (13)
gain of the transconductor. Concerning the dynamic input 2 K 13
 T.M. Hassan, S.A. Mahmoud / Int. J. Electron. Commun. (AEÜ) 64 (2010) 47 – 55 49

Fig. 2. CMOS realization of the proposed DVCC.


2I B
Iout = −K Vid (14)
K 13

 2  
Vid 2 1
IM9 = I SS + I B = K + IB + (15)
2 K 13 K

From the previous equations, the standby current of M1 and

M2 is defined by the value 2I B /K 13 . For differential input
voltages greater than twice the square root of 2I B /K 13 M1
turns off and the current flowing in M2 increases. On the
other hand, as the differential input voltage is decreased
below twice the square root of 2I B /K 13 , M2 turns off and the
current flowing in M1 increases. In both cases, M9 should
feed the necessary current required for proper operation of
M1 and M2 even if it enters slightly in the linear region.
Fig. 3. Common mode detection circuit.
Therefore, the problem with the minimum common mode
input voltage required to maintain the tail biasing transistor
in saturation has less effect in this circuit. Furthermore, since is limited by
both M1 and M2 are ‘ON’ at standby, this circuit exhibits low
distortion. It should be also noted that the current flowing −2 2IC /K 25 < Vid < 2 2IC /K 25 (17)
in M9 will change by feedback action, formed by M15, in
Moving back to the DVCC circuit, the voltage follower
order to stabilize the value of VS . In addition, the dynamic
is implemented by connecting the outputs of two identical
differential input range is extended to
transconductors, producing the following total current at the
drain of M2:
−2 2I B /K 13 < Vid < 2 2I B /K 13 (16) 
2I B
Consequently, the compromise between the differential in- Iout1 + Iout2 = K [−(VY1 − VY2 ) + (VX − 0)] = 0
K 13
put voltage range and the LTDP standby current limits the
(18)
performance of the transconductor. Concerning VC M , if the
input voltages are fully differential or balanced, VC M1 is a In consequence, the voltage at the X terminal follows the
constant value that can be applied directly to the gate of voltage difference of terminals Y1 and Y2. This condition is
M13. Otherwise, a common mode detection circuit like the valid as long as both output currents are linear, which is guar-
one shown in Fig. 3 is used to track VC M . For proper op- anteed over a wide range when using the proposed transcon-
eration of the common mode detection circuit, all transis- ductor. Concerning the gate voltage of M14, it should follow
tors should be working in saturation mode, while M25–M28 the common mode voltage of the input signals applied to
should be matched. The input dynamic range of this circuit M3 and M4. As these inputs are neither fully differential nor
50 T.M. Hassan, S.A. Mahmoud / Int. J. Electron. Commun. (AEÜ) 64 (2010) 47 – 55

Table 1. Transistor aspect ratios for the proposed DVCC.

Transistors W (m) L (m)

M1–M4 0.5 4
M5–M8 1 1
M9–M12, M19–M20, 0.5 0.5
M25–M28
M13–M14 0.5 1
M15–M16 5 0.5
M17–M18 1 0.5
M21–M24 20 0.25
M29–M30 6 2
M31–M32 5 2
Fig. 5. Magnitude frequency response of the voltage transfer gain.

Fig. 4. The X and Z terminal output voltages versus changes

of Vid . Fig. 6. Input and output voltage referred noise spectral densities.

balanced, a common mode detection circuit becomes essen-

tial for the second transconductor, producing VC M2 =VX /2.

2.2. Simulation results

The performance of the proposed COMS DVCC was

verified by performing PSPICE simulations with supply
voltages ±1.5 V using 0.25 m TSMC CMOS technology.
Simulations were carried out using balanced input volt-
ages with transistor aspect ratios given in Table 1. Fig. 4
presents the X and Z voltages versus the differential input
voltage, when the proposed DVCC is used to realize a
unity gain amplifier with 5 k load resistance. The DVCC
shows good linearity for differential input voltages between Fig. 7. The Z terminal output current versus changes of IX .
±0.9 V, with a total standby power dissipation of 1.74 mW.
In Fig. 5 the magnitude response of the DVCC with a
differential voltage ac-varying signal of 0.5 V magnitude Fig. 9 clarifies the push–pull action of the Class-AB out-
and open-circuited output terminals is demonstrated. The put stage with a standby current of 136 A. Moreover, the
DVCC shows a flat response with 85 MHz 3-dB BW. The magnitude response of the DVCC with an ac-varying input
input and output referred noise spectral densities are then current of 10 A magnitude and a short-circuited Z terminal
displayed in Fig. 6. Thereafter, the Z terminal output cur- is displayed in Fig. 10. The DVCC provides a 120 MHz
rent versus the X terminal input current is shown in Fig. 7 3-dB bandwidth. The time response to a 1 MHz differential
with a ±1 mA linear range, while the variation of the offset square input voltage is tested in Fig. 11, resulting in a rise
voltage across the X terminal with grounded Vid is illus- time in the vicinity of 7.5 ns. Finally, the total harmonic
trated in Fig. 8. The X terminal input resistance RX is less distortion is evaluated for different differential input voltage
than 9  and the offset voltage does not exceed 8.2 mV. amplitudes (Fig. 12). A 1 MHz sinusoidal input generates
 T.M. Hassan, S.A. Mahmoud / Int. J. Electron. Commun. (AEÜ) 64 (2010) 47 – 55
Fig. 8. The offset voltage of the X terminal along with its
derivative.
Fig. 9. Driving capabilities of the output stage.
Fig. 10. Magnitude frequency response of the current transfer gain.
a THD factor less than 0.009. The power supply rejection
ratio (PSRR) from the positive supply to the output has
a value of 41.27 dB and from the negative supply to the
output is 50.3 dB. Table 2 compares the performance pa-
rameters of the proposed DVCC with a DVCC employing
constant tail current (omitting M11–M18, and the common
mode detector circuit). The proposed circuit exhibits a 2.25
times wider voltage range on the expense of a 49 W power
increase, and a 39% BW loss.
51
Fig. 11. The X terminal voltage along with a 0.5 V–1 MHz differ-
ential square input.
Fig. 12. X terminal total harmonic distortion (for frequencies
100 kHz and 1 MHz).
3. Applications based on the proposed DVCC
In this section the proposed DVCC is used to realize an in-
strumentation amplifier, a new MISO second-order LP–BP
filter, and a SIMO second-order universal filter. In all
applications one should recognize the benefits of using
differential voltage current conveyors, which focus on pro-
viding high input impedance circuit designs with grounded
elements.
3.1. Instrumentation amplifier
The first basic application that can be implemented us-
ing a DVCC is an instrumentation amplifier as shown in
Fig. 13. An instrumentation amplifier takes a differential in-
put voltage, multiplies it with a gain, and produces a single
52 T.M. Hassan, S.A. Mahmoud / Int. J. Electron. Commun. (AEÜ) 64 (2010) 47 – 55

Table 2. Performance comparison for the proposed DVCC.

Parameter Proposed DVCC Constant tail current DVCC

CMOS technology (m) 0.25 0.25

Power supply (VDD, VSS) (1.5 V, −1.5 V) (1.5 V, −1.5 V)
No. of transistors 32 16
Total power dissipation (mW) 1.74 1.25
Tail current Dynamic 10 A
Standby current of the output stage (ISB) (A) 136 136
PSRR+ (dB) 41.27 34.56
PSRR− (dB) 50.3 50.1
Input dynamic range with thel X terminal resistance 5 k  −0.9 V to 0.9 V −0.4 V to 0.4 V
Voltage transfer error 0.00136 0.00237
Current driving capability (mA) ±1 ±1
Current transfer error 0.0013 0.0051
X terminal offset voltage withl Y and Z are ground (mV) 8.2 24
X terminal input resistance () 9 32
X terminal open circuit BW (MHz) 85 137
Z terminal short circuit (MHz) 120 250
X terminal THD at Vid = 0.2 sin 2 f 0.0013 at 1 MHz 0.0069 at 1 MHz
Rise time/fall time (pulse √
0.25 V at 1 MHz) 7.48 ns/6.24 ns 3.2 ns/3.1 ns
Input referred noise (nV/√Hz) 130 94.64
Input referred noise (nV/ Hz) 132 94.56

Fig. 13. Circuit realization of the instrumentation amplifier.

ended output voltage. The relation between the output volt-

age and the differential input can be described by the fol- Fig. 14. DC transfer characteristics of the instrumentation amplifier
lowing equation: (G = 1–4).

R2
Vout = Vid
R1
Obviously, the ratio of the Z terminal resistance to the X
terminal resistance defines the gain G of the amplifier. In
addition, this circuit can realize an inverting or noninvert-
ing amplifier, by simply connecting Y1 or Y2 to ground,
respectively. One should also note that this circuit can be
utilized as a voltage-controlled voltage source (VCVS). In
order to verify the performance of the instrumentation am-
plifier, PSPICE simulations were carried out using ±1.5 V
supply voltages. The X terminal resistance was set to 2 k,
while the Z terminal resistance was scanned from 2 to 8 k
in steps of 2 k. The length of the output stage transistors
was increased to 0.75 m to minimize the channel length
modulation effect. Fig. 14 displays the DC gain of the in-
strumentation amplifier for G varying from 1 to 4, while
(19)
Fig. 15 is demonstrating the ac gain. The 3-dB BW proves
to be constant for different gain values.
3.2. MISO BP–LP filter
In this section the proposed DVCC is used to realize a
MISO second-order LP–BP filter as shown in Fig. 16. Two
different responses are achieved depending on the actual
active input. If the first input is active, while the second one
is grounded, an inverting bandpass response is obtained. On
the other hand, grounding the first input while activating
the second one generates a noninverting lowpass response.
This can be verified through direct analysis, obtaining the
 T.M. Hassan, S.A. Mahmoud / Int. J. Electron. Commun. (AEÜ) 64 (2010) 47 – 55 53

Table 3. Passive elements of the MISO filter.

LPF elements Value BPF elements Value

R, R1 –R2 1 k R 2 k
C1 0.25 nF R1 0.65 k
C2 0.5 nF R2 0.5 k
C1 0.8 nF
C2 0.2 nF

Fig. 15. Magnitude frequency response of the instrumentation

amplifier (G = 1–4).

Fig. 17. LP magnitude frequency response of the MISO filter.

Fig. 16. Circuit realization of the MISO filter.

following transfer equations and gains:

VO (S/C1 R)
=− (20)
V1 D(S)
VO (1/C1 C2 R2 R)
= (21)
V2 D(S) Fig. 18. BP magnitude frequency response of the MISO filter.
S 1
D(S) = S 2 + + (22)
R1 C 1 C 1 C 2 R2 R 465 kHz, which is very close to the theoretical value. Next,
R1 the bandpass response is tested by grounding V2 and inject-
Av B P = − (23) ing the ac-varying signal at V1. The passive element values
R
were optimized as shown in Table 3 to achieve a bandpass
AvL P = 1 (24) filter with a 7.4 quality factor Q and a 690 kHz center fre-
From Eq. (22), 0 and Q and of the filter are given by quency f 0 (Fig. 18).

1 3.3. SIMO filter
0 = (25)
C 1 C 2 R2 R
 The filter configuration presented in Fig. 19 realizes a
C1 SIMO universal filter with noninverting HP, BP and LP out-
Q = R1 (26) puts. This filter employs four DVCC blocks, two grounded
C 2 R2 R
capacitors, and five grounded resistors. The first two input
Simulation results prove the aforementioned relations with blocks operate as a summer and the last two are integra-
passive element values given in Table 3. In Fig. 17 a low- tors, with their outputs fed back to the input DVCC blocks.
pass response is generated by grounding V1 and applying This configuration, which resembles the CFOA based fil-
an ac-varying signal at V2. The cutoff frequency is around ter proposed in [10], provides several advantages over the
54 T.M. Hassan, S.A. Mahmoud / Int. J. Electron. Commun. (AEÜ) 64 (2010) 47 – 55

Table 4. Passive elements of the SIMO filter.

LPF, HPF elements Value BPF elements Value

R, R1 –R4 1 k R, R2 –R3 0.5 k

C1 0.25 nF R1 , R4 2 k
C2 0.5 nF C1 0.2 nF
C2 0.2 nF

Fig. 19. Circuit realization of the SIMO universal filter.

Fig. 21. BP magnitude frequency response of the SIMO filter.

From Eq. (30), 0 and Q and of the filter are given by


R
0 = (34)
R1 R2 R3 C 1 C 2
Fig. 20. LP and HP magnitude frequency responses of the SIMO 
filter. R1 C 1
Q = R4 (35)
R R 2 R3 C 2

typical active filters with CFOA. First, it has infinite input Fig. 20 shows the simulated highpass and lowpass frequency
and output impedances. Second, all elements are grounded. responses with the design parameters given in Table 4. The
By applying direct analysis to the filter blocks, the following simulated cutoff frequency equals to 469 kHz which is very
transfer functions and gains are obtained: close to the theoretical value. The design parameters are
then optimized as shown in Table 4 to achieve a bandpass
VH P (S 2 R(R3 + R4 )/R3 R4 ) response with Q = 8 and f 0 = 800 kHz (Fig. 21).
= (27)
Vi D(S)
VB P (S R(R3 + R4 )/R1 C1 R3 R4 ) 4. Conclusion
= (28)
Vi D(S)
In this paper, a novel CMOS DVCC based on a wide lin-
VL P (R(R3 + R4 )/R1 C1 R2 C2 R3 R4 ) ear range transconductor has been presented. The DVCC
= (29)
Vi D(S) has demonstrated a wide dynamic range in the vicinity of
±0.9 V for the voltage follower and a ±1 mA for the current
R R
D(S) = S 2 + S + (30) follower. The DVCC was used to implement an instrumen-
C 1 R1 R4 C 1 C 2 R1 R2 R3 tation amplifier, a MISO LP–BP filter, and a SIMO universal
R(R3 + R4 ) filter. The proposed DVCC circuit and the realized applica-
Av H P = (31) tions have been verified using PSPICE simulations.
R3 R4
R4 References
Av B P = 1 + (32)
R3
[1] Sedra A, Smith K. A second-generation current conveyor
R3
AvL P = 1 + (33) and its applications. IEEE Transactions on Circuit Theory
R4 1970;17:132–4.
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[2] Mahmoud SA. Fully differential CMOS CCII based on
differential difference transconductor. Analog Integrated
Circuits and Signal Processing 2007;50:195–203.
[3] Soliman AM. Current conveyors steer universal filter. Analog
Action 1995; 45–6.
[4] Mahmoud SA. New fully differential CMOS second-
generation current conveyor. ETRI Journal 2006;28:495–501.
[5] Mahmoud SA. Fully differential CMOS CCII based on
differential difference transconductor. Analog Integrated
Circuits and Signal Processing 2006;49:267–79.
[6] Mahmoud SA, Hashiesh MA, Soliman AM. Digitally
controlled fully differential current conveyor. IEEE
Transactions on Circuits and Systems I 2005;52:2055–64.
[7] Soliman AM. Current feedback operational amplifier based
oscillators. Analog Integrated Circuits and Signal Processing
2000;32:45–55.
[8] Elwan HO, Soliman AM. Novel CMOS differential voltage
current conveyor and its applications. IEE Proceedings
1997;144:195–200.
[9] Ismail AM, Soliman AM. Novel CMOS linearized balanced
output transconductance amplifier based on differential pairs.
Frequenz 1999;53:170–4.
[10] Soliman AM. Applications of the current feedback
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Tarek Hassan was born in Cairo,
Egypt, in 1978. He received the B.Sc.
degree in Electronics and Communi-
cations Engineering from Cairo Uni-
versity, Cairo, Egypt, in 2002. He
will be acquiring his M.Sc. degree in
Electrical and Electronics Engineering
from the German University in Cairo,
Cairo, Egypt, in 2007. He is currently
working as a research and teaching
55
assistant at the Electrical and Electronics Engineering Department,
German University in Cairo. His research interests are in circuit
theory; low-voltage analog CMOS circuit design, current-mode
analog signal processing, and mixed analog/digital programmable
analog blocks. He is currently also an IEEE student member.
Soliman Mahmoud was born in Cairo,
Egypt, in 1971. He received the B.Sc.
degree with honors in 1994, the M.Sc.
degree in 1996, and the Ph.D. degree
in 1999, all from the Electronics and
Communications Department, Cairo
University, Egypt. He is currently an
Associate Professor at the Electrical
Engineering Department, Fayoum Uni-
versity, Egypt. He is currently also a
visiting Associate Professor at the Electrical and Electronics Engi-
neering Department, German University in Cairo, Egypt. In 2005,
He was decorated with the Science Prize in Advanced Engineering
Technology from the Academy of Scientific Research and Tech-
nology. His research and teaching interests are in circuit theory,
fully integrated analog filters, high-frequency transconductance
amplifiers, low-voltage analog CMOS circuit design, current-mode
analog signal processing, and mixed analog/digital programmable
analog blocks.