Accepted Manuscript

Regular paper

FPGA Implementation of Fractional-order Chaotic Systems

Divya K. Shah, Rohit B. Chaurasiya, Vishwesh A. Vyawahare, Khushboo

Pichhode, Mukesh D. Patil

PII: S1434-8411(17)30364-3
DOI: http://dx.doi.org/10.1016/j.aeue.2017.05.005
Reference: AEUE 51876

To appear in: International Journal of Electronics and Communi-

cations

Accepted Date: 4 May 2017

Please cite this article as: D.K. Shah, R.B. Chaurasiya, V.A. Vyawahare, K. Pichhode, M.D. Patil, FPGA
Implementation of Fractional-order Chaotic Systems, International Journal of Electronics and Communications
(2017), doi: http://dx.doi.org/10.1016/j.aeue.2017.05.005

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 FPGA Implementation of Fractional-order Chaotic
Systems
Divya K. Shah1 , Rohit B. Chaurasiya1 , Vishwesh A. Vyawahare1 ,
Khushboo Pichhode1 and Mukesh D. Patil2
Department of Electronics Engineering, Ramrao Adik Institute of Technology, Nerul,
Navi Mumbai-400706
Department of Electronics and Telecommunication Engineering, Ramrao Adik Institute
of Technology, Nerul, Navi Mumbai

Abstract
This paper presents the digital implementation of fractional-order (FO) chaotic
systems on Field Programmable Gate Array (FPGA). In the proposed work
Simulink model of each chaotic system is first realized using HDL coder of
MATLAB, wherein each coefficient and signal is represented using a fixed
number of bits. The constructed design is translated into VHDL code us-
ing hardware generation block. This code is further translated into bit-
stream file using Quartus software. The chaotic system is implemented by
downloading the obtained bitstream file into Altera FPGA Cyclone IV E
(EP4CE11529C7N) chip. A methodology has been developed to construct
FO chaotic system using HDL coder. Five different FO chaotic systems, viz.,
Lorenz, Chen, Lü, Arneodo, and Lorenz Hyperchaotic system have been pre-
sented in the paper to illustrate the methodology. The systems have been
implemented on FPGA platform. Analysis of each chaotic system is carried
out on the basis of hardware resource utilization, static power analysis and
synthesis frequency on FPGA. The results show that FPGA provides high-
speed realizations with the desired accuracy and low power consumption for
FO chaotic systems.
Keywords: Nonlinear system, chaos, fractional-order chaotic system, HDL
coder, VHDL, FPGA implementation.

Preprint submitted to Elsevier May 13, 2017

1. Introduction
In recent years there is an increasing interest in theoretical research and
practical/hardware implementation of chaotic systems. The non-linear dy-
namics present in a system may lead to chaos, and is characterized by the
sensitivity to initial conditions [1]. Chaos theory mainly deals with systems
that are nonlinear in nature like turbulence, weather, stock market, biologi-
cal systems, and many more [2, 3]. These systems are characterized by the
impossibility to predict their behaviour. Fractional calculus, the calculus
dealing with the derivatives and integrals of non-integer order (real or com-
plex) is more than 300 years old topic [4, 5, 6]. However due to its high
complexity and the lack of physical interpretation, it was not accepted as a
useful mathematical tool. In recent years, applications of fractional calculus
has been rapidly growing. Literature is abundant with results which show
that fractional derivatives provide a more compact and faithful representa-
tion to many real-world and engineering systems [4].
Last decade has seen an upsurge of research activities in the area of
fractional-order (FO) non-linear systems. Many new chaotic systems have
been proposed by generalizing the time derivatives of variables to fractional
order. Numerical simulation of FO chaotic systems was presented in [4] and
MATLAB solution of FO chaotic circuits was presented in [7]. Parametric
analysis of FO non-linear system was reported in [8]. Numerical simula-
tion of FO Chen and Lu system [9], FO Chen and Chua [10], fractional-
order Voltas [11], Modified Van Der Pol [12], fractional-order Rossler, Multi
mode fractional-order chaos [13], fractional-order Modified Duffing System
[14], fractional-order Rossler System [15], fractional-order Newton Leipnik
[16], fractional-order Liu [17] have been carried out. In [18, 19] the use of
chaotic systems for applications like image encryption have been proposed.
FO Chaotic system without equilibrium is proposed in [20] and its circuit
implementation is also carried out. A simple chaotic electronic oscillator has
been implemented in [21].
The analog implementation (see [22]) has practical difficulties like sensi-
tivity of components to temperature, ageing, etc. The digital implementa-
tion overcomes these problems and also has many advantages like accuracy
and possible integration in embedded applications [23]. Because of this, the
digital implementation of chaotic systems is used in applications like data
encryption and secure communications between embedded systems. Digital
implementation of chaotic systems have been carried out on various hardware

2
platforms like Field Programmable Gate Arrays (FPGA) and common micro-
processors or special microprocessors like Digital Signal Processors (DSPs).
DSP implementation of chaotic system [24, 25] has many problems the pre-
dominant being the restriction of accuracy causing transition from infinite
set of numbers to a final set. There are a few references reporting the DSP
implementation of FO chaotic systems (see [26]).
Recently many digital implementations of chaotic systems have been pro-
posed and implemented using FPGA. The main advantage of employing
FPGA for implementation is its low consumption of power as compared to
other hardware platforms [1]. Low-power usage is due to a lower clock rate
and the absence of wasted cycles for the fetch/decode instruction in FPGA.
In this context, the use of FPGA technology makes it possible to optimize the
hardware resources required while allowing for real-time computing. FPGA
provide great trade-off between computational power and the processing flex-
ibility making them most suitable for the design of digital systems.
Considerable work has been done so far on the FPGA implementation
of integer-order (IO) chaotic systems, Chen chaotic generator [27], Rossler
system [28], Novel chaotic oscillator [29], 3D chaotic system [30], chaotic
oscillator [31] are implemented using RK-4 method. The Chen system [1],
Lorenz system [32, 33, 1], the Hyperchaotic system [34] are implemented on
FPGA using the MATLAB DSP builder toolbox. Reference [35] reports the
FPGA implementation of higher dimensional digital chaotic systems. See also
[36]. The Xilinx system tool generator implementation of following systems
is discussed in the literature: novel chaotic system [37], four wing chaotic
attractor [38], Lorenz chaotic system [39]. Design of four chaotic systems,
Liu-Chen, Lu, Chen and Lorenz, is demonstrated in [23]. FPGA implemen-
tation of multi-scroll chaotic oscillator for chaotic communication applied to
image processing is discussed in [40]. Also see [41] for FPGA implementation
of discrete time chaotic generators. Memristor based FO chaotic system and
its FPGA circuits were proposed in [42]. FPGA implementation of novel
chaotic system and its synchronization is presented in [43].
The majority of the above mentioned FPGA implementations of IO and
FO chaotic systems employ the Xilinx system generator framework. This
approach of FPGA implementation is lengthy and difficult to execute. A
simpler approach to implement the chaotic systems on the FPGA platform
through the easier front-end of MATLAB-Simulink has been proposed by [1].
It gives a systematic and algorithmic approach to use the Simulink and DSP
Builder to implement a chaotic system on FPGA. This work replaces the

3
DSP Builder by HDL coder in implementing the system. This methodology
considerably reduces the efforts, time and is easy to extend to a chaotic
system with any number of state variables. The steps (discussed in detail
in section 5 ) also involve simulation of chaotic systems using ModelSim.
Benchmarking the FPGA implementation results (time evolution of each
variable and phase plots) with the simulations performed in Simulink and
ModelSim is an added advantage of this approach. This paper attempts to
extend this approach to implement the following five fractional-order chaotic
systems on FPGA platform:
1. Fractional-order Lorenz system.
2. Fractional-order Chen system.
3. Fractional-order Lü system.
4. Fractional-order Arneodo system.
5. Fractional-order Lorenz Hyperchaotic system.
The motivation to choose these systems is their popularity among the re-
searchers working in the area of analysis and implementation of chaotic sys-
tems. Also, these systems are found to display a rich chaotic dynamics and
have been analyzed thoroughly. The addition of fractionality in the original
chaotic systems makes the analysis more interesting and such systems may
find applications in modeling complex nonlinear physical systems exhibiting
memory behaviour. The synchronization and control of these systems is a
challenging task and it is believed that any contribution to implement these
systems on FPGA will be helpful to researchers. Along with the implemen-
tation, the paper also carries out a comparative study of hardware resource
utilization, static power analysis and synthesis frequency estimation for im-
plementing these chaotic systems. It is shown with experimental results that
these parameters vary for each chaotic system and are dependent on the
chaotic dynamics.
The paper is organized as follows. Section 2 gives a brief introduction to
fractional calculus. Section 3 discusses the FO chaotic systems implemented
in this work. Hardware details are given in Section 4. Section 5 provides
details about MATLAB HDL coder. Section 6 presents the results of FPGA
implementation of FO chaotic systems. Analysis and comparison in terms of
resource utilization, static power analysis and frequency for the implemented
systems is presented in Section 7. Conclusion is given in section 8.

4
2. Fractional Calculus
Generalizing the integer derivative and integral orders to real and com-
plex numbers is an old concept and is popularly known as fractional cal-
culus [44, 45, 46, 47]. Since its inception in 1695, the topic has been ad-
dressed by eminent mathematicians, physicists and recently by engineers.
Last five decades have witnessed an active use of fractional differential equa-
tions (FDEs) involving fractional derivatives in modeling real-world and en-
gineering processes and systems [48, 49, 50]. There are many definitions of
fractional derivatives, but the three most popularly used are given below [44].
All these definitions assume function f (t) to be sufficiently smooth and
locally integrable.
1. The Grunwald-Letnikov (GL) definition
Using the short memory principle [45], it is defined as
[Xh ]
t−a

α
a Dt f (t) = lim h−α (−1)j α
Cj f (t − jh), (1)
h→0
j=0

where [x] means the integer part of x and α Cj is the binomial coefficient.
This definition is useful for numerical calculations.
2. The Riemann-Liouville (RL) definition
It is obtained using the Riemann-Liouville fractional-order integral and
is given as
Z
α 1 dn t f (τ )
a Dt f (t) = dτ, (2)
Γ(n − α) dt a (t − τ )α−n+1
n

for n − 1 < α < n, n ∈ Z+ .

3. The Caputo definition It is defined as
Z t
α 1 f n (τ )
D
a t f (t) = dτ, (3)
Γ(n − α) a (t − τ )α−n+1
for n − 1 < α < n, n ∈ Z+ , where f n (τ ) is the nth -order derivative of
the function f (t).
As it can be seen, a fractional derivative is a non-local operator. Thus,
it has been found very suitable for modeling systems with spatial dynamics,
hereditary properties and memory [48, 44, 45, 51, 52]. Literature is abundant
with case studies confirming the superiority of FDEs in terms of compactness
and realistic modeling for a plethora of systems.

5
3. FO chaotic systems
This section describes the five FO chaotic systems used in this work.

3.1. Fractional-order Lorenz System

The Lorenz oscillator is a three-dimensional dynamical system that ex-
hibits chaotic flow [4]. It gives the simplified equations modeling convection
rolls arising in atmosphere. The system of equations for FO Lorenz system
are as follows:
q1
0 Dt x(t) = σ(y(t) − x(t)),
q2
0 Dt y(t) = x(t)(ρ − z(t)) − y(t), (4)
q3
0 Dt z(t) = x(t)y(t) − βz(t),

where q1, q2, q3 ∈ R+ are fractional derivative orders and σ, ρ, β are reals.
As shown in [4], the FO Lorenz system exhibits chaos with the parameters
(σ,ρ,β)= (10, 28, 8/3), where the minimal commensurate order q > 0.9941
provided q1 = q2 = q3 = q. Here q = 0.995 is considered.

3.2. Fractional-order Chen System

The fractional-order Chen’s system is described as [4].
q1
0 Dt x(t) = a(y(t) − x(t)),
q2
0 Dt y(t) = (c − a)x(t) − x(t)z(t) + cy(t), (5)
q3
0 Dt z(t) = x(t)y(t) − bz(t),

where q1, q2, q3 ∈ R+ are fractional derivative orders and (a, b, c) are reals.
This system exhibits chaos with the parameters (a, b, c) = (35, 3, 28), where
the minimal commensurate order q > 0.8244 provided q1 = q2 = q3 = q.
This paper considers q = 0.9.

3.3. Fractional Order Lü System

The Lü system is a bridge between Lorenz system and Chen system [53].
The fractional-order Lü system is described as [4].

q1
0 Dt x(t) = a(y(t) − x(t)),
q2
0 Dt y(t) = −x(t)z(t) + cy(t), (6)
q3
0 Dt z(t) = x(t)y(t) − bz(t),

6
where q1, q2, q3 ∈ R+ are fractional derivative orders and (a, b, c) are reals.
With parameter values as (a, b, c) = (36, 3, 20), the Lü system is found to
show chaotic behaviour. The minimal commensurate order q > 0.9156 is
required for chaos with q1 = q2 = q3 = q. Here q = 0.95 is considered.

3.4. Fractional-order Arneodo System

The Arneodo system has rich dynamical behaviour [54] and exhibits os-
cillatory behavior for the integer-order differential equation of at least two.
The fractional-order Arneodo system is described as:
q1
0 Dt x(t) = y(t),
q2
0 Dt y(t) = z(t), (7)
q3
0 Dt z(t) = −β1 x(t) − β2 y(t) − β3 z(t) + β4 x3 (t),

where q1, q2, q3 ∈ R+ are fractional derivative orders and β1 , β2 , β3 and β4

are reals. As shown in [4], the FO Arneodo system exhibits chaos with the
parameters β1 = −5.5, β2 = 3.5, β3 = 0.8, β4 = −1.0 and the commensurate
fractional order of the equations q > 0.86 with q1 = q2 = q3 = q. Here
q = 0.9 is considered.

3.5. Fractional-Order Lorenz Hyperchaotic system

The Hyperchaotic Lorenz system is generated by adding a non-linear
controller to the Lorenz system [55]. The resulting four-dimensional hyper-
chaotic system provides great efficiency in secure communication applica-
tions. Fractional-order Lorenz hyperchaotic system has been discussed in
[56].
q1
0 Dt x(t) = −σ(y(t) − x(t)) + w(t),
q2
0 Dt y(t) = x(t)(ρ − z(t)) − y(t),
q3
0 Dt z(t) = x(t)y(t) − βz(t), (8)
q4
0 Dt w(t) = −y(t)z(t) + rw(t),

where again q1, q2, q3, q4 ∈ R+ are fractional derivative orders and σ, ρ, β,
r are reals. As shown in [57], the FO Lorenz system exhibits chaos with the
parameters (σ, ρ, β, r)= (10, 28, 8/3, −1), where q1 = q2 = q3 = q4 = q =
0.98 is considered.

7
3.6. Discrete approximation of FO chaotic system: Continued fraction ex-
pansion
For digital implementation of these chaotic systems, it is necessary to
convert the FO differential operator to discrete domain thereby converting
the continuous-time differential equations to difference equations. In the
proposed work, discrete approximation of FO differential operator is obtained
using CFE Tustin method [58]. This approximation leads to approximations
in rational form and often converges much more rapidly than PSE [59]. It has
a wider domain of convergence in the complex plane and requires a smaller
set of coefficients to achieve a good approximation.
The generating function to discretize the fractional-order differentiator sr
(r is real number) is given by (9). The expansion of this function determines
both the approximation and its coefficients.

s = ω(z −1 ). (9)

Using backward difference rule and performing power series expansion gives
the discretization formula as mentioned in (10).
±r
−1 ±r 2 ∗ (1 − z −1 )
(ω(z )) = , (10)
2 ∗ (1 + z −1 )
where r ∈ R and 0 < r < 1. This approximation has been popular in
simulating and digital implementation of FO systems and controllers [60].

4. FPGA Implementation
As compared with other processors, FPGAs use dedicated hardware for
processing logic and hence their performance is not constrained by the com-
plexities of additional overhead, such as operating system, etc. The latest
versions of FPGAs emphasize on low dynamic power performance and hence
are increasingly used for signal processing applications [61]. The processor
based system has layers of abstraction to schedule tasks and share resources
among multiple resources. These complexities are not necessary for FPGA
based system [1].
Five FO chaotic systems are designed using hardware description lan-
guage (HDL) Coder in MATLAB/Simulink environment. VHDL code is
generated by using the HDL Code generator. After debugging, the generated
VHDL code is simulated in ModelSim simulator, which are then benchmarked

8
with MATLAB results. Later the synthesized VHDL code is transferred to
FPGA. The time evolution of variables and phase plots are displayed on DSO
using Coder-Decoder (CODEC) available on FPGA. The Reset and Clock
signals on the inlet of the units have been used to ensure the timing of sub-
modules within the units and the synchronization between modules and the
systems. The initial conditions required for the chaotic systems are embed-
ded in the code itself. The output state variables are x(t), y(t), z(t) and
w(t) are of 32 bits in word length with fixed point data-type and fractional
word length of 16 bits. The laboratory setup for implementation on FPGA
is shown in Fig. 1. The implementation was carried out on DE2-115 board

Figure 1: Laboratory hardware setup for implementation of Fractional-order Chaotic Sys-

tem on FPGA.

shown in Fig. 2 from Altera that utilizes a Cyclone IV (EP4CE115F29C7N)

FPGA chip [62]. Following are the details of each module:

9
4.1. Device details
• Cyclone IV devices are ideal for low-cost, small-form-factor applications
in the wireless, broadcast, industrial, consumer, and communications
industries.
• Cyclone IV E offers the lowest power and high functionality with the
lowest cost.
• Cyclone IV EP4CE115F29C7N device has 114,480 logic elements, 300
9*9 bit Multipliers, 266 18*18 bit Multipliers, 3888K Embedded Mem-
ory, 4 general-purpose PLLs, 20 Global Clock Networks, 8 User I/O
Banks, and 528 Maximum user I/O [62].

Figure 2: Altera DE2-115 Cyclone IV EP4CE115F29C7N device [62].

4.2. FPGA clocks

The most important component on the FPGA board is the crystal oscil-
lator for the clock circuitry [62]. The DE2-115 has on board oscillator that
produces 50 MHz clock signal. The FPGA board also provides the feature
of connecting an external clock source to the board. Also the clock can be
used as source clock for the PLL circuit.

10
4.3. Audio Codec Interfacing
The DE2 board is equipped with a Wolfson WM8731 [12] audio coder/
decoder (CODEC) which has on-board ADC and DAC. It supports line-in,
microphone-in and line-out ports with sample rate adjustable from 8 KHz
to 96 KHz. It works on I2C bus interface connected to pins on the Cyclone
IV FPGA. The device is controlled via 2 or 3 wire interface. The interface
provides access to all features, including volume control, mutes, de-emphasis
and power management facilities. The primary function role of ADC and
DAC controller module is to place the data into and read data from the A/D
and D/A registers respectively.

5. MATLAB HDL Coder

The HDL Coder is a toolbox available in MATLAB which is used to gen-
erate Verilog and VHDL codes ready for synthesizing in ASIC and FPGA
platforms [63]. It generates VHDL and Verilog code which is target indepen-
dent and can be used to program FPGA. It works with embedded MATLAB
functions, Simulink Models and State-flow charts which is converted into
HDL and Verilog codes. In order to work with HDL Coder in Simulink, the
Simulink blocks which are compatible with HDL Coder are used. The HDL
Coder supports over 200 Simulink blocks, including State-flow charts. With
the help of HDL coder compatible blocks, one can design signal processing,
control and communication logic as Simulink model file, by dragging and
dropping various blocks into the design. Along with these advantages it also
provides the freedom to select the data-type of variable (floating point or
fixed point) with appropriate word length. Functions written in mcode can
also be included in the design. For verification of results via simulation dif-
ferent MATLAB tools could be used, including scopes, displays, etc. [63].
The design procedure with HDL Coder is shown in Fig. 3. The salient steps
involved in the implementation process are as follows:

Step 1. : The fractional-order chaotic system is modeled in Simulink using

HDL Coder toolbox [63].

Step 2. : The modeled fractional-order chaotic system is simulated and MAT-

LAB plots of state variables are obtained.

Step 3. : VHDL code is generated using HDL coder.

11
 Figure 3: Steps involved in implementation on FPGA.

Step 4. : The generated VHDL code is synthesized in Quartus.

Step 5. : The synthesized code is simulated in ModelSim and ModelSim plots

are obtained.

Step 6. : The .sof file is generated in Quartus software which is transferred

to FPGA.

Step 7. : The phase plot of fractional-order chaotic systems are observed on

DSO.
The state variables are represented by 32 bit fixed point representation
and scaled variables are represented by 16 bit representation to match with
voltage range of CODEC. A separate .vhd program is required to provide
the appropriate clock for fractional-order chaotic system.

12
6. Implementation of Chaotic Systems
This section elaborates the process of FPGA implementation of the FO
chaotic systems.

6.1. Fractional-order Lorenz System

The system given by (4) in section 3.1 is now implemented using FPGA.
The CFE Tustin approximation given in (10) in section 3.6 is used. The
discretized FO Lorenz system is:

Nx (z −1 )
x(k) = σ(y(k − 1) − x(k − 1)),
Dx (z −1 )
Ny (z −1 )
y(k) = x(k)(ρ − z(k − 1)) − y(k − 1), (11)
Dy (z −1 )
Nz (z −1 )
z(k) = x(k)y(k) − βz(k − 1),
Dz (z −1 )

where Nx , Dx , Ny , Dy , Nz , and Dz are discrete polynomials obtained using

the approximation. The Simulink model for Lorenz system is shown in Fig.
4. The time plots of state variables and phase plots obtained using Simulink
are shown in Fig. 5-7.

6.1.1. ModelSim Simulation

Using the HDL code generator, corresponding VHDL code is obtained
for Simulink model. The generated VHDL code is synthesized in Quartus
software. After generation of code from HDL coder, the generated code is
simulated in Modelsim Simulator, the results of same are as shown in Fig.
8. The variables xNew, yNew and zNew are 32-bit output variables. These
variables are further scaled to 16 bit to match with CODEC range of the
FPGA board. The signal form remains unaltered. It is also verified that
the values obtain from ModelSim for state variables exactly match with that
obtained using MATLAB [64] (see Fig.9). Similar procedure is followed for
other chaotic systems.

6.1.2. Implementation Analysis

After generation of VHDL code from HDL Coder and after performing
the functional simulation of same it is synthesized in Quartus to generate
(.sof) file which is transferred to FPGA. The built-in CODEC of FPGA

13
 Figure 4: Simulink Model of Lorenz System.
50 50

45 45

40 40

35 35

30 30
z(t)

z(t)

25 25

20 20

15 15

10 10

5 5

0 0
−30 −20 −10 0 10 20 30 −20 −15 −10 −5 0 5 10 15 20
y(t) x(t)

Figure 5: Phase plot of Figure 6: Phase plot of

Lorenz system obtained Lorenz system obtained
from MATLAB: x(t) ver- from MATLAB: y(t) ver-
sus y(t). sus z(t).

14
 30

20

10
y(t)

−10

−20

−30
−20 −15 −10 −5 0 5 10 15 20
x(t)

Figure 7: Phase plot of Lorenz system obtained from MATLAB: x(t) versus z(t).

Figure 8: ModelSim waveform of Lorenz System.

produces the analog output and is available on DSO. The implementation

results for FO Lorenz System are shown in Fig.10-12 and Fig.13-15. The
implementation of other FO chaotic systems is also carried out using these
steps.

6.2. Fractional-Order Chen System

The FO Chen system (5) in section 3.2 is implemented using FPGA. The
discrete version of the system obtained using CFE Tustin approximation and

15
 MATLAB
ModelSim
20
x(t)
0

−20
0 200 400 600 800 1000 1200 1400 1600 1800 2000
time
50
y(t)

−50
0 200 400 600 800 1000 1200 1400 1600 1800 2000
time
60

40
z(t)

20

0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
time

Figure 9: MATLAB and ModelSim data plot of Lorenz system : x(t), y(t) and z(t).

Figure 10: Real time results of the implemented Lorenz generator: chaotic signal x(t) .

used for implementation is:

Nx (z −1 )
x(k) = a(y(k − 1) − x(k − 1)),
Dx (z −1 )
Ny (z −1 )
y(k) = dx(k) − x(k)z(k − 1) + cy(k − 1), (12)
Dy (z −1 )
Nz (z −1 )
z(k) = x(k)y(k) − bz(k − 1),
Dz (z −1 )

16
 Figure 11: Real time results of the implemented Lorenz generator: chaotic signal y(t).

Figure 12: Real time results of the implemented Lorenz generator: chaotic signal z(t).

with Nx , Dx , Ny , Dy , Nz , and Dz being the discrete polynomials. Fig.16

depicts the simulation results. It is seen that ModelSim and Simulink plots
coincide. Next, the implementation results for FO Chen System are shown
in Fig.17-19.

17
Figure 13: Real time Figure 14: Real time
results of the imple- results of the imple-
mented Lorenz genera- mented Lorenz genera-
tor: chaotic signal : x(t) tor: chaotic signal : y(t)
versus y(t). versus z(t).

6.3. Fractional Order Lü System

The implementation of FO Lü system (6) given in section 3.3 is now
discussed.
Nx (z −1 )
x(k) = a(y(k − 1) − x(k − 1)),
Dx (z −1 )
Ny (z −1 )
y(k) = −x(k)z(k − 1) + cy(k − 1), (13)
Dy (z −1 )
Nz (z −1 )
z(k) = x(k)y(k) − bz(k − 1),
Dz (z −1 )

The simulation results generated using Simulink and ModelSim are shown
in Fig. 20. The overlap of these waveforms is clearly seen. Next, the system
is implemented on the FPGA. The results are shown in Fig. 21-23.

18
Figure 15: Real time results of the implemented Lorenz generator: chaotic signal: x(t)
versus z(t).

6.4. Fractional Order Arneodo System

Next the simulation and FPGA implementation of The FO Arneodo sys-
tem (7) described in section 3.4 is presented.

Nx (z −1 )
x(k) = y(k − 1),
Dx (z −1 )
Ny (z −1 )
y(k) = z(k − 1), (14)
Dy (z −1 )
Nz (z −1 )
z(k) = −β1 x(k) − β2 y(k) − β3 z(k) + β4 x3 (k).
Dz (z −1 )

The simulation results generated using Simulink and ModelSim are shown
in Fig. 24. The overlap of these waveforms is clearly seen. Next, the system
is implemented on the FPGA. The results are presented in Fig. 25-27.

19
 MATLAB
ModelSim
40

20
x(t)
0

−20
0 200 400 600 800 1000 1200 1400 1600 1800 2000
time
50
y(t)

−50
0 200 400 600 800 1000 1200 1400 1600 1800 2000
time
60

40
z(t)

20

0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
time

Figure 16: MATLAB and ModelSim data plot of Chen system :x(t), y(t) and z(t).

Figure 17: Real time re- Figure 18: Real time re-
sults of the implemented sults of the implemented
Chen generator: chaotic Chen generator: chaotic
signal x(t) versus y(t). signal y(t) versus z(t).

20
Figure 19: Real time results of the implemented Chen generator: chaotic signal x(t) versus
z(t).

6.5. Fractional-order Hyperchaotic Lorenz System

The FO Hyperchaotic Lorenz system (8) in section 3.5 is now implemented
using FPGA. Its discrete version is as follows:

Nx (z −1 )
x(k) = −σ(y(k − 1) − x(k − 1)) + w(k − 1),
Dx (z −1 )
Ny (z −1 )
y(k) = x(k)(ρ − z(k − 1)) − y(k − 1), (15)
Dy (z −1 )
Nz (z −1 )
z(k) = x(k)y(k) − βz(k − 1),
Dz (z −1 )
Nw (z −1 )
w(k) = −y(k)z(k) + rw(k − 1).
Dw (z −1 )

The FPGA implementation results are presented in Fig. 28-33.

21
 MATLAB
ModelSim
40

20
x(t)

−20
0 200 400 600 800 1000 1200 1400 1600 1800 2000
time
40

20
y(t)

−20
0 200 400 600 800 1000 1200 1400 1600 1800 2000
time
60

40
z(t)

20

0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
time

Figure 20: MATLAB and ModelSim data plot of Lü system : x(t), y(t) and z(t).

Figure 21: Real time re- Figure 22: Real time re-
sults of the implemented sults of the implemented
Lü generator: chaotic Lü generator: chaotic
signal x(t) versus y(t). signal y(t) versus z(t).

22
Figure 23: Real time results of the implemented Lü generator: chaotic signal x(t) versus
z(t).

MATLAB
ModelSim
0.5
x(t)

−0.5
0 200 400 600 800 1000 1200 1400 1600 1800 2000
time
2

1
y(t)

−1
0 200 400 600 800 1000 1200 1400 1600 1800 2000
time
50
z(t)

−50
0 200 400 600 800 1000 1200 1400 1600 1800 2000
time

Figure 24: MATLAB and ModelSim data plot of Arneodo system :x(t), y(t) and z(t).

23
Figure 25: Real time Figure 26: Real time
results of the imple- results of the imple-
mented Arneodo genera- mented Arneodo genera-
tor: chaotic signal x(t) tor: chaotic signal y(t)
versus y(t). versus z(t).

Figure 27: Real time results of the implemented Arneodo generator: chaotic signal x(t)
versus z(t).

24
Figure 28: Real time Figure 29: Real time
results of the imple- results of the imple-
mented Hyperchaotic mented Hyperchaotic
Lorenz System genera- Lorenz System genera-
tor: chaotic signal x(t) tor: chaotic signal x(t)
versus y(t). versus z(t).

Figure 30: Real time results of the implemented Hyperchaotic Lorenz System generator:
chaotic signal x(t) versus w(t).

25
Figure 31: Real time Figure 32: Real time
results of the imple- results of the imple-
mented Hyperchaotic mented Hyperchaotic
Lorenz System genera- Lorenz System genera-
tor: chaotic signal y(t) tor: chaotic signal y(t)
versus z(t). versus w(t).

Figure 33: Real time results of the implemented Hyperchaotic Lorenz System generator:
chaotic signal z(t) versus w(t).

26
7. Analysis of synthesis results and implementation performance
The synthesis results obtained for each FO chaotic generator from Quar-
tus are specified in terms of logic resources required and registers used. Along
with these, the usage of total DSP blocks, multipliers and PLL used are also
listed. The description of each term is as follows.
1. Logic elements are the smallest units in the device. These are consist
of a four-input look-up table (LUT) which can implement any function
of four variables, a programmable register, a carry chain connection,
register feedback support and have ability to drive local, row, column,
direct link interconnects. Total Logic Elements present on Cyclone IV
E device are 114,480.
2. Logic utilization reports the percentage calculated from the number of
half-adaptive logic modules (half-ALMs) available in the device and the
number of half-ALMs used in the design.
3. Dedicated logic register refers to the registers present in ALM, total
register present on Cyclone IV E device is 3528.
4. Total pins represent the total number of pins used against the total
number of pins available. The total pins available on the device is 529.
The Table 1 shows the hardware resources utilized on FPGA in terms of
total logic elements, total phase-locked loops (PLLs), total combinational
functions, dedicated logic register and embedded multiplier along with max-
imum frequency. It can be concluded that the implementation of FO chaotic
system on FPGA utilizes only small percentage of total resources available
with great accuracy and speed. The Table 2 shows the core static power
dissipation, also known as the Quiescent power.
To further confirm the chaotic behaviour of the implemented systems, the
Lyapunov exponents for each system were calculated from the time series
data. Lyapunov exponent is a measure of presence of chaos in a system. As
mentioned in [65, 26] a system is chaotic if the largest Lyapunov exponent is
positive. These exponents are given in Table 3. It is seen that all are positive
implying a chaotic behaviour.

8. Conclusion
FPGA implementation of fractional-order chaotic systems is the focus of
this paper. A systematic approach to discretize, simulate and implement

27
 Table 1: Synthesis results and Implementation performance.
FO Chaotic Systems
Resource Lorenz Chen Lu Arneodo Hyperchaotic
Lorenz
Total logic
4 5 5 5 4
elements (%)
Total combinational
4 5 4 5 4
functions (%)
Total pins (%) 9 9 9 9 40
Total logic
1 1 1 1 1
registers (%)
Embedded multiplier
52 60 53 57 42
9-bit elements (%)

Table 2: Static Power Analysis and Frequency.

Fractional-order Core Static Thermal Thermal Power
Frequency
Chaotic Systems Power Dissipation Dissipation
Lorenz 98.89 mW 51.37 mW 19.4 MHz
Chen 98.95 mW 51.67 mW 18.63 MHz
Lu 98.92 mW 51.37 mW 19.74 MHz
Arneodo 98.93 mW 52.86 mW 17.2 MHz
Hyperchaotic 98.87 mW 60.47 mW 23.57 MHz

Table 3: Lyapunov Exponents.

Fractional-order Lyapunov
Chaotic Systems Exponents
Lorenz 1.4639
Chen 0.3880
Lu 0.0828
Arneodo 0.2614
Hyperchaotic 0.0350

28
five FO chaotic systems has been presented. The systems are discretized
using the CFE Tustin approximation and the benchmarking of simulation
results for Simulink and ModelSim are given. The HDL coder platform of
MATLAB is used to implement the systems. The results clearly demonstrate
the successful implementation of these systems on FPGA. The chaotic nature
of each implemented system is further confirmed by the positive values of
the Lyapunov exponents. A detailed analysis of the hardware utilization,
static power and synthesis frequency estimation of each system implemented
on FPGA is also presented. It is shown that the implementation of FO
chaotic systems on FPGA is efficient in terms of power, speed and hardware
resources.

References
[1] B. Muthuswamy, S. Banerjee, A Route to Chaos Using FPGAs, Vol. 1
of Emergence in Complexity and Computation, Springer, Switzerland,
2015.

[2] K. Alligood, T. Sauer, J. Yorke, Chaos: An Introduction to Dynamical

Systems, Textbooks in Mathematical Sciences, Springer New York, 2006.

[3] S. Strogatz, Nonlinear Dynamics and Chaos: With Applications to

Physics, Biology, Chemistry, and Engineering, Advanced book program,
Avalon Publishing, 1994.

[4] I. Petras, Fractional-Order Nonlinear Systems: Modeling, Analysis and

Simulation, Nonlinear Physical Science, Springer Science and Business
Media, 2011.

[5] D. Baleanu, K. Diethelm, E. Scalas, J. J. Trujillo, Fractional Calcu-

lus: Models and Numerical Methods, Vol. 5 of Series on Complexity,
Nonlinearity and Chaos, World Scientific, 2016.

[6] C. Goodrich, A. C. Peterson, Discrete Fractional Calculus, Springer,

2016.

[7] Z. W. Trzaska, Matlab Solutions of Chaotic Fractional Order Circuits,

Engineering Education and Research Using MATLAB, October 2011.

29
 [8] Y. Kang, K.-T. Lin, J.-H. Chen, L.-J. Sheu, H.-K. Chen, Parametric
analysis of a fractional-order newton-leipnik system, Journal of Physics:
Conference Series 96 (1) (2008) 1–6.
[9] M. S. Tavazoei, M. Haeri, A necessary condition for double scroll at-
tractor existence in fractional-order systems, Physics Letters A 367 (12)
(2007) 102 – 113.
[10] I. Petras, A note on the fractional-order chua system, Chaos, Solitons
and Fractals 38 (1) (2008) 140 – 147.
[11] I. Petras, A note on the fractional-order volta system, Communications
in Nonlinear Science and Numerical Simulation 15 (2) (2010) 384 – 393.
[12] Zheng-Ming, A.-R. Zhang, Anticontrol of chaos of the fractional order
modified van der pol systems, Applied Mathematics and Computation
187 (2) (2007) 1161 – 1172.
[13] M. S. Tavazoei, M. Haeri, Chaos generation via a switching fractional
multi-model system, Nonlinear Analysis: Real World Applications 11 (1)
(2010) 332 – 340.
[14] Z.-M. Ge, C.-Y. Ou, Chaos in a fractional order modified duffing system,
Chaos, Solitons and Fractals 34 (2) (2007) 262 – 291.
[15] W. Zhang, S. Zhou, H. Li, H. Zhu, Chaos in a fractional-order rossler
system, Chaos, Solitons & Fractals 42 (3) (2009) 1684 – 1691.
[16] L.-J. Sheua, H.-K. Chenb, J.-H. Chena, Chaos in the newtonleipnik
system with fractional order, Chaos, Solitons & Fractals 36 (1) (2008)
98 – 103.
[17] V. Daftardar-Gejji, S. Bhalekar, Chaos in fractional ordered liu system,
Computers & Mathematics with Applications 59 (3) (2010) 1117 – 1127.
[18] X. N. Ahmed A. Abd El-Latif, A hybrid chaotic system and cyclic elliptic
curve for image encryption, International Journal of Electronics and
Communications 67 (10) (July 2012) 136–143.
[19] N. Taneja, B. Raman, I. Gupta, Selective image encryption in fractional
wavelet domain, International Journal of Electronics and Communica-
tions 65 (10) (April 2010) 338–344.

30
[20] V.-T. Pham, S. T. Kingni, C. Volos, S. Jafari, T. Kapitaniak, A simple
three dimensional fractional-order chaotic system without equilibrium:
Dynamics, circuitry implementation, chaos control and synchronization,
International Journal of Electronics and Communications (2017).

[21] T. Banerjee, B. Karmakar, B. C. Sarkar, Chaotic electronic oscillator

from single amplifier biquad, International Journal of Electronics and
Communications 66 (7) (2012) 593 – 597.

[22] K. M. Cuomo, A. V. Oppenheim, Circuit implementation of synchro-

nized chaos with applications to communications, Phys. Rev. Lett. 71
(1993) 65–68.

[23] M. S. Azzaz, C. Tanougast, S. Sadoudi, R. Fellah, A. Dandache, A new

auto-switched chaotic system and its FPGA implementation, Commu-
nications in Nonlinear Science and Numerical Simulation 18 (7) (2013)
1792–1804.

[24] T. U. Press, K. Sun, Chaotic Secure Communication: Principles and

Technologies, Walter de Gruyter GmbH and Co KG, 2016.

[25] H. Kamata, T. Endo, Y. Ishida, Secure communication system using

chaos via DSP implementation, IEEE International Symposium on Cir-
cuits and Systems. Circuits and Systems Connecting the World. ISCAS
96 3 (1996) 112–115.

[26] S. He, K. Sun, H. Wang, Complexity analysis and DSP implementa-

tion of the fractional-order lorenz hyperchaotic system, Entropy 17 (12)
(2015) 8299–8311.

[27] S. Sadoudi, M. S. Azzaz, M. Djeddou, M. Benssalah, An FPGA real-

time implementation of the chen’s chaotic system for securing chaotic
communications, International Journal of Nonlinear Science 7 (4) (2009)
467–474.

[28] S. Sadoudi, M. S. Azzaz, Hardware implementation of the Rossler

Chaotic System for securing chaotic communication, in: Fifth Inter-
national Conference: Science of Electronic, Technologies of Information
and Telecommunications, 2009.

31
[29] K. Ismail, O. A. Turan, P. Ihsan, Implementation of FPGA-based real
time novel chaotic oscillator, Nonlinear Dynamics 77 (1) (2014) 49–59.

[30] C. Tanougast, A. Dandache, Hardware Design of Embedded Systems for

Security Applications, InTech, Croatia, 2012, Ch. 12, pp. 233–260.

[31] L. D. Micco, H. A. Larrondo, FPGA implementation of a chaotic os-

cillator using rk4 method, VII Southern Conference on Programmable
Logic (SPL) (2011) 185–190.

[32] H. Xue, W. bing LI, Implementation of chaos synchronization on FPGA,

Advances in information Sciences and Service Sciences 4 (6) (April 2012)
42–51.

[33] L. Merah, A. Ali-Pacha, N. H. Said, M. Mamat, Design and FPGA

implementation of lorenz chaotic system for information security issues,
Applied Mathematical Sciences 7 (5) (2013) 237–246.

[34] M. Wang, X. Wang, Controlling Liu system with different methods,

Modern Physics Letters B 23 (14) (2009) 1805–1818.

[35] Q. Wang, S. Yu, C. Li, J. L, X. Fang, C. Guyeux, J. M. Bahi, Theoretical

design and FPGA-based implementation of higher-dimensional digital
chaotic systems, IEEE Transactions on Circuits and Systems I: Regular
Papers 63 (3) (2016) 401–412.

[36] K. Rajagopal, A. Karthikeyan, A. K. Srinivasan, FPGA implementation

of novel fractional-order chaotic systems with two equilibriums and no
equilibrium and its adaptive sliding mode synchronization, International
Journal of Bifurcation and Chaos 87 (March 2017) 2281–2304.

[37] R. Rameshbabu, R. karthikeyan, R. balamurali, A. Prasina, FPGA

implementation of adaptive complete synchronization methodology for
novel chaotic systems, Middle- East Journal of Scientific Research 23
(2015) 36–44.

[38] D. Enzeng, L. Zhihan, D. Shengzhi, C. Zengqiang, Topological horseshoe

analysis on a four-wing chaotic attractor and its FPGA implementation,
Nonlinear Dynamics 83 (1) (2016) 623–630.

32
[39] C. Tanougast, Hardware Implementation of Chaos Based Cipher: Design
of Embedded Systems for Security Applications, Springer-Verlag, Berlin
Hedelberg, 2011.
[40] E. Tlelo-Cuautle, V. H. Carbajal-Gomez, P. J. Obeso-Rodelo, J. J.
Rangel-Magdaleno, J. C. Nunez-Perez, FPGA realization of a chaotic
communication system applied to image processing, Nonlinear Dynam-
ics 82 (4) (2015) 1879–1892.
[41] P. Giard, G. Kaddoum, F. Gagnon, C. Thibeault, FPGA implemen-
tation and evaluation of discrete-time chaotic generators circuits, 38th
Annual Conference on IEEE Industrial Electronics Society (2012) 3221–
3224.
[42] K. Rajagopal, L. Guessas, A. Karthikeyan, A. Srinivasan, G. Adam,
Fractional order memristor no equilibrium chaotic system with its adap-
tive sliding mode synchronization and genetically optimized fractional
order PID synchronization, Complexity 2017 (2017) 1–19.
[43] K. Rajagopal, A. Karthikeyan, A. K. Srinivasan, FPGA implementation
of novel fractional-order chaotic systems with two equilibriums and no
equilibrium and its adaptive sliding mode synchronization, Nonlinear
Dynamics 87 (4) (2017) 2281–2304.
[44] A. A. Kilbas, H. M. Srivastava, J. J. Trujillo, Theory and Applications
of Fractional Differential Equations, Elsevier, Netherlands, 2006.
[45] I. Podlubny, Fractional Differential Equations, Academic Press, USA,
1999.
[46] S. G. Samko, A. A. Kilbas, O. I. Marichev, Fractional Integrals and
Derivatives, Gordon and Breach Science Publishers, Netherlands, 1997.
[47] K. S. Miller, B. Ross, An Introduction to the Fractional Calculus and
Fractional Differential Equations, John Wiley & Sons, USA, 1993.
[48] A. Carpenteri, F. Mainardi (Eds.), Fractals and Fractional Calculus in
Continuum Mechanics, Springer-Verlag, USA, 1997.
[49] R. Caponetto, G. Dongola, L. Fortuna, I. Petráš, Fractional Order Sys-
tems: Modeling and Control Applications, World Scientific, Singapore,
2010.

33
[50] S. Das, Functional Fractional Calculus for System Identification and
Controls, Springer, Germany, 2011.

[51] R. L. Magin, Fractional Calculus in Bioengineering, Begell House Pub-

lishers, USA, 2006.

[52] C. A. Monje, Y. Q. Chen, B. M. Vinagre, D. Xue, V. Feliu, Fractional-

order Systems and Control: Fundamentals and Applications, Springer-
Verlag London Limited, UK, 2010.

[53] J. P. Singh, P. P. Singh, B. Roy, Hybrid synchronization of lu and

bhalekar-gejji chaotic systems using nonlinear active control, {IFAC}
Proceedings Volumes 47 (1) (2014) 292 – 296, 3rd International Confer-
ence on Advances in Control and Optimization of Dynamical Systems
(2014).

[54] S. Vaidyanathany, Adaptive backstepping controller and synchronizer

design for arneodo chaotic system with unknown parameters, Interna-
tional Journal of Computer Science and Information Technology (IJC-
SIT) 4 (6) (Dec 2012) 143 – 157.

[55] S. Gang-Quan, C. Hui, Z. Yan-Bin, A new four-dimensional hyper-

chaotic lorenz system and its adaptive control, Chinese Physics B 20 (1)
(2011) 010509.

[56] X.-Y. Wang, J.-M. Song, Synchronization of the fractional order hyper-
chaos lorenz systems with activation feedback control, Communication
in Nonlinear Science Numerical Simulation 14 (10) (January 2009) 3351–
3357.

[57] X.-Y. Wang, M. Wang, A hyperchaos generated from lorenz system,

Physica A 387 (10) (Feb 2008) 3751–3758.

[58] W. Mitkowski, J. Kacprzyk, J. Baranowski, Advances in the Theory and

Applications of Non-integer Order Systems: 5th Conference on Non-
integer Order Calculus and Its Applications, Cracow, Poland, Lecture
Notes in Electrical Engineering, Springer International Publishing, 2013.

[59] L. Dorcak, I. Petras, J. Terpak, M. Zborovjan, Comparison of the meth-

ods for discrete approximation of the fractional-order operator (2003).

34
[60] B. M. V. F. Concepcion A. Monje, YangQuan Chen, Fractional-order
systems and controls: Fundamentals and applications (2010).

[61] R. Woods, J. McAllister, G. Lightbody, Y. Yi, FPGA-based Implemen-

tation of Signal Processing Systems, Wiley, 2017.

[62] Terasic Corporation Online Cyclone Main Boards,

Terasic Altera DE2-115 Board User’s Manual on the System CD (4
2013).
URL http://www.terasic.com.tw/cgi-bin/page/Archive.pl

[63] MATLAB HDL coder.

URL https://www.nutaq.com/matlab-hdl-coder-xilinx-system-generator

[64] Altera Corporation, Altera Corporation Modelsim-Altera Edition (5

2013).
URL http://www.altera.com/products/software/quartus-ii/modelsim/qts-modelsim-

[65] A. Wolf, J. B. Swift, H. L. Swinney, J. A. Vastano, Determining lyapunov

exponents from a time series, Physica 16D 16 (1985) 285–317.

35