OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0
VCC

CE
Lm
Cp
Ep

Ea
Su
Eu
T1
T2
T3
T4
T5
T6

La

Lb
Lo
Ei
U24:A

Li
1
VCC
3
CLR ADR3
2
ADR2
SW5 START ADR1

?
?
?
?
?
?

?
?
?
?
?
?
?
?
?
?
?
?
ADR0

W7
W6
W5
W4
W3
W2
W1
W0
Clear/Start
U24:B D7
CLEAR D6
4
D5
6
CLR D4
5
VCC D3

?
?
?
?
?
?
?
?
D2
7400
ADR3
ADR2
ADR1
ADR0

D1
D7
D6
D5
D4
D3
D2
D1
D0
D0

VCC
U24:C
9
SW1 SW3 VCC
5
6
7
8

8
7
6
5
4
3
2
1

8
10
OFF

ON

Address OPCode / Data

SW4 WEram SW6 LOW
Switch Switches
OFF
ON

Write Single Step

Memory
U24:D
4
3
2
1

9
10
11
12
13
14
15
16

HIGH
12
11
13 U25:A
VCC
HLT
1
Note: The RAM has inverting outputs so this switch 7400
2 12
has also been inverted to enter the correct data.
13
UP = Logic 0 input = Logic 1 Output from RAM
DOWN = Logic 1 input = Logic 0 output from RAM U26:A
(Observe W-Bus indicators for correct value) 1
VCC U26:D
3 U27:A U27:B
SW2 SW8 2 13
VCC Ep 11 1 2 3 4
ENmar ENpc SW7 Manual
12
CLK

Program/Run Manual/Auto
U26:B U27:C
CE
Auto U25:B
ENram 4 5 6
CLK
Note: This extra switch was added to 6 3
Program/Run HLT
isolate the output of the Program Counter 5 4 6
VCC
from the W-bus when entering data, otherwise 5
a logic contention will occur.
U25:B(C) Note: The 555 timer circuit has been substituted with
INIT=LOW a virtual clock source to speed up the simulation.
START=0
COUNT=-1
CLOCK=1

W7 W6 W5 W4 W3 W2 W1 W0

Cp
U1:A U1:B U2:A U2:B
74LS107 74LS107 74LS107 74LS107
3 1 5 8 3 1 5 8
Q J Q J Q J Q J
12 9 12 9
CLK CLK CLK CLK CLK
2 4 6 11 2 4 6 11
Q K Q K Q K Q K
R

R
13

10

13

10

CLR
U3:A U3:B U3:C U3:D
12
2

CLK CLK
La La
1 4 10 13

14
13
12
11

10
15

14
13
12
11

10
15
3

11

7
1
2
9

7
1
2
9
74LS126

U11 U10

D0
D1
D2
D3

CLK

E1
E2

D0
D1
D2
D3

CLK

E1
E2
OE1
OE2

MR

OE1
OE2

MR
ENpc
74LS173 74LS173
Accumulator Accumulator

Q0
Q1
Q2
Q3

Q0
Q1
Q2
Q3
3
4
5
6

3
4
5
6
CLK
Ea Ea
Lm
1

1
15
10

11
12
13
14

3 2 3 2
9
2
1
7

U4
E2
E1

CLK

D3
D2
D1
D0
MR

OE2
OE1

74LS173
4

4
Memory Address Register
Q3
Q2
Q1
Q0

6 5 6 5
6
5
4
3

10
10

8 9
ADR0 8 9
ADR1
ADR2

13
ADR3
13

ENmar
11 12
11 12
15

13
14
10
11
1

6
5
3
2

U13:D U12:D
U5 74LS126
E
A/B

4B
4A
3B
3A
2B
2A
1B
1A

74LS126
74LS157 Accumulator
Accumulator
2-1 Multiplexer Output
Output
4Y

3Y

2Y

1Y
9

4
12

D7 D3
D6 D2
ENram D5 ENram D1
WEram D4 WEram D0
Su Su
13
14
15

12
10

13
14
15

12
10

10

12

13

10

12

13
3
2

6
4

3
2

6
4

U15:D 9 U14:D
U6 U7
WE
ME
A3
A2
A1
A0
D4
D3
D2
D1

WE
ME
A3
A2
A1
A0
D4
D3
D2
D1

74LS86 74LS86
74LS89 74LS89
16 X 4-bit RAM 16 X 4-bit RAM
Q4
Q3
Q2
Q1

Q4
Q3
Q2
Q1
9
7
5

9
7
5

8
11

11

11

11

Su Carry
14
12

15
11

14
12

15
11
5
3

6
2

5
3

6
2

U17 U16
A0
A1
A2
A3

B0
B1
B2
B3

C0

A0
A1
A2
A3

B0
B1
B2
B3

C0

74LS283 74LS283
Full Adder Full Adder
(LSB) (MSB)
C4

C4
S0
S1
S2
S3

S0
S1
S2
S3
4
1

4
1

9
13
10

13
10

CLK CLK
Carry
Li Ei
CLR Li

U19:D U18:D
15
10

11
12
13
14

15
10

11
12
13
14
9
2
1
7

9
2
1
7

12

12

74LS126 74LS126
2

U8 U9
E2
E1

CLK

D3
D2
D1
D0

E2
E1

CLK

D3
D2
D1
D0
MR

OE2
OE1

MR

OE2
OE1

1 4 10 13 1 4 10 13
74LS173 74LS173
Instruction Instruction
3

8
11

11

Register Register
Q3
Q2
Q1
Q0

Q3
Q2
Q1
Q0

(OPCode) (Address) Eu
6
5
4
3

6
5
4
3
I7
I6
I5
I4

CLK CLK
Lb Lb
14
13
12
11

10
15

14
13
12
11

10
15
7
1
2
9

7
1
2
9

U21 U20
D0
D1
D2
D3

CLK

E1
E2

D0
D1
D2
D3

CLK

E1
E2
OE1
OE2

MR

OE1
OE2

MR

74LS173 74LS173
B Register B Register
(LSB) (MSB)
Q0
Q1
Q2
Q3

Q0
Q1
Q2
Q3
3
4
5
6

3
4
5
6

CLK CLK
Lo Lo
CLR CLR
14
13
12
11

10
15

14
13
12
11

10
15
7
1
2
9

7
1
2
9

U23 U22
D0
D1
D2
D3

CLK

E1
E2

D0
D1
D2
D3

CLK

E1
E2
OE1
OE2

MR

OE1
OE2

MR

74LS173 74LS173
Output Register Output Register
Q0
Q1
Q2
Q3

Q0
Q1
Q2
Q3
3
4
5
6

3
4
5
6

VCC
Note: These pull-up resistors are necessary
because the outputs of the 74LS89 (substitute
OP0
OP1
OP2
OP3

OP4
OP5
OP6
OP7

I7 I6 I5 I4 for the 74LS189) are open collector.

U31:A Ring Counter

2 1
CLK

U36:A U36:B U37:A U37:B U38:A U38:B

U31:B 74LS107 74LS107 74LS107 74LS107 74LS107 74LS107
4 3 3 1 5 8 3 1 5 8 3 1 5 8
Q J Q J Q J Q J Q J Q J
12 9 12 9 12 9
CLK CLK CLK CLK CLK CLK
U31:C 2 4 6 11 2 4 6 11 2 4 6 11
Q K Q K Q K Q K Q K Q K
R

6 5
13

10

13

10

13

10

CLR
U31:D
12 13
T6
T5
T4
T3
T2
T1
11

13

U35:E U35:D

Instruction Decoder Control Matrix

10

12

1 U32:A U35:A
2
6 1 2 LDA
4
5 ADD

SUB
9 U32:B U35:B OUT
10
8 3 4
12
10

12

13

10

12

13

10

12

13

10

12

13

10
1

13

U39:D U40:D U41:D U42:D U43:C

1 U33:A U35:C
2
6 5 6
4
5
3

8
11

11

11

11

9 U33:B U35:F
10
10

12
13

13
1
2

4
5

1
2

3
4
5

8 9 8
12
13 U44:A U44:B U45:A U45:B U46:A U46:B

1 U34:A
2
6
HLT
6

6
12

4
5
11

13
1

U47:A U47:B U47:C U47:F U47:E U48:B

U47:D U48:A
2

4
10

12

Cp Ep Lm CE Li Ei La Ea Su Eu Lb Lo