October 27, 2006

Toshiba TH58NVG4D4CTG00
16 Gbit MLC NAND Flash Memory
Structural Analysis

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Toshiba TH58NVG4D4CTG00
16 Gbit MLC NAND Flash Memory
Structural Analysis

Table of Contents

1 Overview
1.1 List of Figures
1.2 List of Tables
1.3 Company Profile
1.4 Introduction
1.5 Device Summary
1.6 Process Summary

2 Device Overview
2.1 Package and Die
2.2 Die Features

3 Package Overview
3.1 Package

4 Process Analysis
4.1 General Device Structure
4.2 Bond Pads
4.3 Dielectrics
4.4 Metallization
4.5 Vias and Contacts
4.6 Transistors and Poly
4.7 High Voltage Transistors
4.8 Isolation
4.9 Wells and Substrate

5 NAND Flash Cell Analysis

5.1 Plan-View Analysis
5.2 Cross-Sectional Analysis (Parallel to Bit Line)
5.3 Cross-Sectional Analysis (Parallel to Word Line)

6 Materials Analysis
6.1 SIMS Analysis
6.2 TEM-EDS Analyses of the Dielectrics
6.3 TEM-EDS Transistors and Poly
6.4 TEM-EDS Metallization

Rev. 1.0 May 17, 2006 SAR-0605-801

Toshiba TH58NVG4D4CTG00
16 Gbit MLC NAND Flash Memory
Structural Analysis

7 Critical Dimensions
7.1 Horizontal Dimensions
7.2 Vertical Dimensions

8 References

Report Evaluation

Rev. 1.0 May 17, 2006 SAR-0605-801

Toshiba TH58NVG4D4CTG00
16 Gbit MLC NAND Flash Memory
Overview 1-1

1 Overview
1.1 List of Figures
2 Device Overview
2.1.1 Top Package View
2.1.2 Bottom Package View
2.1.3 Package X-Ray (Top-View)
2.1.4 TH58NVG4D4CTG00 Die
2.1.5 Die Markings
2.1.6 Annotated Die Photograph
2.2.1 Die Corner 1
2.2.2 Die Corner 2
2.2.3 Die Corner 3
2.2.4 Die Corner 4
2.2.5 Bond Pads
3 Package Overview
3.1.1 Package End
3.1.2 Die Attach 1
3.1.3 Die Attach 2
3.1.4 Ball Bond
4 Process Analysis
4.1.1 General View of TH58NVG4D4CTG00
4.1.2 Die Edge
4.1.3 Outer Seal Structure
4.1.4 Inner Die Seal
4.2.1 Bond Pad
4.2.2 Right Bond Pad Edge
4.3.1 Passivation
4.3.2 IMD 2
4.3.3 TEM IMD 2
4.3.4 IMD 1
4.3.5 TEM IMD 1
4.3.6 PMD
4.4.1 Minimum Pitch Metal 3
4.4.2 TEM Metal 3
4.4.3 TEM Metal 3 Barrier and Adhesion Layers
4.4.4 Minimum Pitch Metal 2
4.4.5 TEM Metal 2
4.4.6 TEM Metal 2 Barrier and Adhesion Layers
4.4.7 Minimum Width Metal 1 in the Periphery
4.4.8 TEM Metal 1
4.4.9 Minimum Pitch Metal 1 in Flash Array
4.5.1 Minimum Pitch Via 2s
4.5.2 Minimum Pitch Peripheral Via 1s and Contacts

Rev. 1.0 May 17, 2006 SAR-0605-801

Toshiba TH58NVG4D4CTG00
16 Gbit MLC NAND Flash Memory
Overview 1-2

4.5.3 Peripheral Contacts (Glass-Etch)

4.5.4 TEM Bit Line Contact
4.5.5 TEM Peripheral Contact
4.5.6 Contacts to Poly
4.5.7 Interpoly Vias
4.5.8 TEM Interpoly Via
4.6.1 Minimum Gate Length NMOS Transistor
4.6.2 Minimum Pitch NMOS Transistors
4.6.3 Minimum Gate Length PMOS Transistor
4.6.4 TEM Flash Cell Transistors
4.6.5 TEM Peripheral Gate Oxide
4.7.1 Peripheral High Voltage Transistor
4.7.2 TEM Thick Gate Oxide
4.7.3 Row Driver Transistor
4.8.1 Poly Over Isolation
4.8.2 TEM STI
4.8.3 Minimum Width STI
4.9.1 SCM Embedded P-Well
4.9.2 SCM Wells
4.9.3 Embedded P-Well
4.9.4 SRP Peripheral P-Well
4.9.5 SRP Peripheral N-Well
4.9.6 Flash Array Embedded P-Well
5 NAND Flash Cell Analysis
5.1.1 Metal 3 Source Supply
5.1.2 Metal 2 Bit Lines
5.1.3 Bit Lines
5.1.4 Metal 1 Source Supply
5.1.5 Source Select Line
5.1.6 Poly 3 Word Lines and Selects
5.1.7 Word Lines at Array Edge
5.1.8 End of Array
5.1.9 Poly 2/Poly 1 Floating Gates
5.1.10 Floating Gates Detail
5.1.11 Active Silicon
5.1.12 Silicon, STI and Contacts Detail
5.2.1 Flash Cell Parallel to Bit Line
5.2.2 Bit Line Contact and Bit Line Select Transistor
5.2.3 Source Contact and Source Select Transistor
5.2.4 TEM Source Select Transistor and Contact
5.2.5 TEM Select Gate Interpoly Via
5.2.6 TEM Select Gate Bottom
5.2.7 TEM Flash Cell Transistors
5.2.8 TEM Floating Gate Bottom
5.2.9 TEM ONO Interpoly Dielectric

Rev. 1.0 May 17, 2006 SAR-0605-801

Toshiba TH58NVG4D4CTG00
16 Gbit MLC NAND Flash Memory
Overview 1-3

5.3.1 Flash Cell (Parallel to Word Line)

5.3.2 P-Well Contact
5.3.3 Bit Line Contacts
5.3.4 TEM Word Line and Floating Gate
5.3.5 Floating Gates
5.3.6 TEM ONO Interpoly Dielectric
6 Materials Analysis
6.1.1 Dielectric Stack
6.1.2 SIMS Profile of the Dielectrics
6.2.1 TEM-EDS Passivation
6.2.2 TEM-EDS IMD 2 and IMD 1
6.2.3 TEM-EDS Pre-Metal Dielectric
6.2.4 TEM-EDS STI
6.3.1 TEM-EDS Hardmask and Sidewall Spacer
6.3.2 TEM-EDS Gate Silicide
6.3.3 TEM-EDS Contact Silicide
6.4.1 TEM-EDS Metal 3 Cap and Body
6.4.2 TEM-EDS Metal 3 Barrier and Adhesion Layers
6.4.3 TEM-EDS Metal 2 Cap and Barrier Layers
6.4.4 TEM-EDS Metal 1

Rev. 1.0 May 17, 2006 SAR-0605-801

Toshiba TH58NVG4D4CTG00
16 Gbit MLC NAND Flash Memory
Overview 1-4

1.2 List of Tables

1 Overview
1.5.1 Device Summary
1.6.1 Process Summary
2 Device Overview
2.1.1 Package, Die and Bond Pad Sizes
4 Process Analysis
4.3.1 Dielectric Thicknesses
4.4.1 Metallization Vertical Dimensions
4.4.2 Metallization Horizontal Dimensions
4.5.1 Via and Contact Dimensions
4.6.1 Peripheral Transistor Horizontal Dimensions
4.6.2 Peripheral Transistor and Polycide Vertical Dimensions
4.9.1 Die Thickness and Well Depths
5 NAND Flash Cell Analysis
5.2.1 Flash Cell Dimensions
7 Critical Dimensions
7.1.1 Package, Die and Bond Pads
7.1.2 Minimum Pitch Metals
7.1.3 Minimum Pitch Contacts and Vias
7.1.4 Peripheral Transistor Horizontal Dimensions
7.1.5 Flash Cell Dimensions
7.2.1 Vertical Dimensions Dielectrics
7.2.2 Vertical Dimensions Metals
7.2.3 Transistor Vertical Dimensions
7.2.4 Die and Wells Vertical Dimensions

Rev. 1.0 May 17, 2006 SAR-0605-801

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