Thin Solid Films 429 (2003) 231–237

Electrical and mechanical properties of low temperature evaporated

silicon dioxideypolyimide dual-layer insulator for plastic-based polymer
transistor
Sung Kyu Park*, Yong Hoon Kim, Jeong In Han, Dae Gyu Moon, Won Keun Kim
Information Display Research Center, Korea Electronics Technology Institute, Pyungtaek, Kyunggi, South Korea

Received 17 October 2002; received in revised form 10 February 2003; accepted 14 February 2003

Abstract

Conjugated polymer thin film transistors have been prepared using silicon dioxide (SiO2 ) and polyimide films as the dual layer
gate dielectric on a plastic substrate. The dielectric layers were evaluated to investigate mechanical properties, surface morphology,
capacitance–voltage and current–voltage characteristics. Spun polyimide and low temperature ion-beam deposited silicon dioxide
layers were used as the gate dielectric, forming a dual layer structure. The organic layer with appropriate Young’s modulus was
found not only to improve the roughness of the SiO2 surface, but also to relieve the mechanical stress of the dielectric, and
accordingly bring about enhanced device performance. The dual layer gate dielectric indicated a good insulating property of
10y5 Aycm2 at 3 MVycm, flat band voltage of 0.5 V, and root-mean-square surface roughness of 0.6;1.2 nm. Based on the
experiments, we built high performance plastic-based P3HT transistor including 0.007 cm2 yVØs in carrier mobility and onyoff
current ratio of approximately 103.
䊚 2003 Elsevier Science B.V. All rights reserved.

Keywords: Insulator; Silicon dioxide; Polyimide; Polymer; Transistor

1. Introduction tering would suffer from high-energy ion damages, as

Recently, organic electron device based on a plastic
substrate has been envisioned as a viable alternative to
more traditional, mainstream electron device with inor-
ganic substrates such as glass and silicon substrates
w1,2x. The performance of organic and silicon semi-
conductor thin film transistor (TFT) on a plastic sub-
strate has continuously improved in line with the request
of polymer electronic components. However, the appli-
cations of the device on a plastic substrate are at an
early stage at present and the performance is much less
than the device on silicon and glass substrates. Most of
all, the low thermal tolerance, poor surface morphology
and non-rigidness of a plastic substrate mainly account
for the poor device performance. SiO2 films deposited
on a plastic substrate by prevalently used plasma-
enhanced chemical vapor deposition (PECVD) or sput-
*Corresponding author. Tel.: q82-31-610-4085; fax: q82-31-610-
4126.
E-mail address: skpark@keti.re.kr (S.K. Park).
well as inherent hydrogen inclusion w3,4x. Moreover,
mechanical distortion causes the compliant substrate to
bend elastically showing considerable degradation in the
intrinsic properties and adhesion of the oxide films.
Particularly, when the SiO2 films are adapted to the
dielectric of TFT device, the compositional and mechan-
ical degradation induce considerable problems con-
cerned with electrical performance of the device w5–7x.
In other words, the ion damages and hydrogen inclusion
lead the dielectric to show high leakage current and
highly biased flat band voltage. As well, the mechanical
stress and rough surface of the substrate also cause the
device to indicate poor electrical performance or failure.
In this paper, we suggest an e-gun evaporated SiO2 gate
insulator stacked with organic layer to relieve the stress
and modify the rough surface, as well as for little trouble
from hydrogen atoms and low ion damage. Finally,
based on the experimental results, we fabricated plastic-
based polymer TFT device, and then investigate the
influences of the composite insulator on the device
performance.

0040-6090/03/$ - see front matter 䊚 2003 Elsevier Science B.V. All rights reserved.
doi:10.1016/S0040-6090(03)00407-3
232 S.K. Park et al. / Thin Solid Films 429 (2003) 231–237
Fig. 1. Schematic view of polymer thin film transistor using printed poly (3-hexylthiophene) semiconductor on plastic substrate.
2. Experimental
The poly-3-hexylthiophene (P3HT) TFTs reported
here used a bottom electrode structure fabricated on
plastic substrate as shown in Fig. 1. Preliminary, poly-
carbonate substrate was pre-annealed for the reduction
of polymer shrinkage and successively, SiO2 film with
50 nm thicknesses was sputtered on the substrate surface
as an adhesion layer of metal thin film and also as a
gas barrier layer. As a gate electrode, aluminum (Al)
was deposited on the substrate. The Al metal was
preferred for its high coefficient of thermal expansion
rate (25 ppmyK) and ductile property compatible with
plastic substrate. Polyimide (PI) and SiO2 films, used
as the dual layer gate insulator, were prepared sequen-
tially with thickness of 40 and 210 nm, respectively.
The PI solution (Nissan 5291) developed for low tem-
perature curing applications, was spun and annealed at
150 8C under vacuum atmosphere for 4 h by using a
lower gradient heating and cooling process. The heating
and cooling process used for all the device fabrication
process were developed for minimizing the thermal
expansion problems and reported in detail in our previ-
ous results w8,9x. After a vacuum chamber was evacuated
to a base pressure of approximately 10y6 torr, the SiO2
powders were evaporated on the PI layer by e-gun
source at a pressure of approximately 10y5 torr. The
acceleration voltage of e-gun source was 7 kV and the
emission current was approximately 80 mA. E-gun
evaporation method was preferred for little trouble from
hydrogen atoms and low ion damage. As a reference,
SiO2 films were also prepared using RF magnetron
sputter at 120 8C with SiO2 target. Following the
insulation layer deposition, thermal annealing at 150 8C
was carried out in nitrogen atmosphere. Gold source
and drain electrodes were deposited by lift-off in order
to prevent the electrodes from acid contamination. Final-
ly, the solution processable polymer semiconductor was
deposited using contact printing method under ambient.
HP 4156B semiconductor parameter analyzer and HP
8256 capacitance meter conducted all of the measure-
ments concerned with current–voltage and capacitance–
voltage characteristics. Morphology of gate dielectric
was measured by atomic force microscopy (AFM, Ther-
mo Microscope Instruments). The measurements were
accomplished with a silicon cantilever for contact AFM
(ULCT-AUMT-B; contact mounted ultralever; force
constant of 4 Nym and resonance frequency of 45 kHz),
and the scan rate and area were 1;4 Hz and 3=3 mm,
respectively.
Mechanical evaluations were also performed using
the e-gun evaporated SiO2 films and indium–tin–oxide
(ITO) films on plastic substrates. The film–substrate
couples are placed over a rectangular hole and clamped
by a ring. Pressurized gas is then used to deform the
couple into a cylindrical shape, which is carried out
using a miniature mechanical testing machine. A
straightforward calculation can estimate the radius of
curvature. For quantitative analysis of the mechanical
evaluation, the stress–strain relations are monitored by
measuring the variations of electrical resistance in the
ITO films using a four-point measurement technique as
the function of the mechanical stress (bending
curvature).
3. Results and discussion
3.1. Mechanical characteristics
In this section, the mechanical properties of the SiO2
gate insulator including organic buffer layer are inves-
 S.K. Park et al. / Thin Solid Films 429 (2003) 231–237 233

tigated. We assume the substrate to be isotropic in the

plane of the substrates. If the plastic substrate is thin
and compliant, the film–substrate couple bends into a
cylindrical roll instead of a spherical cap. Hence, we
ignore the coefficient of Poisson’s ratio in the following
analysis. Under a specific tensile or compression force,
the film–substrate couple bends and consequently, the
bending momentum elongates the sheet in the upper
section of the film–substrate couple and compresses the
sheets in the lower section. Between the elongated and
the compressed parts, there is a ‘neutral layer’ at the
position zn where it is free from any stress. The neutral
layer position of zn is derived from the condition that
there is no net elongation force acting on the film–
substrate couple w5,9x.

ts RØsfØtf
z ns Ø (1)
2 EsØts

If a buffer layer is inserted between the thin oxide

film and plastic substrate, the mechanism of stress–
strain relation in triple layers can be analyzed in the
same manner. In the case of the sheet containing buffer
layer, the triple layer structure leads the neutral layer to
be located at a new position w9x.

EsØtsqEbØŽtsqtb. RØsfØtf
z ns q (2)
2ØŽEsqEb. ŽEsqEb.Øts
where s f is the stress of an oxide thin film on a
substrate and R is the bending curvature of film–
substrate couple. ts, tb and t f , mean thickness of substrate,
buffer layer, and oxide thin film. Es, Eb and E f mean
Young’s modulus of substrate, buffer layer and oxide
thin film, respectively. As shown in Eq. (2), inserting a
buffer layer with Young’s modulus of Eb, can change
the position of neutral layer. In the case of EbsEs and
t f <ts, the neutral layer position moves toward metallic
film by tb y4 compared to a film-substrate couple without
buffer layer. In the case of Eb/Es and t f <ts, as the
value of Eb decreases the position of neutral layer shifts
from mid-surface toward thin films. It is supposed to
relieve the stress imposed on the films.
When bending momentum or external force (bending
curvature of 4 cm) was applied to SiO2 films (210 nm-
thickness) without a buffer layer, crack or delaminating
phenomena is occurred in SiO2 films as shown in Fig.
2a, while Fig. 2b indicates the release of the phenomena
by using organic buffer layer (PI, 40 nm-thickness). As
mentioned above, theoretical consideration, the Young’s
modulus of the PI was controlled by diluting with g-
Butyrolactone (solvent) from 4 to 2.5 GPa. For more
quantitative analysis on stress release, Bulge test corre-
lating with stress–strain relations was carried out using
conductive oxide films such as indium–tin–oxide
Fig. 2. Crack or delaminating images of SiO2 film when bending
momentum (bending curvature of 4 cm) was applied; (a) deeper crack
and more crack density of the SiO2 film without polyimide buffer
layer and (b) shallower crack and less crack density of the SiO2 film
with polyimide buffer layer.
(ITO), assuming that resistivity is increased linearly
with increasing of strain which is originated from
bending stress. The changes of the resistivity were
measured in a steady state by standard four-point probe
method after the stressing procedure and compared the
measured values with those of as-deposited films. As
shown in Fig. 3, the results are in excellent agreement
with the above expectations. In other words, the ITO
films with appropriate organic buffer layer show a less
resistivity change corresponding to lower crack density.
We think that the buffer layer plays a role of relieving
the mechanical stress. From these experiments, it is
supposed that the composite gate dielectric allows the
mechanical stress that was generated during device
fabrication to be reduced, leading to high performance
of plastic-based polymer TFT device. Among various
organic materials, PI was selected not only for high
insulating property but also for relatively lower Young’s
modulus and low ion mobility at device operating
temperatures.
4. Dielectric characteristics and device performance
P3HT-based polymer TFTs have been prepared using
a dual layer gate dielectric of PI (40 nm) and e-beam
234 S.K. Park et al. / Thin Solid Films 429 (2003) 231–237
Fig. 3. Dependence of electrical resistivity increment of ITO films on vending curvatures and buffer materials.
evaporated SiO2 films (210 nm). The dielectric layer
was evaluated to determine the best deposition condition
with regard to the dielectric characteristics and the
interface morphology between the dielectric and the
semiconductor. The SiO2 films deposited on a plastic
substrate by prevalently used PECVD or sputtering
would suffer from hydrogen traps and high-energy ion
damage. The inherent hydrogen atoms from silane
(SiH4) gas are not released by the low temperature
deposition and consequently may cause a considerable
amount of the traps associated with Si–H, O–H, Si–
OH bonds w3,4x. We used e-beam evaporated SiO2 films
with a refractive index approximately 1.3;1.5 similar
to the refractive index of thermally grown SiO2 films.
The refractive index was obtained by ellipsometry meas-
urement. The ion-beam deposited SiO2 films on a plastic
substrate, however, are quite rough with a peak-to-valley
roughness of 10;15 nm and a root-mean-square (RMS)
roughness of 3;5 nm. The poor roughness of SiO2
films on a plastic substrate is considered to be respon-
sible for the rough surface of the plastic substrate
including a peak-to-valley roughness of 10;20 nm and
a RMS roughness of 5;8 nm. It is well known that the
morphology of the gate dielectric is one of the influential
factors determining the carrier mobility and insulating
properties in a polymer TFT device w2x. We have found
that using PI films with a dielectric constant of 3.0,
Young’s modulus of 2.5 GPa, solution viscosity of
12"2.5 and thickness of 40 nm as an interlevel dielec-
tric to planarize substrate topographies, the ion-beam
deposited SiO2 films have relatively smooth surfaces
with a peak-to-valley roughness of 5;8 nm and a RMS
roughness of 0.6;1.2 nm. Fig. 4a,b shows AFM 3-D
images of the dielectric layer surfaces and they indicate
that stacked gate insulator composed of polyimide and
SiO2, is much more smooth than only SiO2 gate
insulator.
Fig. 5a,b depicts the insulating properties and the
capacitance vs. voltage characteristics (C–V) of various
gate dielectrics prepared with metal (Al)–insulator–
metal (Al) (MIM) on the plastic substrates and metal
(Al)—oxide-p-type silicon substrate (MOS) capacitor,
respectively. The dielectrics used in the devices are
single layer SiO2 film with 250 nm-thickness and dual
layer PIySiO2 films with 40y210 nm-thickness. It should
be noted that the leakage current and flat band voltage
characteristics are improved by employing e-gun evap-
orated SiO2 films subjected to N2 annealing. We think
the low-energy ion damage of the evaporation process,
and fewer electron traps associated with hydrogen atoms
may enhance the electrical characteristics. Moreover, the
beneficial role of the nitrogen annealing is probably
attributed to the replacement of some Si–O bonds with
stronger Si–N bonds. However, because low temperature
evaporated SiO2 films have essentially lower atomic
bonding energy, during high voltage stressing the atomic
bonds are apt to be broken resulting in traps being
generated inside the oxide layer and at the oxide
interface w10–12x. They induce higher leakage current
and lower breakdown voltage compared with thermally
grown and high temperature generated SiO2 films. As
well, poor asperity of bottom electrode, originating from
intrinsic substrate surface, induces high field emission
point and accordingly may accelerate trap generation
inside the oxide layer and at the metal–oxide interface,
leading to high leakage current. In the device fabrication,
it should be mentioned that the composite dielectric
composed of polyimide layer and SiO2 films leads to
relatively lower leakage current. One possible mecha-
nism on the phenomena is supposed to be due to the
 S.K. Park et al. / Thin Solid Films 429 (2003) 231–237
Fig. 4. Atomic force microscope images of gate insulator surface; (a) only SiO2 gate insulator, and (b) stacked gate insulator composed of
polyimide and SiO2.
diminishment of surface asperities of the SiO2 insulator.
In other words, the high field emission points near
asperities at the PIySiO2 interface will modulate the
local trap generation rate and may lead to the reduction
of sudden leakage flow. However, detailed experiments
about the phenomenon are now working out separately
and we will pronounce the results with enough discus-
sions on the possible mechanisms.
Whereas, as shown in Fig. 5b, the positive shift of
flat band voltage is supposed to be attributed to addi-
tional charges existed in the polyimide–oxide interface.
Sessler et al. w13x, Dumin et al. w14x and Hook et al.
w15x have shown that polyimide exhibits various types
of conduction under various field and temperature and
thus, ionic, electronic, or polarization currents are pres-
ent. As well, Neuhaus et al. have suggested that because
silicon dioxide is essentially impervious to penetration
by moisture or ionic charges, any conduction in the
polyimide produces effective sodium charges at the
SiO2 –polyimide interface. w16,17x As a result, it was
found that the flat band voltage of MOS capacitor with
single layer of SiO2 is y2.5;y1.5 V, while the dual
layer dielectric induces the positive flat band voltage
235
shift. The polyimideySiO2 composite dielectric indicates
an insulating property of below 10y5 Aycm2 at 3 MVy
cm and flat band voltage of 0.5 V as well as a RMS
surface roughness of 0.6;1.2 nm.
Fig. 6a delineates the electrical characteristics of a
printed P3HT TFT constructed on a plastic substrate
with a gate length of 25 mm, a gate width of 500 mm,
a composite gate dielectric thickness of 250 nm, and a
semiconductor thickness of 0.25;0.5 mm. The satura-
tion field effect mobility, threshold voltage and onyoff
current ratio of the device are 0.007 cm2 yVØs, 0.5;2.5
V and approximately 102, respectively. Fig. 6b shows
the output current curves of the device with SiO2 film
as the dielectric. The device shows carrier mobility of
0.00015 cm2 yVØs, threshold voltage of y2.5 V, and ony
off current ratio of 10. The increasingly negative x-
intercepts with increased gate voltage are due to leakage
current through the dielectric, causing lower onyoff
current ratio, and poorer carrier mobility is attributed to
the poor flatness of the SiO2 films. The rough surface
suffers from defects and voids, which are acting as traps
in semiconductoryinsulator interface, and leads to poorly
ordered semiconductor layer on the surface that are now
236 S.K. Park et al. / Thin Solid Films 429 (2003) 231–237

5. Conclusions
Conjugated polymer TFT was fabricated successfully
on a plastic substrate using organic and inorganic films
as a dual layer dielectric. SiO2 films deposited on a
plastic substrate by widely used sputtering would suffer
from high-energy ion damage, leading to high leakage
current and much negative-biased flat band voltage. E-
gun evaporated SiO2 films subjected to N2 annealing
show enhanced insulating and capacitance vs. voltage
characteristics. The low-energy ion damage, few electron
traps associated with hydrogen inclusion, and nitrogen
radicals are proposed to account for the improved
properties. Also, the significant rough surface and very
compliant property of plastic substrate are also respon-
sible for the poor performance of the polymer TFT
devices, such as low field-effect mobility, low onyoff
current ratio, and unstable output current behaviors.
Spun PI films are proposed as an interlevel dielectric
not only for relieving the mechanical stress imposed on
e-gun evaporated SiO2 films but also for plannerizing
the rough surface of the plastic substrate. As a result,
we obtained high performance plastic-based polymer

Fig. 5. (a) Insulating properties of the gate dielectrics deposited on

plastic substrate, and (b) capacitance vs. voltage characteristics of the
dielectrics deposited on p-type silicon substrate.

investigating using wide viewing angle X-ray diffraction

measurements. The poor ordering and defects probably
impede the movement of charge carriers through the
semiconductor layer and the interface region by scatter-
ing and momentum transfer of the carriers to phonons
in the polymer semiconductor w2x. It is considered that
the employment of polyimide layer causes the gate
dielectric to platen and to close the holes of the SiO2
and thus the leakage current drops. The device with the
dual layer dielectric indicates constant x-intercepts
around 0 V regardless of gate voltage, showing relatively
good carrier mobility. As shown in these experiments,
in the case of a plastic substrate with poor surface
morphology as a base back plate of polymer TFT
devices, a polyimide interlevel dielectric improves the
electrical properties of the devices although being a
certain potential for transfer of contaminant ions from
PI to SiO2 films. Reducing PI thickness and adjusting
of annealing temperature lead the devices to show the Fig. 6. Electrical characteristics of contact printed polymer TFTs fab-
minimal flat band voltage shift, which has negligible ricated on plastic substrates including (a) polyimideySiO2 as a gate
effect on the device performance. dielectric, and (b) only SiO2 films as a gate dielectric.
 S.K. Park et al. / Thin Solid Films 429 (2003) 231–237
TFT device including 0.007 cm2 yVØs in carrier mobility
and onyoff current ratio near 103 with a typical transistor
behavior.
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