EE 171 Take Home Chapter Test 4 (d) reverse-biased

Field Effect Transistors 10. A certain JFET datasheet gives VGS(off ) = -4 V.The pinch-off
voltage, VP,
Instructions: Please use the answer sheet to answer. E- (a) cannot be determined
mail a photo or a scanned version of your answer sheet (b) is -4 V
to the given e-mail below.
(c) depends on VGS
(d) is +4 V
Shade the letter of the best answer.
11. The JFET in Question 10
(a) is an n channel
1. The JFET is
(b) is a p channel
(a) a unipolar device
(c) can be either
(b) a voltage-controlled device
12. For a certain JFET, IGSS =10 nA at VGS =10 V. The input
(c) a current-controlled device
resistance is
(d) answers (a) and (c)
(a) 100 M Ω (b) 1MΩ
(e) answers (a) and (b) (c) 1000MΩ (d) 1000M
2. The channel of a JFET is between the 13. For a certain p-channel JFET, VGS(off ) = 8 V. The value of
(a) gate and drain VGS for an approximate midpoint bias is
(b) drain and source (a) 4 V (b) 0 V
(c) gate and source (c) 1.25 V (d) 2.34 V
(d) input and output 14. In a self-biased JFET, the gate is at
3. A JFET always operates with (a) a positive voltage
(a) the gate-to-source pn junction reverse-biased (b) 0 V
(b) the gate-to-source pn junction forward-biased (c) a negative voltage
(c) the drain connected to ground (d) ground
(d) the gate connected to the source 15. The drain-to-source resistance in the ohmic region
4. For VGS = 0 V, the drain current becomes constant when depends on
VDS exceeds (a) VGS
(b) the Q-point values
(a) cutoff
(b) VDD (c) the slope of the curve at the Q-point
(c) VP (d) all of these
(d) 0 V 16. To be used as a variable resistor, a JFET must be
5. The constant-current region of a FET lies between (a) an n-channel device
(a) cutoff and saturation (b) a p-channel device
(b) cutoff and pinch-off (c) biased in the ohmic region
(c) 0 and IDSS (d) biased in saturation
(d) pinch-off and breakdown 17. When a JFET is biased at the origin, the ac channel
6. IDSS is resistance is determined by
(a) the drain current with the source shorted (a) the Q-point values (b) VGS
(b) the drain current at cutoff (c) the transconductance (d) answers (b) and (c)
(c) the maximum possible drain current 18. A MOSFET differs from a JFET mainly because
(d) the midpoint drain current (a) of the power rating
SELF-TEST ◆ 439
(b) the MOSFET has two gates
7. Drain current in the constant-current region increases
(c) the JFET has a pn junction
when
(d) MOSFETs do not have a physical channel
(a) the gate-to-source bias voltage decreases
19. A D-MOSFET operates in
(b) the gate-to-source bias voltage increases
(a) the depletion mode only
(c) the drain-to-source voltage increases
(b) the enhancement mode only
(d) the drain-to-source voltage decreases
(c) the ohmic region only
8. In a certain FET circuit, VGS = 0 V, VDD = 15 V, IDSS = 15 mA,
(d) both the depletion and enhancement modes
and RD = 470 Ω. If RD is decreased to
20. An n-channel D-MOSFET with a positive VGS is operating
(a) 19.5 mA (b) 10.5 mA
in
(c) 15 mA (d) 1 mA
(a) the depletion mode
9. At cutoff, the JFET channel is
(b) the enhancement mode
(a) at its widest point
(c) cutoff
(b) completely closed by the depletion region
(d) saturation
(c) extremely narrow

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21. A certain p-channel E-MOSFET has a VGS(th) = -2 V. If VGS = 33. A certain common-drain (CD) amplifier with RS = 1.0 kΩ
0 V, the drain current is has a transconductance of 6000 mS. The voltage gain is
(a) 0 A (b) ID(on) (a) 1 (b) 0.86 (c) 0.98 (d) 6
(c) maximum (d) IDSS 34. The datasheet for the transistor used in a CD amplifier
22. In an E-MOSFET, there is no drain current until VGS specifies IGSS = 5 nA at VGS = 10 V. If the resistor from gate
(a) reaches VGS(th) (b) is positive to ground, RG, is 50 MΩ, the total input resistance is
(c) is negative (d) equals 0 V approximately
23. All MOS devices are subject to damage from (a) 50 MΩ (b) ) 200 MΩ (c) ) 40 MΩ (d) ) 20.5 MΩ
(a) excessive heat 35. The common-gate (CG) amplifier differs from both the CS
(b) electrostatic discharge and CD configurations in that it has a
(c) excessive voltage (a) much higher voltage gain (b) much lower voltage gain
(d) all of these (c) much higher input resistance (d) much lower input
24. A certain D-MOSFET is biased at VGS = 0 V. Its datasheet resistance
specifies IDSS = 20 mA and VGS(off) = -5 V. The value of the 36. If you are looking for both good voltage gain and high
drain current input resistance, you must use a
(a) is 0 A (a) CS amplifier (b) CD amplifier (c) CG amplifier
(b) cannot be determined 37. A cascode amplifier consists of
(c) is 20 mA (a) a CD and a CS amplifier (b) a CS and a CG amplifier
25. In a common-source amplifier, the output voltage is (c) a CG and a CD amplifier (d) two CG amplifiers
(a) 180°out of phase with the input 38. The class D amplifier is similar to
(b) in phase with the input (a) class C (b) class B (c) class A (d) none of these
(c) taken at the source 39. The class D amplifier uses
(d) taken at the drain (a) frequency modulation (b) amplitude modulation
(e ) answers (a) and (d) (c) pulse-width modulation (d) duty cycle modulation
26. In a certain common-source (CS) amplifier, Vds = 3.2 V rms 40. E-MOSFETs are generally used for switching applications
and Vgs = 280 mV rms. The voltage gain is because of their
(a) 1 (b) 11.4 (c) 8.75 (d) 3.2 (a) threshold characteristic (b) high input resistance
27. In a certain CS amplifier, RD = 1.0 kΩ, RS = 560 Ω, VDD = 10 (c) linearity (d) high gain
V, and gm = 4500 μS. If the source resistor is completely 41. A sampling circuit must sample a signal at a minimum of
bypassed, the voltage gain is (a) one time per cycle (b) the signal frequency
(a) 450 (b) 45 (c) 4.5 (d) 2.52 (c) twice the signal frequency (d) alternate cycles
28. Ideally, the equivalent circuit of a FET contains 42. The value of resistance emulated by a switched-capacitor
(a) a current source in series with a resistance circuit is a function of
(b) a resistance between drain and source terminals (a) voltage and capacitance (b) frequency and capacitance
(c) a current source between gate and source terminals (c) gain and transconductance (d) frequency and
(d) a current source between drain and source terminals transconductance
29. The value of the current source in Question 28 is 43. A basic CMOS circuit uses a combination of
dependent on the (a) n-channel MOSFETs (b) p-channel MOSFETs
(a) transconductance and gate-to-source voltage (c) pnp and npn BJTs (d) an n-channel and a p-channel
(b) dc supply voltage MOSFET
(c) external drain resistance 44. CMOS is commonly used in
(d) answers (b) and (c) (a) digital circuits (b) linear circuits (c) RF circuits (d) power
30. A certain common-source amplifier has a voltage gain of circuits
10. If the source bypass capacitor is removed, 45. If there is an internal open between the drain and source
(a) the voltage gain will increase in a CS amplifier, the drain voltage is
(b) the transconductance will increase equal to
(c) the voltage gain will decrease (a) 0 V (b) VDD (c) VGS (d) VGD
(d) the Q-point will shift
31. A CS amplifier has a load resistance of 10 kΩ and RD =
820 Ω. If gm = 5 mS and Vin = 500 mV, the output signal
voltage is
(a) 1.89 V (b) 2.05 V (c) 25 V (d) 0.5 V
32. If the load resistance in Question 31 is removed, the
output voltage will
(a) stay the same (b) decrease (c) increase (d) be zero

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 EE 171 Take Home Final Examination 4. Determine AVNL, Zi, Zo, AVL, and AVS. Sketch the two-port
Field Effect Transistors model with the parameters determined in place (such as
gmVgs).
Instructions: Show a step-by-step solution with a
supporting statement for each step. Use the textbook for
references. If you choose to use another book, just state
the theorem, definition, or any other to support your
solution. E-mail a photo or a scanned version of your
answer sheets to the given e-mail below.
Note: If there are any similarities with your solution and
a classmate, both of your exams will be deemed invalid
and thus an automatic grade of 5.0.

1.Determine VG, IDQ, VGSQ, VD, VS, and VDSQ.

5. Determine Vo if Vi = 4mV.

2. For the self-bias configuration, determine IDQ, VGSQ, VD,

and VDS.

6. Determine the output voltage of the network if Vi =

0.8mV and rd = 40kΩ.

3. For the voltage-divider circuit, find IDQ, VGSQ, VD, and VS.

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 EE 171 Take Home Removal Examination
Prelim and Midterm

Instructions: Show a step-by-step solution with a

supporting statement for each step. Use the textbook for
references. If you choose to use another book, just state
the theorem, definition, or any other to support your
solution. E-mail a photo or a scanned version of your
Midterm:
answer sheets to the given e-mail below.
For the network given below :
Your score will be multiplied by 60% of the total score
a. Determine AvNL, Z i , and Z o .
which will be your removal score for either your Prelim
b. Sketch the two-port model with the values determined
or Midterm Exam.
in part (a).
c. Determine AvL and Avs.
Prelim:
d. Change R s to 1 kΩ and determine AvL and Avs. What
1. Sketch Vo for the network and determine the dc
is the effect of increasing levels of R s
voltage available.
on the voltage gains?
e. Change R s to 1 k_ and determine AvNL, Z i , and Z o .
What is the effect of increasing levels of R s on the
parameters?
f. Change R L to 5.6 k_ and determine AvL and Avs. What
is the effect of increasing levels of RL on the voltage
gains? Maintain R s at its original level of 0.6 k_.
g. Determine Ai =Io/Ii with RL = 2.7 kΩ and Rs = 0.6 kΩ.
2. Sketch Vo for the network.

3. Design a clamper that performs the function.

4. a. Design the network of the given circuit to maintain

V L at 12 V for a load variation ( I L ) from 0 mA to 200
mA. That is, determine R S and V Z .
b. Determine P Z max for the Zener diode of part (a).

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