Cheat Sheet - EE130

-19 -14
q = 1.6*10 C e0 = 8.85*10 F/cm *lithography/etching = remove SiO2 with photoresist ni2 n 2i
n p0 −x p= p n0 −x n = minority
K_S = 11.8, K_O = 3.9 Eg (Si) = 1.12 eV *Dry/wet etch; dry=precise, wet = easy, cut sides NA ND
-5
Boltzman k = 8.62*10 eV/K Antenna effect, charges left after etching, tunnel 2 qV / kT
-15 pn=ni e A
@ edge of dep region; maj/min
Planck h = 4.14*10 eV*s *Ion Implantation = dopant atoms introduce into Si
Free e Mass, m0 = 9.1*10-31 kg low T vs diff. Dominant process now. n p=n p0 n p  x p n= p n0 pn  x
Effective density of states Nc = 3.22*10^19 cm-3 *Annealing/Diffusion = clean and spread Drift doesn't change with V b/c low numbers
dEg = 3.5*10^(-8) * N^(1/3) eV *Thin Film Deposition, spray metal, > clean sputter Forward bias = more minority @ dep edge
Basic Semiconductors Fundamentals *CVD – deposit ions/nitrides, etc. Reverse bias = black hole @ dep edge
1 − ( E − E f ) / kT Advanced lithography – EUV photo, ebeam, dip-pen ∂ n p ∂2  n p  n p
f (E) = ( E − E f ) / kT approx: f ( E ) = e Positive = light, softens, negative = light hardens
=D N − G L assume E = 0
1+ e ∂t ∂ x2 n
Charge Neutrality: p−n N D −N A=0 Antenna effect – e- flow tunnel beneath oxide ∂ p n
2
∂  p n  pn
Dop gasphase,solid source,in situ (deposit on surface) =D P − G L L p=  D p  p
mn  2m n  E−E C  ∂t x
2
p
 ∂
−E
PN Junctions
G
g c  E =
n i= N C N V e 2kT pi 2 h3 ∂ p n
Forward Bias = Current flows P->N Steady State: 0
2 1
N D−N A N D −N A 2 2 Dep approx: assume carrier inside dep. region = 0 ∂t
n= [  ni ] Mn > Mp in Si 2
∂  pn
2 2 charge density out dep reg = 0 and q(Nd-Na) inside
No gradient/diff current: D 0
E −E E c E v 3 mp d 2 V −dE − qN D 2
P
∂ x
2
n: V  x=V bi −  x − x
i F
E i=  kTln  = =
p=ni e kT 2 4 mn dx 2 dx s 2 s n  pn
No thermal R-G: 0 No light: G L  0


E −E
F i n p 2  V −V  1 1 
E F −E i=kTln =−kTln  W= s bi A
  
p
n=n i e kT ni ni q N A ND Diode Saturation Currents:
Low T = freeze out; high t = intrinsic; else extrinsic Na Nd qN A Dp Dn
kT p: 2 I =Aqn 2
   I =I 0 e
qV / kT
−1
dp v bi = ln  V  x=  x x p  0 i
Lp N d Ln N a
J P =J drift J diff =q  p p E −qD P q n2i 2 s
dx IV curve shifts left @ high T b/c more diffusion
dn qN D 2
J N =J drift J diff =q n n EqD N n-side: V  x=V bi −  x − x Charge storage: I =Q/ s charge/carrier lifetime
dx 2 s n I DC q
mobility units cm^2/(s*V), diffusion = cm^2/s N A x p= N D x n common field in depletion region Capacitance: C= s G Conductance: G=
kT
one that reaches first is first to depleted
Diff len.: L N =  D N n v th =

D kT q mp
 3kT
meff
q  mp
v = E
−q E
Dep reg. Widens under reverse bias
E-field: E  x =
−qN A
 x p x
PIN Junctions
Only e/h generated in dep reg contribute to current
Only light absorbed in dep reg is useful. Avalanches.
=  p= , units : F= 
 q mp mp mp s MS Junctions
1 /2
hi T = phonon scattering, low T = ion scattering 2qN lightly doped rectifying, heavily doped ohmic
Peak E-field: E 0= V bi ∣V r∣
1 s Ideal assumptions: intimate contact, no oxide/charge
= =q n n p p  cm
−1 −1
2 Not ideal: interface pinned Ef 0.4-0.9 eV below Ec
qn n p p  E
Brkd Voltage: V BR= s crit −V bi  BN = M − X Barrier height; work(metal) – EA
Generation: band2band, R-G center, impact ion 2qN
Recomb: direct, R-G, Auger (2 collide, excite 1) 1
Cap diagram slope = 2 /qN  s A2  BN =qV bi [ E G− E FS −E i FB ] barrier height
dn  n  p 2
rate of recombination= = = 1 W 2dep 2 V bi −V A   = X  E −
dt   cap/volt characteristics: = 2 2= BP G M holes' barrier
2 2
Semiconductor Fabrication: C dep A  s qN s A V bi = M −S = B− E C −E F  built-in potential
Vbr decreases with increasing N or decreasing Eg
*oxidation = deposition of SiO2 layer
dry = thin, slow, precise, wet = thick, fast, imprecise p p0 −x p =N A n n0 −x n =N D majority W
 =
2  s V bi −V A 
qN D =
2 s V bi V A
qN A
 t
PN higher V for same I. MS more reverse current. ox
−1 Lowers Id/Vd curve respectively. Degrades perf.
MS = Ideal for rectifying high I, low V. I0 > PN's Fixed charge  V T = ∫
 ox 0
x  ox  x dx alter mobilit Not all Vd drops across channel; some in contacts
Contact both directions, dope heavily to tunnel Vt rolloff – V_t decreases with decreasing length
t ox −Q F
Actual, MS is rectifying. Ohmic needs high N(thin) V FB= MS − Q F  V G  ¿= I_off becomes too large if V_t becomes too small.
−H  −V  /  N
Ohmic when small barrier  C Consequence of reducing oxide thickness.
P=e B A D SiO2 ox
nd
Reduce height/reduce width. 2 works. 1 too rare st Fixed charge due to ionized silicon not oxidized. Reduce tox
Carrier injection @ contact: 3 modes (parameter) Mobile ions shift CV curves. Positive shifts left • Larger Cox raises Ion, better e-field
thermionic emission (work fcn, T, Forward bias), Interface traps smooth out curve; degrade mobility • Reduce subthreshold swing
tunneling (high doping) More surface scattering with lower t_ox • Control Vt rolloff
thermally activated tunneling (high T, high doping) Lower t_ox shifts CV curve down, lowers V_t • Bad – breakdown due to high field; leakage
MOSC MOSFET Define EOT = E_siO2/E_gate dielectric * t_ox


Ideal assumption: no charge in oxide, same Work Fcn V =2  x  si 2qN Hi-k challenges: chemical reaction w/ gate
G F ox   s  n chan (p-si)
1  ox  si lower surface mobility, too low V_t for PMOS
 M =E 0−E FM   x= [E i  bulk− E i x ] Source/drain leakage in body is a problem. Drain
q

 si 2qN
1 1 V G =2  F −x ox   s  p chan (n-si) controls this part. Reduce this w/ UTB, FINFET, SOI.
 S = [ E ibulk −E i  surface]  F = [ E i bulk − E F ] ox  si
q q 2 BJT
W n V DS
I D= C ox V G −V T V DS − ; 0V DS V DSsat Good design: minority carriers don't recombine in B
W=
 2  si ∣ s ∣ E = /  E
qN
ox si ox si  s =2 f

I D=
L
W n 2
2
C V −V T  ; V DS V DSsat ; V G V T
Emitter current almost all from carriers from B
Control doping in base but balance w/ dep width
E max =−
 2qN D
2  si
K si
∣ s ∣=
 2qN A
2  si
∣ s ∣ n/p type
Only
2L ox G
For above, C_ox = e_ox/t_ox, or cap per unit area
apply to diffusive devices, today quasi-ballistic
I E =I B I C current flows to C in pnp, E in npn
Bias Mode E-B Interface C-B Interface
V G = S x ox


2qN
K ox K si  0 s
Decrease t_ox decreases V_T and C_min
  neg for N silicon * Square law also ignores bulk charge effect, assumes Saturation
gate charge balanced by inversion charge, not dep Active
Forward
Forward
Forward
Reverse
* Also ignores changes in dep width
C ox Inverted Reverse Forward
CG= ox Threshold and Subthreshold
 W Poly gate: C= Mobility degrades at high V_GS, minority carriers Cutoff Reverse Reverse
1 ox T ox W dpoly /3
 si x ox flow at low V_GS(subthreshold). Exponential decay. I Ep I Ep
C ox =ox A/t ox C si =si A/W Hi N = little effect Small subthreshold swing is desirable, get sharper Pnp emitter efficiency = =
I E I EpI En
Nonideal: nonmetal gate, charge traps, FB voltage slope.
I
Threshold voltage: larger doping requires small t_ox. I e qV / k T =1 C dep gs
S=60mV 1
C dep Base transport factor T = Cp
 I Ep
ds
Nonmetal gate is problematic; small oxide is good, C ox C ox
Common base gain  dc = T I C =dc I E I CB0
but hard to get smaller. Want high dope in body. Lower swing by Increase Cox, problem – tunneling,
dc I
Poly gate: W dpoly =ox V ox /T ox qN poly scattering Common Emitter dc gain B dc= = C
Decrease C_dep w/ lighter doping. Kills V_t 1− dc I B

 2 s V poly E g kT N gate
W dpoly = V fb = − ln   Decrease Temp I C =B dc I B I CE0
qN poly q q N body
Velocity saturates b/c of high energy collisions. Base width modulation / punchthrough
V th =V fb  st ox
ox 
si 2qN A  s
si
ox
I D =WQinv v drift
1
=
1
V Dsat V GS −V T sat L
Qinv =C ox V GS −V T −V D 

1 High CB bias causes early effect, sloped Ic vs Vec
Base gets shorter and thinner.
Effective tox increase:
T ox W dpoly /3 Ballistic devices often exceed v_sat.
Series resistance shifts IdVg curve to right.