ABSTRACT

In place where control over the machine from a remote location and man power is
reduced considerably and reduces stress and strain, GSM system can do duty Effectively.
This project deals with using GSM system in a mission critical place like power station,
highly secured industries.

This will help to controlling a Machine Manually, controlling a machine through

a wired telephone network, and IR also. The main aim of our project is to control the
speed of the motor by sending an sms via GSM MODEM.

1
 CHAPTER 1

INTRODUCTION

To control the speed of the motor using GSm modem we need the following
requirements,

Microcontroller 89c51

EEPROM

DAC

MAX232

LCD

IR sensor

DC motor

The general block diagram of our project is shown below,

2
1.1 BLOCK DIAGRAM :

FIGURE NO 1:BLOCK DIAGRAM OF SPEED OF DC MOTRO USING GSM

3
 CHAPTER 2

GSM MODEM

This GSM modem is a highly flexible plug and play GSM 900 / GSM 1800 /
GSM 1900 modem for direct and easy integration RS232, voltage range for the power
supply and audio interface make this device perfect solution for system integrators and
single user.

Voice, Data/Fax, SMS, DTMF, GPRS, integrated TCP/P stack and other features
like the GSM / GPRS modules on this homepage.

2.1 GSM MODEM CHARACTERISTICS :

• Dual Band or Triband GSM GPRS modem (EGSM 900/1800MHz) / (EGSM

900/1800 / 1900 MHz )

• Designed for GPRS, data, fax, SMS and voice applications

• Fully compliant with ETSI GSM Phase 2+ specifications (Normal MS)

2.2 GENERAL CHARACTERISTICS :

• Input voltage: 8V-40V

• Input current: 8mA in idle mode, 150mA in communication GSM 900 @ 12V

• Input current: 8mA in idle mode, 110mA in communication GSM 1800 @ 12V

• Temperature range: Operating -20 to +55 degree Celsius; Storage -25 to +70
degree Celsius

• Overall dimensions: 80mm x 62mm x 31mm / Weight: 200g

4
 CHAPTER 3

LCD

The HD44780U dot-matrix liquid crystal display controller and driver LSI
displays alpha numeric, Japanese kana characters, and symbols. It can be configured to
drive a dot-matrix liquid crystal display under the control of a 4- or 8-bit microprocessor.
Since all the functions such as display RAM, character generator, and liquid crystal
driver, required for driving a dot-matrix liquid crystal display are internally provided on
one chip, a minimal system can be interfaced with this controller/driver.

A single HD44780U can display up to one 8-character line or two 8-character

lines. The HD44780U has pin function compatibility with the HD44780S which allows
the user to easily replace an LCD-II with an HD44780U. The HD44780U character
generator ROM is extended to generate 208 5 ´8 dot character fonts and 32 5 ´ 10 dot
character fonts for a total of 240 different character fonts.

The low power supply (2.7V to 5.5V) of the HD44780U is suitable for any
portable battery-driven product requiring low power dissipation.

3.1 FEATURES :

• 5 ´ 8 and 5 ´ 10 dot matrix possible

• Low power operation support:

• ¾ 2.7 to 5.5V

• Wide range of liquid crystal display driver power

• ¾ 3.0 to 11V

• Liquid crystal drive waveform

• ¾ A (One line frequency AC waveform)

5
• Correspond to high speed MPU bus interface

• ¾ 2 MHz (when VCC = 5V)

• 4-bit or 8-bit MPU interface enabled

• 80 ´ 8-bit display RAM (80 characters max.)

6
 CHAPTER 4

MICROCONTROLLER

The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer

with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM). The
device is manufactured using Atmel’s high density nonvolatile memory technology and is
compatible with the industry standard MCS-51™ instruction set and pin out.

The on-chip Flash allows the program memory to be reprogrammed in-system or

by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU
with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which
provides a highly flexible and cost effective solution to many embedded control
applications.

4.1 PIN DIAGRAM :

FIGURE NO :2 PIN DIAGRAM OF MICROCONTROLLER 89C51

4.2 PIN DECRIPTION :

VCC :

7
Supply voltage.

GND :

Ground.

PORT 0 :

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can
sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high
impedance inputs.

Port 0 may also be configured to be the multiplexed low order address/data bus
during accesses to external program and data memory. In this mode P0 has internal
pullups.

Port 0 also receives the code bytes during Flash programming, and outputs the
code bytes during program verification. External pullups are required during program
verification.

PORT 1 :

Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output
buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are
pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that
are externally being pulled low will source current (IIL) because of the internal pullups.

Port 1 also receives the low-order address bytes during Flash programming and
verification.

PORT 2 :

Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output
buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are

8
pulled high by the internal pull ups and can be used as inputs. As inputs, Port 2 pins that
are externally being pulled low will source current (IIL) because of the internal pull ups.

Port 2 emits the high-order address byte during fetches from external program
memory and during accesses to external data memory that use 16-bit addresses (MOVX
@DPTR). In this application it uses strong internal pull-ups when emitting 1s. During
accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits
the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some control signals during
Flash programming and verification.

PORT 3 :

Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output
buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are
pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that
are externally being pulled low will source current (IIL) because of the pullups. Port 3
also serves the functions of various special features of the AT89C51 as listed below: Port
3 also receives some control signals for Flash programming and verification.

PORT FUNCTIONS

P3.0 RXD (serial input port)

P3.1 TXD (serial output port)

P3.2 INT0 (external interrupt 0)

P3.3 INT1 (external interrupt 1)

P3.4 T0 (timer 0 external input)

P3.5 T1 (timer 1 external input)

9
 P3.6 WR (external data memory write strobe)

P3.7 RD (external data memory read strobe)

RST :

Reset input. A high on this pin for two machine cycles while the oscillator is
running resets the device.

ALE/PROG :

Address Latch Enable output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG) during
Flash programming.

In normal operation ALE is emitted at a constant rate of 1/6 the oscillator

frequency, and may be used for external timing or clocking purposes. Note, however, that
one ALE pulse is skipped during each access to external Data Memory. If desired, ALE
operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is
active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled
high. Setting the ALE-disable bit has no effect if the microcontroller is in external
execution mode.

PSEN :

Program Store Enable is the read strobe to external program memory. When the
AT89C51 is executing code from external program memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are skipped during each access to
external data memory.

EA/VPP :

External Access Enable. EA must be strapped to GND in order to enable the

device to fetch code from external program memory locations starting at 0000H up to

10
FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on
reset.

EA should be strapped to VCC for internal program executions. This pin also
receives the 12-volt programming enable voltage (VPP) during Flash programming, for
parts that require 12-volt VPP.

XTAL1 :

Input to the inverting oscillator amplifier and input to the internal clock operating
circuit.

XTAL2 :

Output from the inverting oscillator amplifier.

OSCILLATOR CHARACTERISTICS :

XTAL1 and XTAL2 are the input and output, respectively, of an inverting
amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1.
Either a quartz crystal or ceramic resonator may be used. To drive the device from an
external clock source, XTAL2 should be left unconnected while XTAL1 is driven as
shown in Figure 2. There are no requirements on the duty cycle of the external clock
signal, since the input to the internal clocking circuitry is through a divide-by-two flip-
flop, but minimum and maximum voltage high and low time specifications must be
observed.

11
 CHAPTER 5

EEPROM

The AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial

electrically erasable and programmable read-only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation are
essential.

The AT24C01A/02/04/08/16 is available in space-saving 8-lead PDIP, 8-lead

JEDEC SOIC, 8-lead MAP, 5-lead SOT2(AT24C01A/AT24C02/AT24C04), 8-lead
TSSOP and 8-ball dBGA2 packages and is accessed via a 2-wire serial interface. In
addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to
5.5V)versions.

5.1 FEATURES :

• Low-voltage and Standard-voltage Operation

– 2.7 (VCC = 2.7V to 5.5V)

– 1.8 (VCC = 1.8V to 5.5V)

• Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),

• 1024 x 8 (8K) or 2048 x 8 (16K)

• 2-wire Serial Interface

• Schmitt Trigger, Filtered Inputs for Noise Suppression

• Bi-directional Data Transfer Protocol

• 100 kHz (1.8V) and 400 kHz (2.5V, 2.7V, 5V) Compatibility

12
 • Write Protect Pin for Hardware Data Protection

• 8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes

• Partial Page Writes are Allowed

5.2 PIN DIAGRAM :

FIGURE NO :3 PIN DIAGRAM OF EEPROM

5.3 PIN DESCRIPTION :

5.3.0 SERIAL CLOCK (SCL) :

The SCL input is used to positive edge clock data into each EEPROM device and
negative edge clock data out of each device.

5.3.1 SERIAL DATA (SDA) :

13
 The SDA pin is bi-directional for serial data transfer. This pin is open-drain
driven and may be wire-ORed with any number of other open-drain or open collector
devices.

5.3.2 DEVICE/PAGE ADDRESSES (A2, A1, A0) :

The A2, A1 and A0 pins are device address inputs that are hard wired for the
AT24C01A and the AT24C02. As many as eight 1K/2K devices may be addressed on a
single bus system (device addressing is discussed in detail under the Device Addressing
section).

The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of
four 4K devices may be addressed on a single bus system. The A0 pin is a no connect.

The AT24C08 only uses the A2 input for hardwire addressing and a total of two
8K devices may be addressed on a single bus system. The A0 and A1 pins are no
connects.

The AT24C16 does not use the device address pins, which limits the number of
devices on a single bus to one. The A0, A1 and A2 pins are no connects.

5.3.3 WRITE PROTECT (WP):

The AT24C01A/02/04/16 has a Write Protect pin that provides hardware data
protection. The Write Protect pin allows normal read/write operations when connected to
ground (GND). When the Write Protect pin is connected to VCC, the write protection
feature is enabled.

14
 CHAPTER 6

DIGITAL TO ANALOG CONVERTOR

6.1 FEATURES :

• Single power supply

• Operating supply voltage 2.5 V to 6 V

• Low standby current

• Serial input/output via I2C-bus

• Address by 3 hardware address pins

• Sampling rate given by I2C-bus speed

• 4 analog inputs programmable as single-ended or differential inputs

6.1 PIN DIAGRAM :

FIGURE NO :4 PIN DIAGRAM OF DAC

15
 CHAPTER 7

MAX232

The Max 232 is a dual RS-232 receiver / transmitter that meets all EIA RS232C
specifications while using only a +5V power supply. It has 2 onboard charge pump
voltage converters which generate +10V and –10V power supplies from a single 5V
power supply. It has four level translators, two of which are RS232 transmitters that
convert TTL\ CMOS input levels into + 9V RS232 outputs. The other two level
translators are RS232 receivers that convert RS232 inputs to 5V.

TTL\CMOS output level. These receivers have a nominal threshold of 1.3V, a

typical hysterisis of 0.5V and can operate upto + 30V input.

1. Suitable for all RS232 communications.

2. +12V power supplies required.

3. Voltage quadrapular for input voltage upto 5.5V (used in power supply Section of
computers, peripherals, and modems).

Three main sections of MAX232 are

1. A dual transmitter

2. A dual receiver

3. +5V to + 10V dual charge pump voltage converter.

7.1 TRANSMITTER SECTION :

Each of the two transmitters is a CMOS inverter powered by + 10V internally

generated supply. The input is TTL and CMOS compatible with a logic threshold of
about 26% of Vcc. The input if an unused transmitter section can be left unconnected: an

16
internal 400KΩ pull up resistor connected between the transistor input and Vcc will pull
the input high forming the unused transistor output low.

The open circuit output voltage swing is guaranteed to meet the RS232
specification + 5v output swing under the worst of both transmitter driving the 3KΩ

Minimum load impedance, the Vcc input at 4.5V and maximum allowable ambient
temperature typical voltage with 5KΩ and Vcc= +.9 v

The slow rate at output is limited to less than 30V/μs and the powered done
output impedance will be a minimum of 300Ω with +2V applied to the output with Vcc
=0V.The outputs are short circuit protected and can be short circuited to ground
indefinitely.

7.2 RECIEVER SECTION :

The two receivers fully conform to RS232 specifications. They’re input

impedance is between 3KΩ either with or without 5V power applied and their switching
threshold is within the +3V of RS232 specification. To ensure compatibility with either
RS232 IIP or TTl\CMOS input. The MAX232 receivers have VIL of 0.8V and VIH of
2.4V the receivers have 0.5V of hysterisis to improve noise rejection.

The TTL\CMOS compatible output of receiver will be low whenever the RS232
input is greater than 2.4V. The receiver output will be high when input is floating or
driven between +0.8V and –30V.

Electrical characteristics of MAX232

Vcc = 6v V+ = 12v V- = 12v EQ NO :1

17
7.3 PIN DIAGRAM OF MAX 232:

FIGURE NO : 5 PIN DIAGRAM OF MAX232

18
 CHAPTER 8

RS 232

The most common communication interface for short distance is RS-232. RS-232
defines a serial communication for one device to one computer communication port, with
speeds upto 19,200 baud. Typically 7 or 8 bits (on/off) signal are transmitted to represent
a character or digit. The 9 pin connector is used. The pin details is given below.

8.1 RS-232 TO TTL CABLE :

A common feature found on many Microcontrollers is a serial port (often called a

SCI, COM, or ASYNC port). I am going to use the term SCI as a short cut to mean the
serial port on your Microcontroller. Quite often, the SCI on your Microcontroller will
generate the appropriate LOGIC signals to communicate with another chip. They do not,
however, generate the proper voltages required for connecting to RS-232 devices. This
article is going to describe the differences between RS-232 and TTL, and how to build a
converter so you can connect your Microcontroller to an RS-232 compatible device, such
as the COM port on your PC.

Most microcontrollers run on a single supply voltage, and 99 out of 100 times,
that voltage is +5 volts. In rough terms, logical 1 on these devices indicates that +5 is the
voltage on the output pin. Logical 0 specifies that 0 volts is on the line.

The RS-232-C standard specifies that the voltage on the wire for sending a logical
0 are from +5v to +15v. The voltage for sending a 1 are from -5v to -15v. Most
microcontrollers not capable of generating these voltages. So, to connect a
microcontroller SCI port to a true RS-232 device, you need to convert the TTL voltages
of 0 and +5 into voltages between about -10 volts and +10 volts.

19
 CHAPTER 9

OPTICALLY COUPLED OPTOCOUPLER IC

The H11GX series are photodarlington-type optically coupled optocouplers.

These devices have agallium arsenide infrared emitting diode coupled with a silicon
darlington connected phototransistor which has an integral base-emitter resistor to
optimize elevated temperature characteristics.

9.1 FEATURES :

• High BVCEO

Minimum 100 V for H11G1

Minimum 80 V for H11G2

Minimum 55 V for H11G3

• High sensitivity to low input current

• Minimum 500 percent CTR at IF = 1 mA

• Low leakage current at elevated temperature

• (maximum 100 μA at 80°C)

• Underwriters Laboratory (UL) recognized File# E90700

20
9.2 PIN DIAGRAM :

FIGURE NO :6 PIN DIAGRAM OF H11G1 IC

9.3 APPLICATIONS :

• CMOS logic interface

• Telephone ring detector

• Low input TTL interface

• Power supply isolation

• Replace pulse transformer

21
 CHAPTER 10

RAMP GENERATOR

A precision ramp generator produces a 0 to 5V ramp while operating from a

single 5V supply.

Using standard circuits and no auxiliary voltage generators, such as charge pumps
or inductive DC-DC converters, it is difficult to build a precision, rail-to-rail ramp
generator that operates on a single supply and resets to a well-defined level. implements
such a circuit using a bootstrapped series reference and an op amp with rail-to-rail I/O
and very low bias current.

The ramp is generated by a constant charging current into capacitor CRAMP,

which is connected between ground and

the noninverting input of op amp IC1, configured as a voltage follower. The current
through RRAMP is the charging current, kept constant by forcing the voltage across
RRAMP to equal the reference voltage from IC1. One side of RRAMP is connected to
CRAMP, and the other side to the reference output. In turn, the ground terminal of the
reference IC connects to the op-amp output, which provides a low-impedance replica of
the voltage across CRAMP.

Thus, the op-amp output follows the CRAMP voltage and drives the GND pin of
the IC2 reference, keeping the voltage across RRAMP equal to VREF. A 1μF capacitor
from the op-amp output bootstraps IC1's supply-voltage input, driving it above the
nominal level yet keeping it within that device's operating range, and thereby allowing
the op-amp output to reach its own supply-rail voltage.

A MOSFET switch across the ramp capacitor returns the ramp output to 0V when
RAMP_DISABLE goes high, allowing the ramp to develop when RAMP_DISABLE is
low. A scope shot of the ramp shows the excursion limits for a supply voltage of 5.00V.
The ramp slope is:

22
 ……….EQ NO :2

10.1 RAMP WAVEFORM :

FIGURE NO :7 RAMP WAVEFORM

23
 CHAPTER 11

TRIAC DRIVER DEVICE M0C3022

The MOC301XM and MOC302XM series are optically isolated triac driver
devices. These devices contain a GaAs infrared emitting diode and a light activated
silicon bilateral switch, which functions like a triac. They are designed for interfacing
between electronic controls and power triac to control resistive and inductive loads for
115/240 VAC operations.

11.1 FEATURES :

• Excellent IFT

stability—IR emitting diode has low degradation

• High isolation voltage—minimum 5300 VAC RMS

• Underwriters Laboratory (UL) recognized—File #E90700

• Peak blocking voltage

250V-MOC301XM

400V-MOC302XM

• VDE recognized (File #94766)

Ordering option V (e.g. MOC3023VM)

24
11.2 PIN DIAGRAM :

FIGURE NO :8 PIN DIAGRAM OF MOC3022

11.3 APPLICATIONS :

• Industrial controls

• Solenoid/valve controls

• Traffic lights

• Static AC power switch

• Vending machines

• Incandescent lamp dimmers

25
 CHAPTER 12

COMPARATOR OPERATION

The following drawing show the two simplest configurations for voltage
comparators. The diagrams below the circuits give the output results in a graphical form.

For these circuits the REFERENCE voltage is fixed at one-half of the supply
voltage while the INPUT voltage is variable from zero to the supply voltage.

In theory the REFERENCE and INPUT voltages can be anywhere between zero
and the supply voltage but there are practical limitations on the actual range depending on
the particular device used.

FIGURE NO :9 BASIC OPERATION OF COMPARATORS

26
12.1 INPUT VS OUTPUT RULES :

1. Current WILL flow through the open collector when the voltage at the PLUS
input is lower than the voltage at the MINUS input.

2. Current WILL NOT flow through the open collector when the voltage at the
PLUS input is higher than the voltage at the MINUS input.

12.2 DIFFERENCE BETWEEN ANALOG AND DIGITAL GROUND :

Generally, all digital grounds are gathered to a single point. Likewise all analog
grounds are gathered to a single point. Then generally there is some connection between
the two grounds, so they have no DC potential difference. That connection may well be a
choke, which will allow the two grounds to have the same DC potential, but hopefully it
will keep the AC noise, which tends to be pretty "loud" on the digital ground due to the
high speed switching currents, off the analog ground and hopefully therefore keep it
quieter.

27
 CHAPTER 13

I2C BUS

• Only two bus lines are required; a serial data line (SDA) and a serial clock line
(SCL)

• Each device connected to the bus is software addressable by a unique address and
simple master/ slave relationships exist at all times; masters can operate as
master-transmitters or as master-receivers

• It’s a true multi-master bus including collision detection and arbitration to prevent
data corruption if two or more masters simultaneously initiate data transfer

• Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 kbit/s
in the standard mode or up to 400 kbit/s in the fast mode

• On-chip filtering rejects spikes on the bus data line to preserve data integrity

• The number of ICs that can be connected to the same bus is limited only by a
maximum bus capacitance of 400 pF.

13.1 DESIGNER BENEFITS :

I2C-bus compatible ICs allow a system design to rapidly progress directly from a
functional block diagram to a prototype. More over, since they ‘clip’ directly onto the
I2C-bus without any additional external interfacing, they allow a prototype system to be
modified or upgraded simply by ‘clipping’ or ‘unclipping’ ICs to or from the bus.

Here are some of the features of I2C-bus compatible ICs which are

particularly attractive to designers:

• Functional blocks on the block diagram correspond with the actual ICs; designs
proceed rapidly from block diagram to final schematic

28
 • No need to design bus interfaces because the I2C-bus interface is already
integrated on-chip

• Integrated addressing and data-transfer protocol allow systems to be completely

software-defined

• The same IC types can often be used in many different applications

• Design-time reduces as designers quickly become familiar with the frequently

used functional blocks represented by I2C-bus compatible ICs

• ICs can be added to or removed from a system without affecting any other circuits
on the bus

• Fault diagnosis and debugging are simple; malfunctions can be immediately

traced

• Software development time can be reduced by assembling a library of reusable

software modules. In addition to these advantages, the CMOS ICs in the I2C-bus
compatible range offer designers special features which are particularly attractive
for portable equipment and battery-backed systems.

13.2 ADVANTAGE :

• Extremely low current consumption

• High noise immunity

• Wide supply voltage range

• Wide operating temperature range.

29
 CHAPTER 14

CIRCUIT DIAGRAM

30
 TABLE OF CONTENTS

CHAPTER NO TITLE PAGE NO

ACKNOWLDEGEMENT III

ABSTRACT 1

LIST OF TABLES IX

LIST OF FIGURES IX

1 INTRODUCTION 2

1.1 BLOCK DIAGRAM 3

2 GSM MODEM 4

2.1 GSM CHARACTERISTICS 4

2.2 GENERAL CHARACTERISTICS 4

3 LIQUID CRYSTAL DISPLAY 5

3.1 FEATURES 5

4 MICROCONTROLLER 7

4.1 PIN DIAGRAM 7

4.2 PIN DESCRIPTION 7

 vii

5 EEPROM 12

5.1 FEATURES 12

5.2 PIN DIAGRAM 13

5.3 PIN DESCRIPTION 13

6 DAC 15

6.1 FEATURES 15

6.2 PIN DIAGRAM 15

7 MAX232

7.1 TRANSMITTER SECTION 16

7.2 RECEIVER SECTION 17

7.3 PIN DIAGRAM 18

8 RS232 19

8.1 RS232 TO TTL CABLE 19

9 OPTO COUPLER IC 20

9.1 FEATURES 20

9.2 PIN DIAGRAM 21

9.3 APPLICATION 21

10 RAMP GENERATOR 22

10.1 RAMP WAVEFORM 23

 viii

11 MOC 3022 IC 24

11.1 FEATURES 24

11.2 PIN DIAGRAM 25

11.3 APPLICATION 25

12 COMPARATOR OPERATION 26

12.1 INPUT VS OUTPUT RULE 26

12.2 DIFF BETWEEN ANALOG AND DIGITAL GROUND 27

13 12C BUS 28

13.1 DESIGNER BENEFITS 28

13.2 ADVANTAGE 29

14 CIRCUIT DIAGRAM

14.1 TRIAC FIRING CIRCUIT

14.2 WORKING

14.3 WAVEFORM

15 FLOWCHART

15.1 ALGORITHM

15.2 CODING

16 CONCLUSION

16.1 APPLICATION

17 REFERENCE
 ix

LIST OF FIGURES

FIG NO TITLE PAGE NO

1 BLOCK DIAGRAM 3

2 MICROCONTROLLER PIN DIAGRAM 4

3 EEPROM PIN DIAGRAM 6

4 DAC PIN DIAGRAM 7

5 MAX232 IC PIN DIAGRAM 10

6 OPTOCOUPLER IC PIN DIAGRAM 15

7 RAMP WAVEFORM 15

8 PIN DIAGRAM MOC3022 18

9 BASIC OPERATION OF

COMPARATORS 20

10 CIRCUIT DIAGRAM 31

11 TRIAC FIRING CIRCUIT 32

12 WAVEFORM 33
13 FLOWCHART 34
 PROJECT REPORT
On
SPEED CONTROL OF DC MOTOR USING GSM

Submitted in partial fulfillment for the award of the degree

Of

BACHELOR OF TECHNOLOGY
in
ELECTRICAL AND ELECTRONICS ENGINEERING

by
T . RENGASAMY (10503046)
J . VINOTH KUMAR (10503066)
A . GOPINATH (10503071)
S . KANNAN (10503072)
Under the guidance of

Mr. K.MOHANRAJ, M.E.,

(lecturer , Electrical And Electronics Engineering)

FACULTY OF ENGINEERING AND TECHNOLOGY

S.R.M UNIVERSITY
(Under section 3of UGC Act,1956)
SRM Nagar, kattankulathur-603 203
Kancheepuram Dist.
April 2007
 BONAFIDE CERTIFICATE

Certified that this project report "SPEED CONTROL OF DC

MOTOR USING GSM "is the bonafide work of"
T .RENGASAMY (10503046), J . VINOTH KUMAR
(10503066), A . GOPINATH (10503071), S . KANNAN
(10503072)” who carried out the project work under my supervision.

HEAD OF THE DEPARTMENT INTERNAL GUIDE

Date :
 ACKNOWLEDGEMENT

I express my gratitude towards the great engineer who is the designer

of speed control of DC motor using GSM in him by him and through him

humanity still has hope.

I take this opportunity to thank Prof.R.Venkatramani, Dean, SRM

university for granting me the permission to carry out the work in the

institution

I express my sincere gratitude to Mr.R.Chidambaram prof./Head,

Dept. of electrical and electronic Engineering , SRM university for this

valuable suggestion during my thesis work

I offer my sincere thanks to my internal guide Mr. Mohanraj.K ME.,

Lect., Dept. of EEE SRM university for all the valuable guidance he

provided me during the course of thesis.

I would like to acknowledge SRM staff members particularly the

project co - ordinator MR.C.Vaithilingam and the students for establishing

an enjoyable working environment.

Finally I would like to thank my beloved parents and my friends for

their love and tenacious process. This work is their legacy.