.By7d Brazos 2.0 MB SCH (8L) - Ramp1 Final - (Mindy) - (E201203-6361) - 20120321C R1a 0312 PDF

5 4 3 2 1
PCB STACK UP
14" BY7D Brazos 2.0 Block Diagram 01
LAYER 1 : TOP
LAYER 2 : GND UMA DISCRETE
AMD FUSION APU
INT_HDMI
LAYER 3 : IN1 Zacate/Ontario EXT_HDMI
D HDMI PG 25 D
LAYER 4 : SVCC
413-BALL INT_LVDS
LAYER 5 : IN2 DDRIII-SODIMM2 DDRIII-SODIMM1 EXT_LVDS
LVDS PG 30
PG 12 PG 11 19mmX19mm BGA
LAYER 6 : IN3
INT_CRT
LAYER 7 : GND EXT_CRT
CRT PG 30
SINGLE CHANNEL DDR3
LAYER 8 : BOT
DISPLAY PORT X2
DX11 IGP
4 X1 PCIE GEN2 GPP
1 X4 UMI-LINK GEN1
VGA DAC Graphics
PCI-E X4
Seymour XTX VRAM DDR3
PG 3,4,5
PAGE 21, 22
29mm X 29mm
PG 13,14,15,16,17,18,19,20
X'TAL VGA AMD Seymour XTX
27.0MHz
C UMI LINK POWER SYSTEM

DP1(x4) 2.5GT /s ISL88731CHRTZ-T P36
C
RT8223P P37
UMI(x4) TPS51216RUKR P38
TPS51211DSCR P39
DMI TPS51211DSCR P40
SATA - HDD Con. SATA 0 USB 2.0 (Port0~13) USB2-0 USB2.0 Con.
USB2.0 TPS51211DSCR P40
P31 P24
OZ8380ALN P41
SATA
USB2-5 ISL95870AHRUZ P42
SATA - ODD Con. SATA 1 Card Reader 3 IN 1
P31 Card Reader Con.
(AU6437B53-GDL-GR) P29 P29
P36
PCI-E, 1X (port2) CHARGER
RJ45 AR8152(10/100) PCIE USB2-6 CCD
PG 26 PG 26 P30 +15V P37
AMD
PCI-E, 1X (port0) +3VPCU
Mini Card I (WIFI) Hudson M3L USB 3.0 (Port0~3) USB3-0
PG 28 USB2.0 (P7) USB3.0 +3V_S5
USB2-10 USB3.0 Con. +3V
P24 +3V_GPU
FCH +5VPCU
USB3-1 +5V_S5
BATTERY RTC 24.5mm X 24.5mm USB3.0 re-driver IC
B
P7 P24 +5V B
X'TAL
32.768KHz DISCHARGE
LPC USB2-11 USB3.0 Con. +SMDDR_VTERM P38

P6, 7, 8, 9, 10
Azalia P24 +SMDDR_VREF
SPI IHDA
+1.5VSUS
+1.5V
+1.5V_GPU
SPI
P39
+1.0V
Share SPI flash +1.0V_GPU
PG 34
P40
Audio Codec CX20671-21Z +1.1V_S5
+1.1V
EC PG 27 +1.8V
+1.8V_GPU
PORT-A
PORT-B
NPCE885L
PG 34 P41
A CPU_CORE A
CPU_VDDNB_CORE
P42
MIC INT. +VGPU_CORE
FAN Keyboard Touch Pad LED Hall Sensor Touch Pad/B Power/B HP DMIC
JACK SPEAKER
PG 32 PG 33 PG 33 PG 35 PG 30 Con. PG 33 Con. PG 33 PG 27 PG 27 PG 27 PG 27 Quanta Computer Inc.
5 www.Teknisi-Indonesia.com 4 3 2
Size
Date:
Document Number
PROJECT : BY7D
Block Diagram
Monday, March 12, 2012
1
Sheet 1 of 45
Rev
1A
5 4 3 2 1
BOI
02
PAGE DESCRIPTION FUNCTIONS CONTROL Power States ITEM Value Code FUNCTIONS
POWER PLANE VOLTAGE SIGNAL ACTIVE IN 1 CEC@ CEC
1 Schematic Block Diagram
2 NMP@ LPC Debug Card
2 POWER STAGE & BOI-FUNCTION
VIN 10V~+19V S0~S5 3 512M@ VRAM 512M
3-5 Processor CPU
4 1GCA@ VRAM 1Gb*4(C-die, A-die)
D 6 - 10 FCH CLG +VCCRTC +3.0V~+3.3V S0~S5 D
5 1GEB@ VRAM 1Gb*4(E-die, B-die)
7 RTC RTC
+3V +3.3V MAINON S0 6 2G@ VRAM 2Gb
11 - 12 DDRIII SO-DIMM DDR
7 AMD@ AMD VRAM
13 - 20 Seymour XTX(M2) VGA +3V_S5 +3.3V S5_ON S0~S5
8 Sam@ Samsung VRAM
21 - 22 VRAM - DDR3 VGA
+3VPCU +3.3V AC/DC Insert enable S0~S5 9 EV@ DISCRETE
23 RESERVE VGA
10 IV@ UMA
24 USB Connector USB +5V +5V MAINON S0
11 ECRT@ DISCRETE CRT
USB 3.0 Redriver U3B
+5V_S5 +5V S5_ON S0~S5 12 ICRT@ UMA CRT
USB Sleep Charger SLC
13 EHM@ DISCRETE HDMI
25 HDMI comm part HDM +5VPCU +5V AC/DC Insert enable S0~S5
14 IHM@ UMA HDMI
CEC CEC
WIMAX_P +3.3V WMAX_P S0 15 U3@ Internal USB 3.0
26 Atheros LAN LAN
16 U2@ USB 2.0 (colay W USB 3.0)
27 Codec (CX20671-21Z) ADO +1.8V +1.8V MAINON S0
17 ULD@ USB Port (Left Down)
28 MINI Card (Wi-Fi & WIMAX) MNW
+1.5VSUS +1.5V SUSON S0~S3 18 ULU@ USB Port (Left Up)
29 Card reader MMC
19 ULU2@ USB 2.0 Port (Left Up)
30 VGA Connector VGA +1.5V +1.5V MAINON S0
20 ULU3@ USB 3.0 Port (Left Up)
LCD Panel LDS
+1.1V_S5 +1.1V +1.1V_DUAL_EN S0~S5 21 UR@ USB Port (Right)
CRT & CRT BUS SWITCH CRT
22 UR2@ USB 2.0 Port (Right)
CCD CCD +1.1V +1.1V MAINON S0
C 23 UR3@ USB 300 Port (Right) C
HALL SENSOR&BACK LIGHT SWITCH HSR
+1V +1V MAINON S0
31 HDD HDD
ODD ODD CPU_CORE ~ VRON S0
32 Thermal THC
CPU_VDDNB_CORE ~ VRON S0
FAN THC
33 KeyBoard KBC +VGPU_CORE GPU_VRON S0
TP&FP board TPD,FPD
+1.8V_GPU +1.8V GPU_MAINON S0
Power SW PSW
34 EC NPCE885LA0DX KBC +1V_GPU +1V GFXPG_1V_EN S0
35 LED LED
+3V_GPU +3.3V GPU_MAINON S0
36 CHARGER-ISL88731C PWM
37 System 3V/5V(TPS51123A) PWM +1.5V_GPU +1.5V GPU_MAINON S0
38 DDR 1.5V PWM
39 +1.0V PWM
40 +1.1V/+1.8V PWM
41 CPU CORE PWM
42 GPU PWM
43 Power Tree
B 44 Power Sequence B
45 Change List
GND PLANE PAGE
8769GND 34
26
GND ALL
ADOGND 27
Shield_GND 27
A A
www.Teknisi-Indonesia.com
Quanta Computer Inc.
PROJECT : BY7D
Size Document Number Rev
1A
POWER STAGE & BOI-FUNCTION
Date: Tuesday, March 06, 2012 Sheet 2 of 45
5 4 3 2 1
1 2 3 4 5 6 7 8
(11,12) M_A_A[15:0]
M_A_A0 R17
M_A_A1 H19
U5038E
M_ADD0
ONTARIO (2.0)
M_DATA0 B14 M_A_DQ0
M_A_DQ1
M_A_DQ[0..63] (11,12)
03
M_ADD1
PART 1 OF 5
M_DATA1 A15
M_A_A2 J17 M_ADD2 M_DATA2 A17 M_A_DQ2
M_A_A3 H18 M_ADD3 M_DATA3 D18 M_A_DQ3
M_A_A4 H17 M_ADD4 M_DATA4 A14 M_A_DQ4
M_A_A5 G17 M_ADD5 M_DATA5 C14 M_A_DQ5
M_A_A6 H15 M_ADD6 M_DATA6 C16 M_A_DQ6
M_A_A7 G18 M_ADD7 M_DATA7 D16 M_A_DQ7
M_A_A8 F19 M_ADD8
M_A_A9 E19 M_ADD9 M_DATA8 C18 M_A_DQ8
M_A_A10T19 M_ADD10 M_DATA9 A19 M_A_DQ9 PEG_TXN[3:0]
PEG_TXN[3:0] (13)
M_A_A11F17 M_ADD11 M_DATA10 B21 M_A_DQ10
M_A_A12E18 M_ADD12 M_DATA11 D20 M_A_DQ11 PEG_TXP[3:0]
A PEG_TXP[3:0] (13) A
M_A_A13
W17 M_ADD13 M_DATA12 A18 M_A_DQ12
M_A_A14E16 M_ADD14 M_DATA13 B18 M_A_DQ13 PEG_RXN[3:0]
PEG_RXN[3:0] (13)
M_A_A15G15 M_ADD15 M_DATA14 A21 M_A_DQ14
(11,12) M_A_BS#[2..0] PEG_RXP[3:0]
M_DATA15 C20 M_A_DQ15 PEG_RXP[3:0] (13)
M_A_BS#0
R18 M_BANK0
M_A_BS#1
T18 M_BANK1 M_DATA16 C23 M_A_DQ16
M_A_BS#2
F16 M_BANK2 M_DATA17 D23 M_A_DQ17 U5038A
(11,12) M_A_DM[7..0]
M_DATA18 F23 M_A_DQ18 PEG_RXP0 AA6 P_GPP_RXP0 P_GPP_TXP0 AB6 C_PEG_TXP0 C5562 EV@0.1U/10V_4X PEG_TXP0
M_A_DM0 D15 M_DM0 M_DATA19 F22 M_A_DQ19 PEG_RXN0 Y6 P_GPP_RXN0 P_GPP_TXN0 AC6 C_PEG_TXN0 C5563 EV@0.1U/10V_4X PEG_TXN0
M_A_DM1 B19 M_DM1 M_DATA20 C22 M_A_DQ20 ONTARIO (2.0)
M_A_DM2 D21 M_DM2 M_DATA21 D22 M_A_DQ21 PEG_RXP1 AB4 P_GPP_RXP1 PART 2 OF 5 P_GPP_TXP1 AB3 C_PEG_TXP1 C5564 EV@0.1U/10V_4X PEG_TXP1
M_A_DM3 H22 M_DM3 M_DATA22 F20 M_A_DQ22 PEG_RXN1 AC4 P_GPP_RXN1 P_GPP_TXN1 AC3 C_PEG_TXN1 C5565 EV@0.1U/10V_4X PEG_TXN1
M_A_DM4 P23 M_DM4 M_DATA23 F21 M_A_DQ23
M_A_DM5 V23 M_DM5 PEG_RXP2 AA1 P_GPP_RXP2 P_GPP_TXP2 Y1 C_PEG_TXP2 C5566 EV@0.1U/10V_4X PEG_TXP2
M_A_DM6
AB20 M_DM6 M_DATA24 H21 M_A_DQ24 PEG_RXN2 AA2 P_GPP_RXN2 P_GPP_TXN2 Y2 C_PEG_TXN2 C5567 EV@0.1U/10V_4X PEG_TXN2
PCIE I/F
M_A_DM7
AA16 M_DM7 M_DATA25 H23 M_A_DQ25
M_DATA26 K22 M_A_DQ26 VDD_10 PEG_RXP3 Y4 P_GPP_RXP3 P_GPP_TXP3 V3 C_PEG_TXP3 C5568 EV@0.1U/10V_4X PEG_TXP3
A16 M_DQS_H0 M_DATA27 K21 M_A_DQ27 PEG_RXN3 Y3 P_GPP_RXN3 P_GPP_TXN3 V4 C_PEG_TXN3 C5569 EV@0.1U/10V_4X PEG_TXN3
(11,12) M_A_DQSP0
B16 M_DQS_L0 M_DATA28 G23 M_A_DQ28
(11,12) M_A_DQSN0
B20 M_DQS_H1 M_DATA29 H20 M_A_DQ29 R9782 2K/F_4
ON_ZVDD Y14 P_ZVDD_10 P_ZVSS AA14 ON_ZVSS R9783 1.27K/F_4
(11,12) M_A_DQSP1
A20 M_DQS_L1 M_DATA30 K20 M_A_DQ30
(11,12) M_A_DQSN1
E23 M_DQS_H2 M_DATA31 K23 M_A_DQ31
(11,12) M_A_DQSP2
(11,12) M_A_DQSN2 E22 M_DQS_L2
MEMORY I/F
J22 M_DQS_H3 M_DATA32 N23 M_A_DQ32 (7) UMI_RXP0 AA12 P_UMI_RXP0 P_UMI_TXP0 AB12 UMI_TXP0_C C5570 0.1U/10V_4X UMI_TXP0 (7)
(11,12) M_A_DQSP3
J23 M_DQS_L3 M_DATA33 P21 M_A_DQ33 (7) UMI_RXN0 Y12 P_UMI_RXN0 P_UMI_TXN0 AC12 UMI_TXN0_C C5571 0.1U/10V_4X UMI_TXN0 (7)
(11,12) M_A_DQSN3
R22 M_DQS_H4 M_DATA34 T20 M_A_DQ34
(11,12) M_A_DQSP4
P22 M_DQS_L4 M_DATA35 T23 M_A_DQ35 (7) UMI_RXP1 AA10 P_UMI_RXP1 P_UMI_TXP1 AC11 UMI_TXP1_C C5572 0.1U/10V_4X UMI_TXP1 (7)
(11,12) M_A_DQSN4
W22 M20 M_A_DQ36 Y10 AB11 UMI_TXN1_C C5573 0.1U/10V_4X
UMI I/F
M_DQS_H5 M_DATA36 (7) UMI_RXN1 P_UMI_RXN1 P_UMI_TXN1 UMI_TXN1 (7)
(11,12) M_A_DQSP5
V22 M_DQS_L5 M_DATA37 P20 M_A_DQ37
(11,12) M_A_DQSN5
(11,12) M_A_DQSP6 AC20 M_DQS_H6 M_DATA38 R23 M_A_DQ38 (7) UMI_RXP2 AB10 P_UMI_RXP2 P_UMI_TXP2 AA8 UMI_TXP2_C C5574 0.1U/10V_4X UMI_TXP2 (7)
AC21 M_DQS_L6 M_DATA39 T22 M_A_DQ39 (7) UMI_RXN2 AC10 P_UMI_RXN2 P_UMI_TXN2 Y8 UMI_TXN2_C C5575 0.1U/10V_4X UMI_TXN2 (7)
(11,12) M_A_DQSN6
(11,12) M_A_DQSP7 AB16 M_DQS_H7
(11,12) M_A_DQSN7 AC16 M_DQS_L7 M_DATA40 V20 M_A_DQ40 (7) UMI_RXP3 AC7 P_UMI_RXP3 P_UMI_TXP3 AB8 UMI_TXP3_C C5576 0.1U/10V_4X UMI_TXP3 (7)
M_DATA41 V21 M_A_DQ41 (7) UMI_RXN3 AB7 P_UMI_RXN3 P_UMI_TXN3 AC8 UMI_TXN3_C C5577 0.1U/10V_4X UMI_TXN3 (7)
(12) M_A_CLKP0 M17 M_CLK_H0 M_DATA42 Y23 M_A_DQ42
(12) M_A_CLKN0 M16 M_CLK_L0 M_DATA43 Y22 M_A_DQ43 FT1_ONTARIO
(12) M_A_CLKP1 M19 M_CLK_H1 M_DATA44 T21 M_A_DQ44
(12) M_A_CLKN1 M18 M_CLK_L1 M_DATA45 U23 M_A_DQ45
(11) M_A_CLKP2 N18 M_CLK_H2 M_DATA46 W23 M_A_DQ46
B (11) M_A_CLKN2 N19 M_CLK_L2 M_DATA47 Y21 M_A_DQ47 B
+1.5VSUS
(11) M_A_CLKP3 L18 M_CLK_H3
(11) M_A_CLKN3 L17 M_CLK_L3 M_DATA48 Y20 M_A_DQ48

M_DATA49 AB22 M_A_DQ49
(11,12) M_A_RST# L23 M_RESET_L M_DATA50 AC19 M_A_DQ50
N17 M_EVENT_L M_DATA51 AA18 M_A_DQ51 +M_VREF R9784
(11,12) M_A_EVENT#
M_DATA52 AA23 M_A_DQ52 1K/F_4
M_DATA53 AA20 M_A_DQ53
(11,12) M_A_CKE0 F15 M_CKE0 M_DATA54 AB19 M_A_DQ54
(11,12) M_A_CKE1 E15 M_CKE1 M_DATA55 Y18 M_A_DQ55
M_DATA56 AC17 M_A_DQ56

M_DATA57 Y16 M_A_DQ57 R9786 C5578 C5579
W19 M0_ODT0 M_DATA58 AB14 M_A_DQ58 1K/F_4 M_A_EVENT# R9787 1K/F_4 +1.5VSUS
(12) M_A_ODT0
(12) M_A_ODT1 V15 M0_ODT1 M_DATA59 AC14 M_A_DQ59 0.1U/10V_4X 1000P/50V_4X
(11) M_A_ODT2 U19 M1_ODT0 M_DATA60 AC18 M_A_DQ60
(11) M_A_ODT3 W15 M1_ODT1 M_DATA61 AB18 M_A_DQ61
M_DATA62 AB15 M_A_DQ62
(12) M_A_CS#0 T17 M0_CS_L0 M_DATA63 AC15 M_A_DQ63
(12) M_A_CS#1 W16 M0_CS_L1
(11) M_A_CS#2 U17 M1_CS_L0
(11) M_A_CS#3 V16 M1_CS_L1 M_VREF M23 +M_VREF
(11,12) M_A_RAS# U18 M_RAS_L
(11,12) M_A_CAS# V19 M_CAS_L

V17 M_WE_L M_ZVDDIO_MEM_S M22 39.2/F_4 R9789 +1.5VSUS
(11,12) M_A_WE#
FT1_ONTARIO
C C
D D

PROJECT : BY7D
1A
ONTARIO MEM & PCIE I/F(1/3)
Date: Wednesday, March 21, 2012 Sheet 3 of 45
1 2 3 4 5 6 7 8
1
CNTR_VREF
+1.8V
R9790
CNTR_VREF +3V
R9792
04
*20K/F_4
2
U5038B R9794 *1K/F_4
IHM@0.1U/10V_4X ANALOG/DISPLAY/MISC *0_4
INT_HDMI_TXDP2 PEG_HDMI_TXDP2 A8 H3 R9793 150/F_4 APU_RST# 1 3 APU_LDT_RST_HTPA#
GND
(25) INT_HDMI_TXDP2 TDP1_TXP0 DP_ZVSS
(25) INT_HDMI_TXDN2 INT_HDMI_TXDN2 IHM@0.1U/10V_4X C5584 PEG_HDMI_TXDN2 B8 TDP1_TXN0 Q5024 R9796

C5580 DP_BLON G2 R9791 IV@0_4 INT_LVDS_BLON (30) *BSS138_200MA *34.8K/F_4
DP MISC
(25) INT_HDMI_TXDP1 INT_HDMI_TXDP1 IHM@0.1U/10V_4X PEG_HDMI_TXDP1 B9 TDP1_TXP1 DP_DIGON H2 R9795 IV@0_4 INT_LVDS_DIGON (30) C5585
1
(25) INT_HDMI_TXDN1 INT_HDMI_TXDN1 IHM@0.1U/10V_4X C5586 PEG_HDMI_TXDN1 A9 TDP1_TXN1 DP_VARY_BL H1 R9797 IV@0_4 INT_DPST_PWM (30) G7 *0.1U/10V_4X
DISPLAYPORT 1
C5581 R9798 IV@10K/F_4 *SHORT_ PAD1
GND
(25) INT_HDMI_TXDP0 INT_HDMI_TXDP0 IHM@0.1U/10V_4X PEG_HDMI_TXDP0 D10 TDP1_TXP2
(25) INT_HDMI_TXDN0 INT_HDMI_TXDN0 IHM@0.1U/10V_4X C5582 PEG_HDMI_TXDN0 C10 TDP1_TXN2 TDP1_AUXP B2 INT_HDMI_AUXP (25)
2
C5583 TDP1_AUXN C2 INT_HDMI_AUXN (25)
(25) INT_HDMI_TXCP INT_HDMI_TXCP IHM@0.1U/10V_4X PEG_HDMI_TXCP A10 TDP1_TXP3 for debug only
(25) INT_HDMI_TXCN INT_HDMI_TXCN IHM@0.1U/10V_4X C5587 PEG_HDMI_TXCN B10 TDP1_TXN3 TDP1_HPD C1 INT_HDMI_HPD (25) +3V
C5588
(30) INT_LCD_TXLOUT2+ B5 LTDP0_TXP0 LTDP0_AUXP A3 INT_LCD_EDIDCLK INT_LCD_EDIDCLK (30)
(30) INT_LCD_TXLOUT2- A5 LTDP0_TXN0 LTDP0_AUXN B3 INT_LCD_EDIDDATA INT_LCD_EDIDDATA (30)
<20110920_Lincan>
(30) INT_LCD_TXLOUT1+ D6 LTDP0_TXP1 LTDP0_HPD D3 DP0_HPD R9799 *100K_4
PH, isn't installed by default
(30) INT_LCD_TXLOUT1- C6 LTDP0_TXN1
DISPLAYPORT 0
DAC_RED C12 INT_CRT_RED_R R9800 IV@0_4 INT_CRT_RED +3V
(30) INT_LCD_TXLOUT0+
(30) INT_LCD_TXLOUT0-
A6
B6
LTDP0_TXP2
LTDP0_TXN2
DAC_REDB
DAC_GREEN
D13
A12 INT_CRT_GRE_R R9801 IV@0_4 INT_CRT_GRE
INT_CRT_RED
INT_CRT_GRE
(30)
(30)
SMbus
2
DAC_GREENB B12
D8 A13 INT_CRT_BLU_R R9802 IV@0_4 INT_CRT_BLU
(30) INT_LCD_TXLCLKOUT+
C8
LTDP0_TXP3 DAC_BLUE
B13
INT_CRT_BLU (30)
R9803 *0_4 6 1 APU_SIC APU
GND
(30) INT_LCD_TXLCLKOUT- LTDP0_TXN3 DAC_BLUEB (6) SCLK3
Near CPU EMI 0928
V2 CLKIN_H DAC_HSYNC E1 Q9001A
(7) CLK_APU_HCLKP INT_CRT_HSYNC (30)
VGA DAC
V1 CLKIN_L DAC_VSYNC E2 (34) 2ND_MBCLK R9804 0_4 2N7002KDW_115MA
(7) CLK_APU_HCLKN INT_CRT_VSYNC (30)
CLK
(7) CLK_DP_NSSCP D2 DISP_CLKIN_H DAC_SCL F2 INT_CRT_DDCCLK (30) PU 4.7K to +3VPCU in EC
D1 DISP_CLKIN_L DAC_SDA D4 +3V
(7) CLK_DP_NSSCN INT_CRT_DDCDAT (30)
APU_SVC J1 D12 R9805 499/F_4
GND
SVC DAC_ZVSS
APU_SVD J2 SVD
5
TEST4 R1 T5042
SER
<Layout Note> APU_SIC P3 SIC TEST5 R2 T5043
C5589 *0.1U/10V_4X APU_SID P4 SID TEST6 R6 APU_TEST6_DIRECRACKMON T5044 (6) SDATA3 R9806 *0_4 3 4 APU_SID
Close to APU APU_BP0_TSTCLK_USCLK0 T5045
T5
(7) APU_RST#
APU_RST# R9807 0_4 APU_LDT_RST#_R T3 RESET_L
TEST14
TEST15 E4 T5046 Q9001B APU
R9808 0_4 APU_PWRGD_R T4 PWROK TEST16 K4 APU_BP2_SCANSHIFTEN_USDATA0 T5047 (34) 2ND_MBDATA R9809 0_4 2N7002KDW_115MA
(7) APU_PWRGD
TEST17 L1 APU_BP3_SCANSHIFTEND_USDATA1 T5048
APU_PROCHOT#_VDDIO U1 L2 TEST18 R9810 1K/F_4 PU 4.7K to +3VPCU in EC
CTRL
PROCHOT_L TEST18
C5590 APU_THERMTRIP_L# U2 M2 TEST19 R9811 1K/F_4 TEST25_H T5049
GND
THERMTRIP_L TEST19
APU_ALERT# T2 ALERT_L TEST25_H K1 TEST25_H R9812 510/F_4 TEST25_L T5050
*IV@1000P/16V_4X TEST25_L K2 TEST25_L R9813 510/F_4 (8) APU_TALERT# R9814 0_4 APU_ALERT#
TEST
+1.8V
UMA boot issue 1027 B2A APU_TDI N2 TDI TEST28_H L5 APU_TEST28_H_PLLCHARZ T5051
APU_TDO N1 TDO TEST28_L M5 APU_TEST28_L_PLLCHARZ T5052
APU_TCK P1 TCK TEST31 M21 APU_TEST31_MEM_TEST T5053
APU_TMS P2 J18 APU_TEST33_H_M_CLKTST_H C5591 0.1U/10V_4X R9815 51/F_4
JTAG
TMS TEST33_H
APU_TRST# M4 J19 APU_TEST33_H_M_CLKTST_L C5592 0.1U/10V_4X R9816 51/F_4
GND
UNNAMED_7_CAP_I337_B
TRST_L TEST33_L
APU_DBRDY M3 DBRDY TEST34_H U15 APU_TEST34_H_TSTCLKIN_H T5054
APU_DBREQ# M1 DBREQ_L TEST34_L T15 APU_TEST34_L_TSTCLKIN_L T5055
H4 R9817 *1K/F_4
GND
TEST35
(41) CPU_VDDNB_FB_H R9818 0_4 VDDCR_NB_SENSE F4 VDDCR_NB_SENSE TEST36 N5 APU_TEST36 T5056

(41) CPU_VDD_FB_H R9819 0_4 VDDCR_CPU_SENSE G1 VDDCR_CPU_SENSE TEST37 R5 APU_TEST37_GIO_TSTDTM0_CLKINIT T5057
VDDIO_MEM_S_SENSE F3 VDDIO_MEM_S_SENSE
(41) CPU_VDDNB_FB_L R9820 0_4 F1 VSS_SENSE
(41) CPU_VDD_FB_L R9821 0_4 B4 RSVD_1

TEST38
DMAACTIVE_L
K3
T1
APU_FDO
ON_DMAACTIVE# R9822 0_4
T5058
DMAACTIVE_L (7)
HDT(Hardware Debug Tool ) Connector
W11 RSVD_2
ONTARIO (2.0)
AMD FAE suggest connect to voltage regulator V5 RSVD_3
+1.8V
PART 3 OF 5
<Layout Note> R9824
FT1_ONTARIO R9823 1K/F_4 +1.8V
DIFFERENTIAL ROUTING
1K/F_4
CN24
+1.8V
R9825 1 2 APU_TCK R9826 1K/F_4
1K/F_4 3 4 APU_TMS R9827 1K/F_4
T5059 VDDCR_NB_SENSE 5 6 APU_TDI R9828 1K/F_4
T5060 VDDCR_CPU_SENSE 7 8 APU_TDO
VDDIO_MEM_S_SENSE R9829 0_4 APU_TRST# 9 10 APU_PWRGD_R +1.8V
T5061
R9830 *10K/F_4 11 12 APU_LDT_RST#_R
<Layout Note> R9831 *10K/F_4 13 14 APU_DBRDY
R9832 *10K/F_4 15 16 APU_DBREQ# R9833 1K/F_4
close to CPU R9834 *0_4 TEST19
17 18
19 20 R9835 *0_4 TEST18
*HDR10X2_DEBUG
<20110905_Lincan>
A A
choose the 1k ohm
Thermal Management Signals +3V
Serial VID
PV stage:add +1.5VSUS option
R540 R541 for Caspian CPU
SI Change from AMD request power leakge issue
3
2 CPU_COREPG (10,41)
R9836 1K/F_4
VFIX MODE VID Override Circuit
+1.8V
Q9002
2N7002K_300MA SVC SVD Voltage Output
+1.8V R9839 1K/F_4
1
R9840 100K_4
0 0 1.1V
R9841 R9842 0 1 1.0V
APU_PROCHOT#_VDDIO R9838 1K_4 APU_SVC R9843 0_4 CPU_SVC
,34) APU_PROCHOT#_VDDIO +3V 1K_4 1K_4
APU_SVD R9844 0_4 CPU_SVD
CPU_SVC (41) 1 0 0.9V
APU_PWRGD R9845 0_4 CPU_PWRGD_SVID_REG
CPU_SVD (41) TO POWER IC
CPU_PWRGD_SVID_REG (41) 1 1 0.8V
2
R9846 *220_4
R9847 *220_4
APU_THERMTRIP_L# 1 3 R9849 0_6 SYS_SHDN# R9848 *220_4
SYS_SHDN# (14,37)
Q9004
METR3904-G_200MA
To indicate SVI interface is active

+3V
R9850
*10K_4 +3V
CPU Thermal sensor HW control (near CPU)
2
R9852 1K/F_4 APU_ALERT#

PU 10K to +3V_S5 in FCH
1 3 R9851 *0_6 R9853 1K/F_4 APU_SIC +3VPCU +3VPCU +3VPCU
APU_THERMTRIP# (6)
Q9006
*METR3904-G_200MA R9854 1K/F_4 APU_SID
+1.8V
R9855 R9856 R9857
U5039 470K_4
+3VPCU R9858 150_4 +3VPCU_HW_SD 5 1 R9859 34K/F_4 *10K_4 *330_4
VCC SET
C5593 2
GND
2
R9860 300/F_4 APU_RST#
0.1U/16V_4Y
R9861 300/F_4 APU_PWRGD 4 3 THER_SHD# 1 3 SYS_SHDN#
HYST OT# Q9005 *METR3904-G_200MA
R9862 1K/F_4 APU_TEST36 G708T1U
Rset(Kohm)=0.0012T*T-0.9308T+96.147,Shut down on R9863 0_4
73degree <C3B_20120321>
+3V Hysteresis is 30C change R9859 to 34K ohm for thermal
(Thermal shutdown temperature: UMA is 73 degree, DIS is 74degree)
INT_LCD_EDIDCLK R9864 *IV@2.2K_4
INT_LCD_EDIDDATA R9865 *IV@2.2K_4
INT_CRT_RED R9866 IV@150/F_4

INT_CRT_GRE R9867 IV@150/F_4
INT_CRT_BLU R9868 IV@150/F_4
PROJECT :BY7D
1A
ONTATIO DISPLAY/CLK/MI(2/3)
1
1
CPU_CORE
U5038C
VDD_18
<B3A_20120202>
change to short pad
R9869 *0/short_8 CPU_CORE CPU_CORE CPU_CORE

05
11A E5 VDDCR_CPU_1 VDD_18_1 U8 +1.8V 2A
E6 VDDCR_CPU_2 VDD_18_2 W8
F5 VDDCR_CPU_3 VDD_18_3 U6 C5595 C5597 C5599
F7 VDDCR_CPU_4 VDD_18_4 U9 1U/6.3V_4X 10U/6.3V_8X 1U/6.3V_4X C5600 C5601 C5602
G6 VDDCR_CPU_5 VDD_18_5 W6
G8 VDDCR_CPU_6 VDD_18_6 T7 C5594 C5596 C5598 1U/6.3V_4X *10U/6.3V_8X *10U/6.3V_8X 1U/6.3V_4X 1U/6.3V_4X
H5 VDDCR_CPU_7 VDD_18_7 V7 1U/6.3V_4X 0.1U/10V_4X 0.1U/10V_4X 20110915 Add 10U/6.3V_8X 10U/6.3V_8X 10U/6.3V_8X C5611 C5613 C700 C701
H7 VDDCR_CPU_8 C5603 C5604 C5605 C5606 C5607 C5608 C5609 C5610 C5612
(for BY5 layout) 1U/6.3V_4X ESD@39P/50V_4N ESD@39P/50V_4N
J6 VDDCR_CPU_9 10U/6.3V_8X 10U/6.3V_8X 10U/6.3V_8X 10U/6.3V_8X 1U/6.3V_4X
J8 VDDCR_CPU_10 <C3B_20120306>
L7 VDDCR_CPU_11
reserve for ESD
M6 VDDCR_CPU_12
M8 VDDCR_CPU_13
N7 VDDCR_CPU_14 <B3A_20120202>
R8 VDDCR_CPU_15
change to short pad CPU_CORE CPU_VDDNB_CORE CPU_VDDNB_CORE
CPU_VDDNB_CORE
+1.8V
VDDAN_18_DAC R9870 *0/short_6
10A E8 VDDCR_NB_1 VDD_18_DAC W9 150mA
E11 VDDCR_NB_2
E13 VDDCR_NB_3
F9 VDDCR_NB_4 1U/6.3V_4X 1U/6.3V_4X C703 C702
ONTARIO (2.0)
F12 VDDCR_NB_5 C5624 C5629 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X C5622 C5625 C5627
PART 4 OF 5
G11 VDDCR_NB_6 10U/6.3V_8X 1U/6.3V_4X C5614 C5615 C5616 C5617 C5618 C5619 C5620 C5621 C5623 C5626 C5628 ESD@39P/50V_4N ESD@39P/50V_4N
G13 VDDCR_NB_7 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X
H9 VDDCR_NB_8 <B3A_20120202>
H12 VDDCR_NB_9
change to short pad
K11 VDDCR_NB_10 T5062
K13 VDDCR_NB_11
+1.0V
VDDPL_10 R9871 *0/short_6
POWER
L10 VDDCR_NB_12 VDDPL_10 U11 200mA CPU_VDDNB_CORE
L12 VDDCR_NB_13
L14 VDDCR_NB_14
CPU_VDDNB_CORE +1.8V
M11 VDDCR_NB_15
M12 VDDCR_NB_16 C5630 C5631 C5632
M13 VDDCR_NB_17 10U/6.3V_8X 0.1U/10V_4X 1U/6.3V_4X
N10 VDDCR_NB_18
N12 VDDCR_NB_19
VDD_10 +1.0V 10U/6.3V_8X 10U/6.3V_8X C718 C719
N14 VDDCR_NB_20 C5633 C5634 C5635 C5636 C5637 C5638 C5639
P11 VDDCR_NB_21 5.5A 10U/6.3V_8X 10U/6.3V_8X 10U/6.3V_8X *220P/50V_4X *220P/50V_4X ESD@39P/50V_4N ESD@39P/50V_4N
P13 VDDCR_NB_22 VDD_10_1 U13 R9872 *0/short_6
VDD_10_2 W13
VDD_10_3 V12 0.1U/10V_4X 0.1U/10V_4X R9873 *0/short_6
+1.5VSUS G16 VDDIO_MEM_S_1 VDD_10_4 T12 C5642 C5644 EMI 1206
2A G19 VDDIO_MEM_S_2 C5641 C5643 C5645 R9874 *0/short_6
E17 VDDIO_MEM_S_3 C5640 10U/6.3V_8X 1U/6.3V_4X 1U/6.3V_4X CPU_VDDNB_CORE
10U/6.3V_8X +1.0V
J16 VDDIO_MEM_S_4 <B3A_20120202>
L16 VDDIO_MEM_S_5
change to short pad
L19 VDDIO_MEM_S_6
N16 VDDIO_MEM_S_7
R16 VDDIO_MEM_S_8
R19 VDDIO_MEM_S_9 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X C5654 C720 C721
W18 VDDIO_MEM_S_10
+3V C5646 C5647 C5648 C5649 C5650 C5651 C5652 C5653
0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X ESD@39P/50V_4N ESD@39P/50V_4N
U16 VDDIO_MEM_S_11 VDD_33 A4 500mA
C5655
FT1_ONTARIO <C3B_20120307>
1U/6.3V_4X
reserve for ESD
GND
+1.5VSUS
+1.5VSUS +1.5VSUS
1U/6.3V_4X 1U/6.3V_4X 10U/6.3V_8X C706 C704 C707 C711 C712

C5659 C5661 C5656 C5657
C5658 C5660 10U/6.3V_8X ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N
1U/6.3V_4X 1U/6.3V_4X
A A
U5038D
+1.5VSUS +1.5VSUS
A7 VSS_1 ONTARIO (2.0) VSS_50 N13
B7 VSS_2 PART 5 OF 5 VSS_51 N20
B11 VSS_3 VSS_52 N22
B17 VSS_4 VSS_53 P10
B22 VSS_5 VSS_54 P14
C4 VSS_6 VSS_55 R4 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X C5670 C713 C714 C715 C716
D5 VSS_7 VSS_56 R7 C5662 C5663 C5664 C5665 C5666 C5667 C5668 C5669
D7 VSS_8 VSS_57 R20 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N
D9 VSS_9 VSS_58 T6
D11 VSS_10 VSS_59 T9
D14 VSS_11 VSS_60 T11 <C3B_20120306>
B15 VSS_12 VSS_61 T13 reserve for ESD
D17 VSS_13 VSS_62 U4
D19 VSS_14 VSS_63 U5
E7
E9
VSS_15
VSS_16
VSS_64
VSS_65
U7
U12
EMC CAPS place capacitors under BGA
E12 VSS_17 VSS_66 U20
E20 VSS_18 VSS_67 U22
F8 VSS_19 VSS_68 V8 +1.5VSUS CPU_CORE CPU_VDDNB_CORE +1.5VSUS
F11 VSS_20 VSS_69 V9
F13 VSS_21 VSS_70 V11
G4 VSS_22 VSS_71 V13
G5 VSS_23 VSS_72 W1
G7 VSS_24 VSS_73 W2
G9 VSS_25 VSS_74 W4 0.1U/10V_4X C5678
GROUND
G12 VSS_26 VSS_75 W5 C5671 C5672 C5673 C5674 C5675 C5676 C5677
G20 VSS_27 VSS_76 W7 180P/50V_4N 180P/50V_4N180P/50V_4N 180P/50V_4N180P/50V_4N 180P/50V_4N 0.1U/10V_4X
G22 VSS_28 VSS_77 W12
H6 VSS_29 VSS_78 W20
H11 VSS_30 VSS_79 Y5
H13 VSS_31 VSS_80 Y7
J4 VSS_32 VSS_81 Y9 VDD_18 VDDAN_18_DAC VDD_10 VDDPL_10 +3V
J5 VSS_33 VSS_82 Y11
J7 VSS_34 VSS_83 Y13
J20 VSS_35 VSS_84 Y15
K10 VSS_36 VSS_85 Y17
K14 VSS_37 VSS_86 Y19
L4 VSS_38 VSS_87 AA4 C5684
L6 VSS_39 VSS_88 AA22 C5679 C5680 C5681 C5682 C5683
L8 VSS_40 VSS_89 AB2 180P/50V_4N 180P/50V_4N 180P/50V_4N 180P/50V_4N 180P/50V_4N 0.1U/10V_4X
L11 VSS_41 VSS_90 AB5
M7 VSS_45 VSS_94 AB21
N4 VSS_46 VSS_95 AC5
N11 VSS_49 VSSBG_DAC A11
FT1_ONTARIO
GND
GND

PROJECT : BY7D
1A
ONTARIO POWER & DECOUP(3/3)
1
5 4 3 2 1
Note :
06
PCIE_RST2# asserted during transition to S3/S4/S5
to reset PCIE devices in the FCH
+3V_S5 For LAN,WLAN R678 33_4
(26,28) FCH_PCIE_RST#
NC,no install by default
C844
R383 *2.2K_4 FCH_TEST0 1 2
(7,28,29,34) PLTRST#
D43 150P/50V_4N
B130LAW-7-F_1A
R382 *2.2K_4 FCH_TEST1 R438 *0_4 U3A
PCIE_RST2# AB6 G8
GEVENT22# PCIE_RST2#/GEVENT4# USBCLK/14M_25M_48M_OSC
T84 R2 RI#/GEVENT22#
R344 *2.2K_4 FCH_TEST2 GEVENT21# W7 B9 USB_RCOMP_SB R647 11.8K/F_6
T77 SLP_S3# SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP
(34) SLP_S3# T3 SLP_S3#
SLP_S5# W2 H1
MISC
(34) SLP_S5# SLP_S5# USB_FSD1P/GPIO186 T157
USB
D DNBSWON# R682 0_4 PWR_BTN# J4 H3 D
(34) DNBSWON# PWR_BTN# USB_FSD1N T156
FCH_PWRGD
+3V For Dimm (10) FCH_PWRGD N7 PWR_GOOD HUDSON-M3 USB_FSD0P/GPIO185 H6 T159
FCH_TEST0 T9 Part 4 of 5 H5
TEST0 USB_FSD0N T158
R272 2.2K_4 SMB_RUN_CLK FCH_TEST1 T10
USB
T95 TEST1/TMS
1.1
ACPI / WAKE UP
FCH_TEST2 V9 H10
R270 2.2K_4 SMB_RUN_DAT EC_A20GATE TEST2 USB_HSD13P
AE22 G10
(34) EC_A20GATE
(34) EC_KBRST#
EC_KBRST# AG19
GA20IN/GEVENT0#
KBRST#/GEVENT1#
USB_HSD13N HUB3
R271 *10K_4 GPIO65 EC_EXT_SCI# R9 K10
EVENTS
(34) EC_EXT_SCI# PME#/GEVENT3# USB_HSD12P
GEVENT23# C26 J12
T100 LPC_SMI#/GEVENT23# USB_HSD12N
CLK_REQG# Not Implemented: leave unconnected (34) LPCPD# T5 LPC_PD#/GEVENT5#
SYS_RST# U4 G12 USBP11+ USBP11+ (24) Reserve USB2.0/3.0 option Note :
PCIE_WAKE# SYS_RESET#/GEVENT19# USB_HSD11P USBP11-
(26,28) PCIE_WAKE# K1 F12 USBP11- (24) USB 2.0 and USB 3.0 signal pair combinations to a single USB 3.0 connector:
GEVENT20# V7
WAKE#/GEVENT8# USB_HSD11N (Left Up)
+3V_S5 For Lan&WiFi (4) APU_THERMTRIP#
C379
T80
33P/50V_4N R288
APU_THERMTRIP#
10K/F_4 WD_PWRGD
R10
IR_RX1/GEVENT20#
THRMTRIP#/SMBALERT#/GEVENT2# USB_HSD10P
K12 USBP10+
USBP10-
USBP10+ (24)
‧ USB_SS_T /R 1P/N and USB_HSD11P/N
‧ USB_SS_T /R 0P/N and USB_HSD10P/N
+3V AF19 WD_PWRGD USB_HSD10N K13 USBP10- (24) USB3.0 S&C (Right)
R396 2.2K_4 SMB_LAN_CLK
R430 0_4 RSMRST# U2 B11
(34) RSMRST_GATE# RSMRST# USB_HSD9P
R384 2.2K_4 SMB_LAN_DAT R432 22K_4 D11 <Layout Note>
USB_HSD9N
AG24 CLK_REQ4#/SATA_IS0#/GPIO64 USB P/N pairs with trace lengths up to 10"
Note: FCH_PCIE_LAN_CLKREQ# AE24 E10
(26) FCH_PCIE_LAN_CLKREQ# CLK_REQ3#/SATA_IS1#/GPIO63 USB_HSD8P
<B3A_20120130> BOARD_ID8 AE26 F10
SCL0/SDA0: for SMBUS in the S0 power domain (8) BOARD_ID8
BOARD_ID9 SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD8N
add for EMI (BOT: -9090, 5240) (8) BOARD_ID9 AF22 CLK_REQ0#/SATA_IS3#/GPIO60
SCL1/SDA1: for SMBUS in the S5 power domain AH17 C10 USBP7+
SATA_IS4#/FANOUT3/GPIO55 USB_HSD7P USBP7+ (28)
AG18 A10 USBP7- WLAN
+3V_S5 SMB_LAN_CLK
(27) PCBEEP
PCBEEP AF24
SATA_IS5#/FANIN3/GPIO59
SPKR/GPIO66
USB_HSD7N USBP7- (28) HUB2
SMB_RUN_CLK AD26 H9 USBP6+_LCD USBP6+_LCD (30)
(11,12,33) SMB_RUN_CLK SCL0/GPIO43 USB_HSD6P
R685 10K_4 APU_THERMTRIP# C601 SMB_RUN_DAT AD25 G9 USBP6-_LCD USBP6-_LCD (30) CCD on LVDS
USB
(11,12,33) SMB_RUN_DAT SDA0/GPIO47 USB_HSD6N
R368 10K_4 USB_SC_OC# SMB_LAN_CLK
2.0
(26,28) SMB_LAN_CLK T7 SCL1/GPIO227
R374 10K_4 USB_NORMAL_OC# E@2200P/50V_4X SMB_LAN_DAT R7 A8 USBP5+ USBP5+ (29)
(26,28) SMB_LAN_DAT SDA1/GPIO228 USB_HSD5P
R377 10K_4 FCH_JTAG_TCK GPIO62 AG25 C8 USBP5- USBP5- (29) Card Reader
T34 CLK_REQ2#/FANIN4/GPIO62 USB_HSD5N
FCH_PCIE_WLAN_CLKREQ# AG22
GPIO
(28) FCH_PCIE_WLAN_CLKREQ# CLK_REQ1#/FANOUT4/GPIO61
J2 IR_LED#/LLB#/GPIO184 USB_HSD4P F8
+3V_S5 GPIO51 AG26 E8
T29 SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD4N
V8 DDR3_RST#/GEVENT7#/VGA_PD
R407 10K_4 PCIE_WAKE# W8 C6
R375 2.2K_4 PWR_BTN# SPI_HOLD# GBE_LED0/GPIO183 USB_HSD3P
(8) SPI_HOLD# Y6 SPI_HOLD#/GBE_LED1/GEVENT9# USB_HSD3N A6
C V10 C
GBE_LED2/GEVENT10# USBP2+
Note: Note: M3L doesn't have VGA_PD function AA8 C5
LLB#, WAKE# and PWR_BTN need pull up to Note : GPIO65 AF25
GBE_STAT0/GEVENT11#
CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#
USB_HSD2P
USB_HSD2N
A5 USBP2-
T170
T171
HUB1
+3VPCU only if S5+ mode is supported GPIO[48:65] integrated PU 8.2K to +3V
C1
FCH_BLINK USB_HSD1P
Note : T81 M7 BLINK/USB_OC7#/GEVENT18# USB_HSD1N C3
GEVENT6# R8
Gevent[12:18]# integrated PU 10K to +3V_S5 T79
GEVENT17# USB_OC6#/IR_TX1/GEVENT6# USBP0+
(Integrated PU is not supported when the pin T83 T1 USB_OC5#/IR_TX0/GEVENT17# USB_HSD0P E1 USBP0+ (24) USB2.0 debug port
GEVENT16# P6 E3 USBP0- USBP0- (24)
T86 USB_OC4#/IR_RX0/GEVENT16# USB_HSD0N (Left Down)
is configured for USB over current function) FCH_JTAG_TDO F5
T87 USB_OC3#/AC_PRES/TDO/GEVENT15#
FCH_JTAG_TCK FCH_JTAG_TCK P5 C16 USBSS_CALRP R646 U3@1K/F_4
T92
USB
FCH_JTAG_TDI USB_SC_OC# R711 *0_4 FCH_JTAG_TDI USB_OC2#/TCK/GEVENT14# USBSS_CALRP USBSS_CALRN R642 U3@1K/F_4
OC
T93 (24,34) USB_SC_OC# J7 A16 +FCH_VDD_11_SSUSB_S
FCH_JTAG_RST# USB_NORMAL_OC# R710 *0_4 FCH_JTAG_RST# USB_OC1#/TDI/GEVENT13# USBSS_CALRN
T94 (24,34) USB_NORMAL_OC# T8 USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12#
A14
USB_SS_TX3P
C14
USB_SS_TX3N
ACZ_BCLK_R AB3 C12
ACZ_SDOUT_R AZ_BITCLK USB_SS_RX3P
AB1
AZ_SDOUT USB_SS_RX3N
A12 USB_SS_TX/RX[3,2]P/N,USB_HSD[13, 12, 9, 4]P/N,USB_FSD[1,0]P/N
5 6 ACZ_SDIN0 AA2
ACZ_SDIN1 AZ_SDIN0/GPIO167 signal pairs do not exist on Hudson-M3L/D3L
4 7 Y5 D15
ACZ_SDIN2_R AZ_SDIN1/GPIO168 USB_SS_TX2P
3 8 Y3 B15
ACZ_SDIN3_R AZ_SDIN2/GPIO169 USB_SS_TX2N
2 9 Y1 AZ_SDIN3/GPIO170
1 10 ACZ_SYNC_R AD6 E14
ACZ_RST#_R AZ_SYNC USB_SS_RX2P
AE4 F14
To Azalia HDaudio interface are +3V_S5 R734 *10KX8 AZ_RST# USB_SS_RX2N
USB
F15 USB3_TXP1
AUDIO
USB3_TXP1 (24)
3.0
T65 USB_SS_TX1P
(8,33) BOARD_ID10 K19 G15 USB3_TXN1
PS2_DAT/SDA4/GPIO187 USB_SS_TX1N USB3_TXN1 (24)
HD
ACZ_SDOUT R392 33_4 ACZ_SDOUT_R J19 USB3.0 Port 2
(27) ACZ_SDOUT T42 PS2_CLK/CEC/SCL4/GPIO188
J21 H13 USB3_RXP1 USB3_RXP1 (24)
ACZ_SYNC R391 33_4 ACZ_SYNC_R SPI_CS2#/GBE_STAT2/GPIO166 USB_SS_RX1P USB3_RXN1
(27) ACZ_SYNC USB_SS_RX1N G13 USB3_RXN1 (24)
ACZ_BITCLK R406 33_4 ACZ_BCLK_R D21 J16 USB3_TXP0
(27) ACZ_BITCLK PS2KB_DAT/GPIO189 USB_SS_TX0P USB3_TXP0 (24)
C20 H16 USB3_TXN0 USB3_TXN0 (24)
C571 *22P/50V_4N PS2KB_CLK/GPIO190 USB_SS_TX0N
D23 PS2M_DAT/GPIO191 USB3.0 S&C
C22 J15 USB3_RXP0 USB3_RXP0 (24)
ACZ_RST# R357 33_4 ACZ_RST#_R PS2M_CLK/GPIO192 USB_SS_RX0P USB3_RXN0
(27) ACZ_RST# K15 USB3_RXN0 (24)
USB_SS_RX0N
B (27) ACZ_SDIN0 ACZ_SDIN0 F21 Note: B
T66 KSO_0/GPIO209
E20 H19 SMB_EC_CLK R318 *0_4 MBCLK
T67 KSO_1/GPIO210 SCL2/GPIO193 SMB_EC_DAT R315 *0_4 MBDATA
MBCLK (34,36) SCL2/SDA2: for SMBUS in the S5 power domain
T68 F20 G19 MBDATA (34,36)
KSO_2/GPIO211 SDA2/GPIO194 SCLK3 SCL3/SDA3: for SMBUS in the S5 power domain
T69 A22 G22 SCLK3 (4)
KSO_3/GPIO212 SCL3_LV/GPIO195 SDATA3
T71 T70 E18 G21 SDATA3 (4)
KSO_5 KSO_4/GPIO213 SDA3_LV/GPIO196
A20 E22
KSO_5/GPIO214 EC_PWM0/EC_TIMER0/GPIO197 R15 0_4 R599 10K_4 SMB_EC_CLK
T72 J18 H22 +3V_S5
KSO_6/GPIO215 EC_PWM1/EC_TIMER1/GPIO198 EC_PWM2
T73 H18 J22 EC_PWM2 (10)
KSO_7/GPIO216 EC_PWM2/EC_TIMER2/WOL_EN/GPIO199 R600 10K_4 SMB_EC_DAT
T74 G18 H21
KSO_8/GPIO217 EC_PWM3/EC_TIMER3/GPIO200
T75 B21
KSO_9/GPIO218
T76 K18 K21
KSO_10/GPIO219 EMBEDDED KSI_0/GPIO201 R14 0_4 R593 10K_4 SCLK3
T78 D19 KSO_11/GPIO220 KSI_1/GPIO202 K22 +3V_S5
T82 A18 CTRL F22
KSO_12/GPIO221 KSI_2/GPIO203 R594 *0_4 R595 10K_4 SDATA3
T85 C18 F24 +3V
KSO_13/GPIO222 KSI_3/GPIO204
T88 B19 E24
KSO_14/XDB0/GPIO223 KSI_4/GPIO205
T89 B17 B23
T90 A24
C24 SCL2/SDA2:
T91 D17 F18 SMBUS Implemented: PU 2.2K to +3V_S5
KSO_[17:0] provided test points (follow checklist) SMBUS Not Implemented: PU 10K to +3V_S5
SCL3/SDA3:
Low Voltage SMBUS Implemented: PU 10K to APU_VDDIO (+3V)
Hudson-M3
+3V_S5 Low Voltage SMBUS Not Implemented: PU 10K to +3V_S5
R662
10K_4
EC will Conflict with FCH, did not mount R315&R318

2 1 SYS_RST#
G2 *SHORT_PAD EC FCH Device I2C_Device(S)
I2Ce_1(M) I2Cf_2(M) Charger Battery ALL/S5

A A
+3V_S5
I2Ce_2(M) EEPROM APU ALL
I2Ce_3(M) VGA Thermal

R286
*10K_4 I2Cf_3(M) APU S5
2 1 KSO_5 I2Cf_1(M) Lan WLan S5 Quanta Computer Inc.

G5 *SHORT_PAD
I2Cf_0(M) Dimm Clk Gen S0 PROJECT :BY7D
1A
FCH 1/5(GPIO/USB/AZ)
5 4 3 2 1
5 4 3 2 1
07
APU_PCIE_RST# IS FOR PCIE DEVICES ON APU
+3V
Note : C5559 EV@0.1U/10V_4X

PCIE_RST# asserted during transition to S3/S4/S5
5
to reset PCIE devices in the APU For GPU APU_PCIE_RST# R670 33_4 U5034
A_RST# asserted during transition to S3/S4/S5 GPU_RST# 2
C843 4 PERST#_BUF
to reset all devices in the FCH or connected to it, U3E APU_PCIE_RST# PERST#_BUF (13)
1
except the ACPI logic in the FCH. C842 150P/50V_4N 150P/50V_4N
*EV@TC7SH08FU(F)
HUDSON-M3
3
PCIE_RST#_R AE2 AF3
PLTRST# R669 33_4 A_RST# PCIE_RST# PCICLK0 PCI_CLK1_R R434 0_4 PCI_CLK1
For LPC devices,Card reader (6,28,29,34) PLTRST# AD5
A_RST# Part 1 of 5 PCICLK1/GPO36
AF1 PCI_CLK1 (10)
D AF5 D
UMI_RXP0 C767 0.1U/10V_4X UMI_RXP0_C PCICLK2/GPO37 PCI_CLK3_R R436 0_4 PCI_CLK3
(3) UMI_RXP0 AE30 AG2 PCI_CLK3 (10)
UMI_RXN0 C764 0.1U/10V_4X UMI_RXN0_C UMI_TX0P PCICLK3/GPO38 PCI_CLK4_R R433 0_4 PCI_CLK4 R365 EV@0_4
(3) UMI_RXN0 AE32 AF6 PCI_CLK4 (10)
UMI_RXP1 C765 0.1U/10V_4X UMI_RXP1_C UMI_TX0N PCICLK4/14M_OSC/GPO39
(3) UMI_RXP1 AD33
CLKS
UMI_RXN1 C766 0.1U/10V_4X UMI_RXN1_C UMI_TX1P
AD31 AB5
PCI
(3) UMI_RXN1 UMI_TX1N PCIRST# T135
UMI_RXP2 C770 0.1U/10V_4X UMI_RXP2_C AD28
(3) UMI_RXP2 UMI_TX2P
UMI_RXN2 C771 0.1U/10V_4X UMI_RXN2_C AD29
(3) UMI_RXN2 UMI_TX2N
UMI_RXP3 C773 0.1U/10V_4X UMI_RXP3_C AC30 AJ3
(3) UMI_RXP3 UMI_TX3P AD0/GPIO0
UMI_RXN3 C774 0.1U/10V_4X UMI_RXN3_C AC32 AL5 <B3A_20120206>
(3) UMI_RXN3 UMI_TX3N AD1/GPIO1
AG4 change to short pad
UMI_TXP0 AD2/GPIO2 D37
(3) UMI_TXP0 AB33 AL6
UMI_TXN0 UMI_RX0P AD3/GPIO3 *RB500V-40_100MA
(3) UMI_TXN0 AB31 AH3
UMI_TXP1 UMI_RX0N AD4/GPIO4 R681 *0/short_6
(3) UMI_TXP1 AB28 AJ5 1 2 +3VPCU
UMI_TXN1 UMI_RX1P AD5/GPIO5
(3) UMI_TXN1 AB29 AL1
UMI_TXP2 UMI_RX1N AD6/GPIO6
Y33 AN5
(3)
(3)
UMI_TXP2
UMI_TXN2
UMI_TXN2
UMI_TXP3
Y31
UMI_RX2P
UMI_RX2N
AD7/GPIO7
AD8/GPIO8
AN6 RTC Circuitry(RTC)
(3) UMI_TXP3 Y28 AJ1 D27
UMI_TXN3 UMI_RX3P AD9/GPIO9 BAT54C-7-F_200MA
(3) UMI_TXN3 Y29 AL8
PCI EXPRESS
UMI_RX3N AD10/GPIO10
INTERFACES
AL3 +3V_RTC +3VRTC
R275 590/F_4 PCIE_CALRP AD11/GPIO11
AF29 AM7
R276 2K/F_4 PCIE_CALRN PCIE_CALRP AD12/GPIO12
AF31 AJ6
+1.1V_PCIE_VDDR PCIE_CALRN AD13/GPIO13
AK7 20MIL R655 510/F_6 +3VRTC 1 2 +VCCRTC_2
0.1U/10V_4X C709 PCIE_TXP_WLAN_C AD14/GPIO14
(28) PCIE_TXP_WLAN V33 AN8
0.1U/10V_4X C710 PCIE_TXN_WLAN_C GPP_TX0P AD15/GPIO15 D38
To WLAN (28) PCIE_TXN_WLAN V31
GPP_TX0N AD16/GPIO16
AG9
20MIL
W30 AM11 *RB500V-40_100MA
GPP_TX1P AD17/GPIO17 C537
W32 AJ10
0.1U/10V_4X C705 PCIE_TXP_LAN_C GPP_TX1N AD18/GPIO18 +3V
(26) PCIE_TXP_LAN AB26 AL12
0.1U/10V_4X C708 PCIE_TXN_LAN_C GPP_TX2P AD19/GPIO19 1U/10V_4X
To LAN (26) PCIE_TXN_LAN AB27
GPP_TX2N AD20/GPIO20
AK11
20MIL
AA24 AN12 GPU_RST#
GPP_TX3P AD21/GPIO21
AA23 AG12
GPP_TX3N AD22/GPIO22 PCI_AD23 R680
AE12 PCI_AD23 (10)
PCIE_RXP_WLAN AD23/GPIO23 PCI_AD24 R428
(28) PCIE_RXP_WLAN AA27 AC12 PCI_AD24 (10)
PCIE_RXN_WLAN GPP_RX0P AD24/GPIO24 PCI_AD25 *2.2K_4 1K/F_4
From WLAN (28) PCIE_RXN_WLAN AA26
GPP_RX0N AD25/GPIO25
AE13 PCI_AD25 (10)
W27 AF13 PCI_AD26
GPP_RX1P AD26/GPIO26 PCI_AD26 (10)
V27 AH13 PCI_AD27
+BAT
GPP_RX1N AD27/GPIO27 PCI_AD27 (10)
INTERFACE
PCIE_RXP_LAN V26 AH14 R435 *0_4 GFXPG_1V_EN
From LAN
(26) PCIE_RXP_LAN
(26) PCIE_RXN_LAN
PCIE_RXN_LAN W26
GPP_RX2P AD28/GPIO28
AD15 HUDSON_MEMHOT# GFXPG_1V_EN (34,39,42) 20MIL
C W24 AC15 C
GPP_RX3P AD30/GPIO30
W23 AE16 +BAT
PCI
AN3
CBE0#
AJ8
CBE1#
AN10
CBE2#
1
R274 2K/F_4 CLK_CALRN F27 AD12
+1.1V_CKVDD CLK_CALRN CBE3#
FRAME#
AG10 Net GPIO I/O Power Well DOS
AK9
INT_CLK_FCH_SRCP DEVSEL# CN21
TP62 G30 AL10
INT_CLK_FCH_SRCN PCIE_RCLKP IRDY#
TP63 G28
PCIE_RCLKN TRDY#
AF10 GFXPG_1V_EN GPIO28 DGPU_PWRGD I +3.3V "0->1"
AE10 50273-0027N-001
CLK_DP_NSSCP PAR
(4) CLK_DP_NSSCP RP22 2 1 0X2 INT_CLK_DP_NSSCP R26 AH1
2
CLK_DP_NSSCN INT_CLK_DP_NSSCN DISP_CLKP STOP#
To CPU (4) CLK_DP_NSSCN 4 3 T26
DISP_CLKN PERR#
AM9 PE_GPIO0 GPIO44 DGPU_RST# O +3.3V "0->1"
AH8
SERR#
H33 AG15
DISP2_CLKP REQ0#
H31
DISP2_CLKN REQ1#/GPIO40
AG13 PE_GPIO1 GPIO45 DGPU_PWREN O +3.3V "0->1"
AF15
CLK_APU_HCLKP REQ2#/CLK_REQ8#/GPIO41
(4) CLK_APU_HCLKP RP20 2 1 0X2 INT_CLK_APU_HCLKP T24 AM17 T40
CLK_APU_HCLKN INT_CLK_APU_HCLKN APU_CLKP REQ3#/CLK_REQ5#/GPIO42
To CPU (4) CLK_APU_HCLKN 4 3 T23
APU_CLKN GNT0#
AD16
AD13
CLK_PCIE_VGAP GNT1#/GPO44
(13) CLK_PCIE_VGAP RP23 2 1 0X2 INT_CLK_PCIE_VGAP J30 AD21
CLK_PCIE_VGAN INT_CLK_PCIE_VGAN SLT_GFX_CLKP GNT2#/SD_LED/GPO45
To GPU (13) CLK_PCIE_VGAN 4 3 K29
SLT_GFX_CLKN GNT3#/CLK_REQ7#/GPIO46
AK17 T39
AD19 CLKRUN#
CLKRUN# CLKRUN# (34)
H27 AH9
GPP_CLK0P LOCK#
H28
GPP_CLK0N
AF18
CLK_PCIE_WLANP INTE#/GPIO32
(28) CLK_PCIE_WLANP RP12 2 1 0X2 INT_CLK_PCIE_WLANP J27 AE18
CLK_PCIE_WLANN INT_CLK_PCIE_WLANN GPP_CLK1P INTF#/GPIO33
To WLAN (28) CLK_PCIE_WLANN 4 3 K26
GPP_CLK1N INTG#/GPIO34
AC16
AD18
INT_CLK2P INTH#/GPIO35
TP64 F33
INT_CLK2N GPP_CLK2P R280 NMP@22_4
TP65 F31 PCLK_DEBUG (28)
GPP_CLK2N R281 22_4
CLK_PCIE_LANP INT_CLK_PCIE_LANP PCLK_591 (34)
(26) CLK_PCIE_LANP R722 0_4 E33
CLK_PCIE_LANN R723 0_4 INT_CLK_PCIE_LANN GPP_CLK3P LPC_CLK0_R R608 22_4 LPC_CLK0
To LAN (26) CLK_PCIE_LANN E31
GPP_CLK3N LPCCLK0
B25 LPC_CLK0 (10) For EMI
D25 LPC_CLK1_R R611 22_4 LPC_CLK1
LPCCLK1 LPC_CLK1 (10)
<B3A_20120131> M23 D27 LAD0
GPP_CLK4P LAD0 LAD0 (28,34)
Note: CLK_FCH_SRCP/N is 100MHZ SSC M24 C28 LAD1
change to 0 ohm for layout routing GPP_CLK4N GENERATOR LAD1 LAD1 (28,34)
LPC
B A26 LAD2 PCLK_DEBUG C805 *15P/50V_4C
LAD2 LAD2 (28,34) B
Note: CLK_DP_NSSCP/N is 100MHZ non-SSC M27 A29 LAD3
LAD3 (28,34)
GPP_CLK5P LAD3 LFRAME# PCLK_591 C434 *15P/50V_4C
M26 A31
CLOCK
Note: CLK_PCIE_TRAVISP/N is 100MHZ non-SSC GPP_CLK5N LFRAME# LFRAME# (28,34)

B27 LDRQ#0
LDRQ0# LDRQ#1 T38
Note: CLK_APU_HCLKP/N is 100MHZ SSC N25 AE27 T30
GPP_CLK6P LDRQ1#/CLK_REQ6#/GPIO49 SERIRQ
N26 AE19 SERIRQ (34)
Note: CLK_PCIE_VGAP/N is 100MHZ SSC GPP_CLK6N SERIRQ/GPIO48
Note: GPP_CLK(0:8)P/N is 100MHZ SSC capable R23

GPP_CLK7P
R24
GPP_CLK7N DMAACTIVE_L 32K_X1 C562 18P/50V_4C
G25 DMAACTIVE_L (4)
DMA_ACTIVE# APU_PROCHOT#_VDDIO
N27 E28 APU_PROCHOT#_VDDIO (4,34)
GPP_CLK8P PROCHOT#
1
2
R27 E26 APU_PWRGD
APU
GPP_CLK8N APU_PG APU_PWRGD (4)

C380 15P/50V_4C G26 APU_STOP# Y7
LDT_STP# APU_RST# T31
F26 APU_RST# (4) R390 32.768KHZ_10
CLK_48M_CARD R277 22_4 CLK_48M_CARD_R APU_RST# 20M_4
Card Reader (29) CLK_48M_CARD J26
14M_25M_48M_OSC C534 *0.1U/10V_4X
4
3
G2 32K_X1 32K_X2 C560 18P/50V_4C
32K_X1
C397 27P/50V_4N R715 0_4 25M_X1 C31 G4 32K_X2 USE GROUND GUARD FOR 32K_X1 AND 32K_X2
25M_X1 32K_X2
2
H7 S5_CORE_EN S5_CORE_EN is necessary to connect enable pin of

S5_CORE_EN RTC_CLK T41 +3VPCU/+5VPCU regulator for S5+ mode implementation
Y6 R273 F1 RTC_CLK (10,34)
25MHZ_30 25M_X2 RTCCLK INTRUDER_ALERT# R352 *1M/F_4
C33 F3 +3V_RTC
1M/F_4 25M_X2 INTRUDER_ALERT# +3V_RTC INTRUDER_ALERT# Left not connected
E6
PLUS
+3V_RTC
1
VDDBT_RTC_G
(FCH has 50-kohm internal pull-up to
S5
C381 27P/50V_4N
20MIL R656 C531
VBAT).
Hudson-M3 0.1U/10V_4X
560_4
<B3A_20120207>
change C397,C381 to 27pF (crystal vendor suggest)
1
Main source: BG625000737 G6
2nd source: BG625000486
2 *SHORT_PAD
A A

PROJECT :BY7D
FCH 2/5(ACPI/PCI/CLK) 1A

5 4 3 2 1
5 4 3 2 1
U3B
SPI Shared Flash 08
PLACE SATA AC COUPLING
+3V_S5 +3VPCU
CAPS CLOSE TO HUDSON-M2/M3
(31) SATA_TXP0 AK19

SATA_TX0P
HUDSON-M3 Part 2 of 5
SD_CLK/SCLK_2/GPIO73
AL14
AM19 AN14 R718 R719
(31) SATA_TXN0 SATA_TX0N SD_CMD/SLOAD_2/GPIO74
AJ12
SATA HDD/SSD AL20
SD_CD#/GPIO75
AH12
0_4 *0_4
(31) SATA_RXN0 SATA_RX0N SD_WP/GPIO76
(31) SATA_RXP0 AN20 AK13
SATA_RX0P SD_DATA0/SDATI_2/GPIO77
D AM13 D
SD_DATA1/SDATO_2/GPIO78 R496 10K_4
(31) SATA_TXP1 AN22 AH15
SATA_TX1P SD_DATA2/GPIO79
AL22 AJ14
CARD
(31) SATA_TXN1 SATA_TX1N SD_DATA3/GPIO80
SATA ODD
SD
AH20 AC4 U18
(31) SATA_RXN1 SATA_RX1N GBE_COL FCH_SPI_CS0#
AJ20 AD3 1 8 R372 R488
(31) SATA_RXP1 SATA_RX1P GBE_CRS (34) FCH_SPI_CS0# FCH_SPI_CLK CE# VDD
AD9 6 10K_4 10K_4
GBE_MDCK (34) FCH_SPI_CLK FCH_SPI_SO SCK
AJ22 W10 (34) FCH_SPI_SO 5
SATA_TX2P GBE_MDIO FCH_SPI_SI R376 33_4 FCH_SPI_SI_R SI
AH22 AB8 (34) FCH_SPI_SI 2 7 SPI_HOLD# (6)
SATA_TX2N GBE_RXCLK SO HOLD#
AH7
GBE_RXD3
AM23 AF7 3 4
SATA_RX2N GBE_RXD2 C557 WP# VSS C551
AK23 AE7
SATA_RX2P GBE_RXD1 *22P/50V_4N W25Q16BVSSIG 0.1U/10V_4X
AD7
GBE_RXD0
AH24 AG8
SATA_TX3P GBE_RXCTL/RXDV
AJ24 AD1
GBE
SATA_TX3N GBE_RXERR
LAN
SATA_TX/RX[5:2]P/N and SATA_IS[5:2]# do not exist on Hudson-M3L/D3L GBE_TXCLK
AB7
SATA_TX/RX[7,6]P/N and SATA_IS[7,6]# only exist on Hudson-D4. AN24 AF9
SATA_RX3N GBE_TXD3 FCH_SPI_WP
AL24 AG6
SATA_RX3P GBE_TXD2
AE8
GBE_TXD1
AL26 AD8
SATA_TX4P GBE_TXD0
AN26 AB9
SATA_TX4N GBE_TXCTL/TXEN
AC2
GBE_PHY_PD
AJ26 AA7
SATA_RX4N GBE_PHY_RST# GBE_PHY_INTR R342 10K_4
AH26 W9
SATA_RX4P GBE_PHY_INTR +3V_S5
W25Q32BVSSIG:AKE391P0N00
SERIAL
AN29
W25Q16BVSSIG:AKE38FP0N01
ATA
SATA_TX5P FCH_SPI_SI
AL28 V6
SATA_TX5N SPI_DI/GPIO164 FCH_SPI_SO_R R380 33_4 FCH_SPI_SO
SPI_DO/GPIO163
V5 A-stage Socket: DG008000031 91960-0084L
AK27 V3 FCH_SPI_CLK_R R386 33_4 FCH_SPI_CLK
SATA_RX5N SPI_CLK/GPIO162 FCH_SPI_CS0#_R R387 33_4 FCH_SPI_CS0#
AM27 T6
SATA_RX5P SPI_CS1#/GPIO165 FCH_SPI_WP
V1
ROM
ROM_RST#/SPI_WP#/GPIO161
SPI
AL29
NC6
AN31
NC7
L30 T45
VGA_RED
AL31
NC8
PLACE SATA_CAL RES VERY AL33
NC9 VGA_GREEN
L32 T46
C
CLOSE TO BALL OF AH33 M29 C
NC10 VGA_BLUE T47
HUDSON-M2/M3 AH31
NC11
AJ33 M28 T48
NC12 VGA_HSYNC/GPO68
AJ31 N30 T49
NC13 VGA_VSYNC/GPO69
DAC
VGA
M33 +1.5VSUS +3V_S5
VGA_DDC_SDA/GPO70 T50
N32 T51
R581 1K/F_4 SATA_CALRP VGA_DDC_SCL/GPO71
AF28
R583 931/F_4 SATA_CALRN SATA_CALRP
+1.1V_AVDD_SATA AF27 K31 T52
SATA_CALRN VGA_DAC_RSET R425 R426
V28 *1K/F_4 *1K/F_4
AUX_VGA_CH_P T53
R652 10K/F_4 SATA_LED# AD22 V29
SATA_ACT#/GPIO67 AUX_VGA_CH_N T54
U28 T55
AUXCAL VIN_VDDIO VIN_VDDR
AF21
SATA_X1
T31 T56
ML_VGA_L0P
T33 T57
Integrated Clock Mode: ML_VGA_L0N R429 C599 R427 C596
T29 T58
ML_VGA_L1P *1K/F_4 *0.1U/10V_4X *1K/F_4 *0.1U/10V_4X
Leave unconnected. T28 T59
ML_VGA_L1N
R32 T60
+3V ML_VGA_L2P
AG21 R30 T61
SATA_X2 ML_VGA_L2N
P29 T62
ML_VGA_L3P
P28
MAINLINK
ML_VGA_L3N T63
R648 Remove Zero Power ODD funciton C29
ML_VGA_HPD/GPIO229 T64
*10K/F_4
BOARD_ID1 VGA VIN0
AH16 N2 R359 10K_4
T138 BOARD_ID11 FANOUT0/GPIO52 VIN0/GPIO175 VIN1 R674 10K_4
AM15 M3
FCH_PROCHOT#_C FANOUT1/GPIO53 VIN1/GPIO176 VIN2 R676 10K_4
AJ16 L2
FANOUT2/GPIO54 HW VIN2/SDATI_1/GPIO177 MEM_P1V5
N4 T43
BOARD_ID2 VIN3/SDATO_1/GPIO178 MEM_P1V35
AK15 MONITOR P1 T44
BOARD_ID3 FANIN0/GPIO56 VIN4/SLOAD_1/GPIO179 VIN_VDDIO
AN16 P3
BOARD_ID4 FANIN1/GPIO57 VIN5/SCLK_1/GPIO180 VIN_VDDR
AL16 M1
FANIN2/GPIO58 VIN6/GBE_STAT3/GPIO181 VIN7 R675 10K_4
M5
BOARD_ID5 VIN7/GBE_LED3/GPIO182
K6
BOARD_ID6 TEMPIN0/GPIO171
K5 AG16
BOARD_ID7 TEMPIN1/GPIO172 NC1 R312 IV@10K_4 BOARD_ID1 R317 EV@10K_4
B K3 AH10 +3V B
R717 0_4 SB_TALERT# TEMPIN2/GPIO173 NC2 R334 ULU3@10K_4 BOARD_ID2 R333 ULU2@10K_4
(4) APU_TALERT# M6 A28
TEMPIN3/TALERT#/GPIO174 NC3 R322 UR3@10K_4 BOARD_ID3 R320 UR2@0_4
G27
NC4 R297 NLAN@10K_4 BOARD_ID4 R310 LAN@10K_4
L4
NC5 R692 NHDMI@10K_4 BOARD_ID8 R693 HDMI@10K_4
R736 NCRT@10K_4 BOARD_ID9 R538 CRT@10K_4
Hudson-M3 R704 Seymour@10K_4 BOARD_ID11 R424 Thames@10K_4
R684 NS&C@10K_4 BOARD_ID5 R683 S&C@10K_4

+3V_S5
R671 NBT@10K_4 BOARD_ID6 R677 BT@10K_4
R699 NCEC@10K_4 BOARD_ID7 R422 CEC@10K_4
R703 IMR@10K_4 BOARD_ID10 R423 TEXTURE@10K_4

BOARD ID SETTING
Board ID ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 ID10 ID11
BOARD_ID8
(6) BOARD_ID8 BOARD_ID9
UMA SKU H (6) BOARD_ID9
VGA SKU L BOARD_ID10
(6,33) BOARD_ID10
ULU3 H
ULU2 L
UR3 H
UR2 L
W/O LAN H
W LAN L
W/O S&C H
W S&C L
W/O BT H
W BT L
A A
W/O CEC H
W CEC L
W/O HDMI H
W HDMI L
W/O CRT H
W CRT L
Metal/IMR H
TEXTURE L Quanta Computer Inc.
Seymour H PROJECT :BY7D
Thames L
FCH 3/5(SATA/VGA/GND/SPI) 1A

5 4 3 2 1
5 4 3 2 1
PLACE ALL THE DECOUPLING CAPS ON

THIS SHEET CLOSE TO SB AS POSSIBLE. VDD-- S/B CORE power
U3D
09
<B3A_20120202>
+3.3V_FCH_R
change to short pad <B3A_20120202>
change to short pad A3
HUDSON-M3 T25
U3C +1.1V_VCC_FCH_R VSS_1 VSS_65
VDDQ--3.3V I/O power 102mA A33
VSS_2
Part 5 of 5
VSS_66
T27
R299 *0/short_8 1007mA TRACE WIDTH >=100mil
+3V
AB17 HUDSON-M3
VDDIO_33_PCIGP_1
Part 3 of 5
VDDCR_11_1
T14 R300 *0/short_8 +1.1V
B7
B13
VSS_3
VSS_4
VSS_67
VSS_68
U6
U14
AB18 T17 D9 U17
C539 C541 C512 C543 C491 C501 C494 C524 VDDIO_33_PCIGP_2 VDDCR_11_2 VSS_5 VSS_69
AE9 T20 D13 U20
1U/10V_4X 1U/10V_4X 1U/10V_4X 1U/10V_4X 22U/6.3V_8X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X VDDIO_33_PCIGP_3 VDDCR_11_3 C478 C477 C490 C489 C498 C497 C513 C514 VSS_6 VSS_70
AD10 U16 E5 U21
VDDIO_33_PCIGP_4 VDDCR_11_4 VSS_7 VSS_71
PCI/GPIO I/O
D AG7 U18 0.1U/10V_4X 0.1U/10V_4X 1U/10V_4X 1U/10V_4X 10U/6.3V_8X 1U/10V_4X 2.2U/6.3V_4X 2.2U/6.3V_4X E12 U30 D
CORE
AC13 V14 E16 U32
Note: AB12 V17 E29 V11
S0
VDDPL_33_SSUSB_S: AB13
VDDIO_33_PCIGP_8 VDDCR_11_8
V20 CKVDD_1.1V-- F7
VSS_11 VSS_75
V16
AB14 Y17 Internal clock F9 V18
If USB3 S5 Wake is supported, tie to +3.3V_S5 rail. VDDIO_33_PCIGP_9 VDDCR_11_9 +1.1V_CKVDD VSS_12 VSS_76
AB16 Generator I/O F11 W4
VDDIO_33_PCIGP_10 VSS_13 VSS_77
If USB3 is not used, tie to GND. 340mA F13 W6
47mA H24 H26 TRACE WIDTH >=30mil power F16
VSS_14 VSS_78
W25
VDDPL_33_USB_S: +VDDPL_3.3V VDDPL_33_SYS VDDAN_11_CLK_1 L42 VSS_15 VSS_79
V22 J25 +1.1V F17 W28
If S5 Wake is supported, tie to +3.3V_S5 rail. VDDPL_33_DAC VDDAN_11_CLK_2 HCB1608KF-181T15_1.5A VSS_16 VSS_80
U22 K24 F19 Y14
VDDPL_33_ML VDDAN_11_CLK_3 VSS_17 VSS_81
T22 L22 F23 Y16
L44 +FCH_VDDPL_33_SSUSB_S VDDAN_33_DAC VDDAN_11_CLK_4 C460 C459 C442 C404 C484 C474 VSS_18 VSS_82
+3V_S5 11mA L18
VDDPL_33_SSUSB_S VDDAN_11_CLK_5
M22 F25
VSS_19 VSS_83
Y18
CLKGEN
U3@HCB1608KF-221T20_2A +FCH_VDDPL_33_SUSB_S 14mA D7 N21 1U/10V_4X 1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 22U/6.3V_8X 1U/10V_4X F29 AA6
+FCH_VDDPL_33_PCIE VDDPL_33_USB_S VDDAN_11_CLK_6 VSS_20 VSS_84
11mA AH29
VDDPL_33_PCIE VDDAN_11_CLK_7
N22 G6
VSS_21 VSS_85
AA12
R412 +FCH_VDDPL_33_SATA 12mA AG28 P22 G16 AA13
I/O
C508 C496 VDDPL_33_SATA VDDAN_11_CLK_8 +1.1V_PCIE_VDDR VSS_22 VSS_86
G32 AA14
VSS_23 VSS_87
U3@2.2U/6.3V_6X U3@0.1U/10V_4X U2@0_4 1088mA TRACE WIDTH >=100mil PCIE_VDDR--PCIE I/O power H12
VSS_24 VSS_88
AA16
C756 *2.2U/6.3V_6X M31 AB24 L29 +1.1V H15 AA17
LDO_CAP VDDAN_11_PCIE_1 HCB1608KF-181T15_1.5A VSS_25 VSS_89
Y21 H29 AA25
VDDAN_11_PCIE_2 VSS_26 VSS_90
V21 AE25 J6 AA28
VDDPL_11_DAC VDDAN_11_PCIE_3 VSS_27 VSS_91
GROUND
AD24 C407 C445 C430 C415 C391 C398 J9 AA30
L73 VDDAN_11_PCIE_4 VSS_28 VSS_92
0.1U/10V_4X 0.1U/10V_4X 1U/10V_4X 1U/10V_4X 22U/6.3V_8X 1U/10V_4X
EXPRESS
+3V_AVDD_USB Y22 AB23 J10 AA32
HCB1608KF-221T20_2A VDDAN_11_ML_1 VDDAN_11_PCIE_5 VSS_29 VSS_93
V23 AA22 J13 AB25
VDDAN_11_ML_2 VDDAN_11_PCIE_6 VSS_30 VSS_94
V24 AF26 J28 AC6
VDDAN_11_ML_3 VDDAN_11_PCIE_7 VSS_31 VSS_95
PCI
MAIN
C832 C829
LINK
V25 AG27 J32 AC18
2.2U/6.3V_6X 1U/10V_4X VDDAN_11_ML_4 VDDAN_11_PCIE_8 +1.1V_AVDD_SATA VSS_32 VSS_96
K7 AC28
VSS_33 VSS_97
Note: 1337mA TRACE WIDTH >=50mil AVDD_SATA--SATA phy power K16
VSS_34 VSS_98
AD27
VDDPL_33_DAC,VDDPL_33_ML,VDDAN_33_DAC: AB10 AA21 L30 +1.1V K27 AE6
VDDIO_33_GBE_S VDDAN_11_SATA_1 HCB1608KF-181T15_1.5A VSS_35 VSS_99
VGA translator is supported:Tie to +3.3V_S0. Y20 K28 AE15
VDDAN_11_SATA_4 VSS_36 VSS_100
GBE
L31 TRACE WIDTH >=15mil AB21 L6 AE21
LAN
+3V VGA translator is not supported:Tie to GND. VDDAN_11_SATA_2 VSS_37 VSS_101
VDDAN_11_ML,VDDPL_11_DAC: AB22 C467 C451 C472 C466 C412 C387 L12 AE28
HCB1608KF-221T20_2A VDDAN_11_SATA_3 1U/10V_4X 1U/10V_4X VSS_38 VSS_102
VGA translator is not supported:Tie to GND. AB11
VDDCR_11_GBE_S_1 VDDAN_11_SATA_5
AC22 0.1U/10V_4X 0.1U/10V_4X 22U/6.3V_8X 1U/10V_4X L13
VSS_39 VSS_103
AF8
C383 C393 AA11 AC21 L15 AF12
SERIAL
2.2U/6.3V_4X VDDCR_11_GBE_S_2 VDDAN_11_SATA_6 VSS_40 VSS_104
*0.1U/10V_4X AA20 L16 AF16
ATA
AA18 L21 AF33
AA9 AB20 M13 AG30
VDDIO_GBE_S_1 VDDAN_11_SATA_9 VSS_43 VSS_107
AA10 AC19 M16 AG32
L32 TRACE WIDTH >=15mil VDDIO_GBE_S_2 VDDAN_11_SATA_10 VSS_44 VSS_108
C +3V M21 AH5 C
VSS_45 VSS_109
M25 AH11
HCB1608KF-221T20_2A VSS_46 VSS_110
N6 AH18
C389 C399 S5_3.3--3.3v standby power S5 plus mode N11
VSS_47
VSS_48
VSS_111
VSS_112
AH19
2.2U/6.3V_4X *0.1U/10V_4X N13 AH21
TRACE WIDTH >=20mil VSS_49 VSS_113
+3V_AVDD_USB
59mA +VDDIO_33_S
N23
VSS_50 VSS_114
AH23
G7 N18 R314 *0/short_6 +3V_S5 N24 AH25
VDDAN_33_USB_S_1 VDDIO_33_S_1 VSS_51 VSS_115
H8 L19 P12 AH27
TRACE WIDTH >=50mil VDDAN_33_USB_S_2 VDDIO_33_S_2 VSS_52 VSS_116
470mA J8
VDDAN_33_USB_S_3 VDDIO_33_S_3
M18 <B3A_20120202> P18
VSS_53 VSS_117
AJ18
L47 K8 V12 C503 C455 C521 C538 C530 C527 C523 P20 AJ28
+3V_S5 VDDAN_33_USB_S_4 VDDIO_33_S_4 change to short pad VSS_54 VSS_118
3.3V_S5 I/O
K9 V13 *0.1U/10V_4X 2.2U/6.3V_6X 2.2U/6.3V_6X 1U/10V_4X 1U/10V_4X 1U/10V_4X 1U/10V_4X P21 AJ29
HCB1608KF-221T20_2A VDDAN_33_USB_S_5 VDDIO_33_S_5 VSS_55 VSS_119
M9 Y12 P31 AK21
C520 C552 C540 C545 C519 C525 VDDAN_33_USB_S_6 VDDIO_33_S_6 VSS_56 VSS_120
M10 Y13 P33 AK25
EMI VDDAN_33_USB_S_7 VDDIO_33_S_7 VSS_57 VSS_121
0.1U/10V_4X 22U/6.3V_8X10U/6.3V_8X 10U/6.3V_8X 1U/10V_4X 1U/10V_4X N9
VDDAN_33_USB_S_8 VDDIO_33_S_8
W11 R4
VSS_58 VSS_122
AL18
Note: N10 R11 AM21
USB
VDDAN_33_USB_S_9 VSS_59 VSS_123
VDDAN_33_USB_S: M12
VDDAN_33_USB_S_10 5mA +VDDXL_3.3V
R25
VSS_60 VSS_124
AM25
N12 G24 L33 +3V_S5 R28 AN1
If S5 Wake is supported, tie to +3.3V_S5 rail. +FCH_VDDAN_11_USB_S VDDAN_33_USB_S_11 VDDXL_33_S VSS_61 VSS_125
+1.1V_S5 L49 M11
VDDAN_33_USB_S_12
S5_1.1V--1.1V standby power HCB1608KF-221T20_2A T11
VSS_62 VSS_126
AN18
VDDCR_11_S,VDDAN_11_USB_S: C566 2.2U/6.3V_6X 113mA T16 AN28
HCB1608KF-221T20_2A C504 0.1U/10V_4X TRACE WIDTH >=20mil U12 +VDDCR_1.1V R353 *0/short_6 +1.1V_S5 C420 C386 C385 VSS_63 VSS_127
If S5 Wake is supported, tie to +1.1V_S5 rail. N20 T18 AN33
C548 0.1U/10V_4X VDDAN_11_USB_S_1 VDDCR_11_S_1 TRACE WIDTH >=15mil *0.1U/10V_4X 2.2U/6.3V_6X 1U/10V_4X VSS_64 VSS_128
VDDCR_11_SSUSB_S,VDDAN_11_SSUSB_S: 140mA U13
VDDAN_11_USB_S_2 VDDCR_11_S_2
M20
N8 T21
L52 +FCH_VDDCR_11_USB_S C473 C461 C456 VSSAN_HWM VSSPL_DAC
If USB3 S5 Wake is supported, tie to +1.1V_S5 rail. +1.1V_S5 T12
VDDCR_11_USB_S_1 VDDPL_11_SYS_S
J24 70mA +VDDPL_1.1V VSSAN_DAC
L28
TRACE WIDTH >=15mil T13 1U/10V_4X 1U/10V_4X 2.2U/6.3V_4X <B3A_20120202> K25 K33
If USB3 is not used, tie to GND. HCB1608KF-221T20_2A VDDCR_11_USB_S_2 VSSXL VSSANQ_DAC
42mA 12mA change to short pad VSSIO_DAC
N28
C505 C518 C587 M8 +VDDAN_3.3V_HWM H25
VDDAN_33_HWM_S VSSPL_SYS
0.1U/10V_4X 0.1U/10V_4X 10U/6.3V_8X P16
VDDAN_11_SSUSB_S_1 EFUSE
R6
+1.1V_S5 +FCH_VDD_11_SSUSB_S M14
N14
VDDAN_11_SSUSB_S_2
AA4 26mA +VDDIO_AZ Hudson-M3
VDDAN_11_SSUSB_S_3 VDDIO_AZ_S
+FCH_VDDAN_11_SSUSB_S_R
282mA P13
VDDAN_11_SSUSB_S_4
L46 R302 *0/short_8 P14 Trace width >=20 mil Note:
U3@HCB1608KF-221T20_2A VDDAN_11_SSUSB_S_5
USB VDD L_33_S:
N16
VDDCR_11_SSUSB_S_1 SS If USB3 Wake is supported, tie to +3.3V_S5 rail.
+FCH_VDDCR_11_SSUSB_S
424mA N17
VDDCR_11_SSUSB_S_2
R304 *0/short_8 P17 Otherwise, tie to +3.3V_S0 rail.
VDDCR_11_SSUSB_S_3
M17 VDDPL_11_SYS_S:
VDDCR_11_SSUSB_S_4
B C515 C485 R414 If USB3 S5 Wake is supported, tie to +1.1V_S5 rail. B
R413 U3@10U/6.3V_8X U3@0.1U/10V_4X If only USB S3 Wake is supported, tie to +1.1V_S3 rail.
C510 C507 C495 C506 U2@0_4
U2@0_4 U3@1U/10V_4X U3@1U/10V_4X C493 C482
If USB Wake is not supported, tie to +1.1V_S0 rail.
U3@0.1U/10V_4X U3@0.1U/10V_4X POWER
U3@1U/10V_4X U3@0.1U/10V_4X VDDIO_AZ_S:
Wake on Ring supported: Tie to +3.3/1.5V_S5.
Hudson-M3
Wake on Ring not supported: Tie to +3.3/1.5V_S0.
+1.1V_S5 +1.1V +VDDPL_1.1V

+VDDIO_AZ
+3V +VDDPL_3.3V
+3V_S5 +3V_S5 +VDDAN_3.3V_HWM
L36
U2@HCB1608KF-221T20_2A L40
R301 *0/short_8 L35 L51 HCB1608KF-221T20_2A
U3@HCB1608KF-221T20_2A HCB1608KF-221T20_2A
<B3A_20120202> C437 C433
C427 C443 C570 C532 2.2U/6.3V_6X 0.1U/10V_4X
change to short pad C593 C448 2.2U/6.3V_6X 2.2U/6.3V_6X
0.1U/10V_4X 0.1U/10V_4X
2.2U/6.3V_6X *0.1U/10V_4X
A A

PROJECT :BY7D
FCH 4/5(POWER) 1A

5 4 3 2 1
5 4 3 2 1
OVERLAP COMMON PADS WHERE

POSSIBLE FOR DUAL-OP RESISTORS.
+3V +3V +3V +3V_S5 +3V_S5 +3V_S5 +3V_S5
10
STRAPS PINS
D D
R700 R702 R701 R617 R625 R305 R663
10K_4 *10K_4 *10K_4 *10K_4 10K_4 *10K_4 10K_4
(7) PCI_CLK1
PCI_CLK1
FCH POWER GOOD CIRCUIT
PCI_CLK3
(7) PCI_CLK3
PCI_CLK4
(7) PCI_CLK4 +3V_S5
LPC_CLK0
(7) LPC_CLK0
LPC_CLK1
(7) LPC_CLK1
EC_PWM2 C8
(6) EC_PWM2
*0.1U/10V_4X
RTC_CLK
(7,34) RTC_CLK
5
PU to +3V in power IC
PU to +3V_S5 in FCH 2 CPU_COREPG (4,41)
FCH_PWRGD 4
(6) FCH_PWRGD MPWROK
1 MPWROK (34)
R686 R690 R688 R612 R620 R306 R672
*10K_4 10K_4 10K_4 10K_4 *10K_4 2.2K_4 *2.2K_4 EC_PWM2--> U1 TC7SH08FU(F) PU to +3VPCU in EC
3
SPI ROM: 2.2-KΩ 5% pull-down C9
LPC ROM: Pull-up to 3.3V_S5. R6
External pull-up resistor is not required as FCH has *0.1U/10V_4X 100K_4
integrated 10-KΩ pull-up to 3.3V_S5.
C C
Remove PCI_CLK2 function
-------- PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4 LPC_CLK0 LPC_CLK1 EC_PWM2 RTC_CLK

REQUIRED
STRAPS PULL ALLOW USE non_Fusion EC CLKGEN LPC ROM S5 PLUS MODE
HIGH PCIE Gen2 DEBUG CLOCK MODE ENABLED ENABLED DISABLED
-------- --------
DEFAULT STRAP DEFAULT DEFAULT
PULL FORCE IGNORE FUSION EC CLKGEN SPI ROM S5 PLUS MODE

-------- PCIE Gen1 DEBUG CLOCK MODE DISABLED DISABLED ENABLED
LOW --------
STRAP DEFAULT DEFAULT DEFAULT
DEFAULT
B B
DEBUG STRAPS
FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]
PCI_AD27
(7) PCI_AD27
PCI_AD26
(7) PCI_AD26
PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23
PCI_AD25
(7) PCI_AD25
PCI_AD24 PULL USE PCI DISABLE ILA USE FC USE DEFAULT DISABLE PCI
(7) PCI_AD24
PCI_AD23 HIGH PLL AUTORUN PLL PCIE STRAPS MEM BOOT
(7) PCI_AD23
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
R345 R401 R402 R351 R350

*2.2K_4 *2.2K_4 *2.2K_4 *2.2K_4 *2.2K_4 PULL BYPASS ENABLE ILA BYPASS FC USE EEPROM ENABLE PCI
LOW PCI PLL AUTORUN PLL PCIE STRAPS MEM BOOT
A A

PROJECT :BY7D
FCH 5/5(STRAP & PWRGD) 1A
Date: Monday, March 19, 2012 Sheet 10 of 45

5 4 3 2 1
1
DDR_STD H=4(DDR)
11
JDIM1A M_A_DQ[0..63] (3,12)
(3,12) M_A_A[15:0]
M_A_A0 98 5 M_A_DQ0
M_A_A1 A0 DQ0 M_A_DQ1 +1.5VSUS
97 7 JDIM1B
M_A_A2 A1 DQ1 M_A_DQ2
96 15
95 17 2.48A 75 44
M_A_A4 A3 DQ3 M_A_DQ4 VDD1 VSS16
92 4 76 48
91 6 81 49
90 16 82 54
86 18 87 55
89 21 88 60
85 23 93 61
107 33 94 65
M_A_A11 A10/AP DQ10 M_A_DQ11 VDD8 VSS23
84 35 99 66
83 22 100 71
M_A_A13 A12/BC# DQ12 M_A_DQ13 VDD10 VSS25
119 24 105 72
80 34 106 127
A14 DQ14 VDD12 VSS27
PC2100 DDR3 SDRAM SO-DIMM

M_A_A15 78 36 M_A_DQ15 111 128
A15 DQ15 M_A_DQ16 VDD13 VSS28
39 112 133

DQ16 M_A_DQ17 VDD14 VSS29
(3,12) M_A_BS#0 109 41 117 134
BA0 DQ17 M_A_DQ18 VDD15 VSS30
(3,12) M_A_BS#1 108 51 118 138
(3,12) M_A_BS#2 79 53 123 139
(3) M_A_CS#2 114 40 124 144
M_A_CKE0 S0# DQ20 M_A_DQ21 VDD18 VSS33
(3) M_A_CS#3 121 42 145
S1# DQ21 M_A_DQ22 VSS34
(3) M_A_CLKP2 101 50 +3V 199 150
CK0 DQ22 M_A_DQ23 VDDSPD VSS35
(3) M_A_CLKN2 103 52 151
CK0# DQ23 M_A_DQ24 VSS36
(3) M_A_CLKP3 102 57 77 155
CK1 DQ24 M_A_DQ25 NC1 VSS37
(3) M_A_CLKN3 104 59 122 156
R9875 CK1# DQ25 M_A_DQ26 NC2 VSS38
(3,12) M_A_CKE0 73 67 125 161
CKE0 DQ26 M_A_DQ27 R9876 *10K/F_4 NCTEST VSS39
(3,12) M_A_CKE1 74 69 +3V 162
*68_4 CKE1 DQ27 M_A_DQ28 VSS40
(3,12) M_A_CAS# 115 56 (3,12) M_A_EVENT# 198 167
CAS# DQ28 M_A_DQ29 EVENT# VSS41
(3,12) M_A_RAS# 110 58 (3,12) M_A_RST# 30 168
RAS# DQ29 M_A_DQ30 RESET# VSS42
(3,12) M_A_WE# 113 68 172
R9877 10K/F_4 DIMM2_SA0 WE# DQ30 M_A_DQ31 VSS43
+3V 197 70 173
R9878 10K/F_4 DIMM2_SA1 SA0 DQ31 M_A_DQ32 +SMDDR_VREF_DQ VSS44
201 129 +SMDDR_VREF_DQ 1 178
SMB_RUN_CLK SA1 DQ32 M_A_DQ33 +SMDDR_VREF_CA VREF_DQ VSS45
(6,12,33) SMB_RUN_CLK 202 131 +SMDDR_VREF_CA 126 179
SMB_RUN_DAT SCL DQ33 M_A_DQ34 VREF_CA VSS46
(6,12,33) SMB_RUN_DAT 200 141 184
SDA DQ34 M_A_DQ35 VSS47
143 185
M_A_CKE1 DQ35 M_A_DQ36 VSS48
(3) M_A_ODT2 116 130 2 189
ODT0 DQ36 M_A_DQ37 VSS1 VSS49
(3) M_A_ODT3 120 132 3 190
140 8 195
(204P)
DQ38 M_A_DQ39 VSS3 VSS51
(3,12) M_A_DM0 11 142 9 196
DM0 DQ39 M_A_DQ40 VSS4 VSS52
(3,12) M_A_DM1 28 147 13
R9879 DM1 DQ40 M_A_DQ41 VSS5
(3,12) M_A_DM2 46 149 14
(204P)
DM2 DQ41 M_A_DQ42 VSS6
(3,12) M_A_DM3 63 157 19
*68_4 DM3 DQ42 M_A_DQ43 VSS7
(3,12) M_A_DM4 136 159 20
(3,12) M_A_DM5 153 146 25
(3,12) M_A_DM6 170 148 26 203 +SMDDR_VTERM
DM6 DQ45 M_A_DQ46 VSS10 VTT1
(3,12) M_A_DM7 187 158 31 204
(3,12) M_A_DQSP[7:0] 160 32
M_A_DQSP0 DQ47 M_A_DQ48 VSS12
12 163 37 205
M_A_DQSP1 DQS0 DQ48 M_A_DQ49 VSS13 GND
29 165 38 206
M_A_DQSP2 DQS1 DQ49 M_A_DQ50 VSS14 GND
47 175 43
M_A_DQSP3 DQS2 DQ50 M_A_DQ51 VSS15
64 177
M_A_DQSP4 DQS3 DQ51 M_A_DQ52
137 164
M_A_DQSP5 DQS4 DQ52 M_A_DQ53 DDRSK-20401-TP4B
154 166
171 174
(3,12) M_A_DQSN[7:0] 188 176
AMD suggestion for CLK glitch 12/29 M_A_DQSN0 DQS7 DQ55 M_A_DQ56
10 181
M_A_DQSN1 DQS#0 DQ56 M_A_DQ57
27 183
45 191
62 193
135 180
152 182
169 192
186 194
DQS#7 DQ63
DDRSK-20401-TP4B
A A
TERMINATOR DECOUPLING CAPACITOR 9.12A(VCC plane from source)

+1.5VSUS
+1.5VSUS
+SMDDR_VTERM +3V
C5685 C5686 C5687
C5688 C5689 C5690 C5691 C5692 C5693 C5694 10U/6.3V_8X 10U/6.3V_8X 10U/6.3V_8X C5695
10U/6.3V_8X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 2.2U/6.3V_6X 0.1U/10V_4X *C@0.1U/10V_4X
+1.5VSUS
EMI 01/07
C5697 C5698 C5699
+ C5696
+SMDDR_VREF_CA 10U/6.3V_8X 10U/6.3V_8X 10U/6.3V_8X
+SMDDR_VREF_DQ *220U/2.5V_3528P_E35b
C5703 C5704 C5705

C5700 C5701 C5702 Close to DIMM1
1000P/50V_4X 0.1U/10V_4X 2.2U/6.3V_6X
1000P/50V_4X 0.1U/10V_4X 2.2U/6.3V_6X
Close to DIMM1 Quanta Computer Inc.

PROJECT : BY7D
1A
DDRIII SODIMM1
1
1 2 3 4 5 6 7 8
DDR_STD H=8(DDR)
(3,11) M_A_A[15:0]
M_A_A0
<Layout Note>
Close to CPU
JDIM2A
M_A_DQ0
M_A_DQ[0..63] (3,11)
+1.5VSUS
JDIM2B
12
98 5
97 7 75 44
96 15 2.48A 76 48
95 17 81 49
92 4 82 54
91 6 87 55
90 16 88 60
86 18 93 61
89 21 94 65
85 23 99 66
107 33 100 71
M_A_A11 A10/AP DQ10 M_A_DQ11 VDD10 VSS25
84 35 105 72
A
M_A_A12 A11 DQ11 M_A_DQ12 VDD11 VSS26 A
83 22 106 127
A12/BC# DQ12 VDD12 VSS27

M_A_A13 119 24 M_A_DQ13 111 128
80 34 112 133
78 36 117 134
A15 DQ15 M_A_DQ16 VDD15 VSS30
39 118 138

DQ16 M_A_DQ17 VDD16 VSS31
(3,11) M_A_BS#0 109 41 123 139
(3,11) M_A_BS#1 108 51 124 144
(3,11) M_A_BS#2 79 53 145
BA2 DQ19 M_A_DQ20 VSS34
(3) M_A_CS#0 114 40 +3V 199 150
S0# DQ20 M_A_DQ21 VDDSPD VSS35
(3) M_A_CS#1 121 42 151
S1# DQ21 M_A_DQ22 VSS36
(3) M_A_CLKP0 101 50 77 155
CK0 DQ22 M_A_DQ23 NC1 VSS37
(3) M_A_CLKN0 103 52 122 156
CK0# DQ23 M_A_DQ24 R9880 *10K/F_4 NC2 VSS38
(3) M_A_CLKP1 102 57 +3V 125 161
CK1 DQ24 M_A_DQ25 NCTEST VSS39
(3) M_A_CLKN1 104 59 162
CK1# DQ25 M_A_DQ26 VSS40
(3,11) M_A_CKE0 73 67 (3,11) M_A_EVENT# 198 167
CKE0 DQ26 M_A_DQ27 EVENT# VSS41
(3,11) M_A_CKE1 74 69 (3,11) M_A_RST# 30 168
CKE1 DQ27 M_A_DQ28 RESET# VSS42
(3,11) M_A_CAS# 115 56 172
CAS# DQ28 M_A_DQ29 VSS43
(3,11) M_A_RAS# 110 58 173
RAS# DQ29 M_A_DQ30 +SMDDR_VREF_DQ VSS44
(3,11) M_A_WE# 113 68 +SMDDR_VREF_DQ 1 178
R9881 10K/F_4 DIMM1_SA0 WE# DQ30 M_A_DQ31 +SMDDR_VREF_CA VREF_DQ VSS45
197 70 +SMDDR_VREF_CA 126 179
R9882 10K/F_4 DIMM1_SA1 SA0 DQ31 M_A_DQ32 VREF_CA VSS46
201 129 184
SMB_RUN_CLK SA1 DQ32 M_A_DQ33 VSS47
(6,11,33) SMB_RUN_CLK 202 131 185
SMB_RUN_DAT SCL DQ33 M_A_DQ34 VSS48
(6,11,33) SMB_RUN_DAT 200 141 2 189
SDA DQ34 M_A_DQ35 VSS1 VSS49
143 3 190
DQ35 M_A_DQ36 VSS2 VSS50
(3) M_A_ODT0 116 130 8 195
(204P)
(3) M_A_ODT1 120 132 9 196
140 13
DQ38 M_A_DQ39 VSS5
(3,11) M_A_DM0 11 142 14
(3,11) M_A_DM1 28 147 19
(3,11) M_A_DM2 46 149 20
(204P)
(3,11) M_A_DM3 63 157 25
(3,11) M_A_DM4 136 159 26 203 +SMDDR_VTERM
(3,11) M_A_DM5 153 146 31 204
(3,11) M_A_DM6 170 148 32
(3,11) M_A_DM7 187 158 37 205
DM7 DQ46 M_A_DQ47 VSS13 GND
(3,11) M_A_DQSP[7:0] 160 38 206
M_A_DQSP0 DQ47 M_A_DQ48 VSS14 GND
12 163 43
M_A_DQSP1 DQS0 DQ48 M_A_DQ49 VSS15
29 165
47 175
M_A_DQSP3 DQS2 DQ50 M_A_DQ51 DDRSK-20401-TP8D
B 64 177 B
137 164
154 166
171 174
(3,11) M_A_DQSN[7:0] 188 176
M_A_DQSN0 DQS7 DQ55 M_A_DQ56
10 181
27 183
45 191
62 193
135 180
152 182
169 192
186 194
DQS#7 DQ63
DDRSK-20401-TP8D
C 9.12A(VCC plane from source) C
TERMINATOR DECOUPLING CAPACITOR

+1.5VSUS
+SMDDR_VTERM +SMDDR_VREF_DQ +SMDDR_VREF_CA

+SMDDR_VTERM +3V
C5706 C5707 C5708
C5715 10U/6.3V_8X 10U/6.3V_8X 10U/6.3V_8X R9883 *0_6 +SMDDR_VREF R9884 *0_6 +SMDDR_VREF
C5709 C5710 C5711 C5712 C5713 C5714 C5716
10U/6.3V_8X
10U/6.3V_8X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 2.2U/6.3V_6X 0.1U/10V_4X R9885 1K_4 R9886 1K_4 +1.5VSUS R9887 1K_4 R9888 1K_4 +1.5VSUS
+1.5VSUS 0.32uA(20mils)
C5718 C5719 C5720

+ C5717
+SMDDR_VREF_DQ +SMDDR_VREF_CA 10U/6.3V_8X 10U/6.3V_8X 10U/6.3V_8X
*220U/2.5V_3528P_E35b
C5721 C5723 C5724 C5726

C5722 C5725 Close to DIMM0
1000P/50V_4X 0.1U/10V_4X 2.2U/6.3V_6X 1000P/50V_4X 0.1U/10V_4X 2.2U/6.3V_6X
Close to DIMM0
D D

PROJECT : BY7D
1A
DDRIII SODIMM2
1 2 3 4 5 6 7 8
<VGA>
PART 1 0F 9
U5000A
13
AA38 PCIE_RX0P PCIE_TX0P Y33
Y37 PCIE_RX0N PCIE_TX0N Y32
Y35 PCIE_RX1P PCIE_TX1P W33

Seymour Power-on sequence
W36 W32
PCIE_RX1N PCIE_TX1N
1 => +1V_GPU
W38
V37
PCIE_RX2P
PCIE_RX2N
PCIE_TX2P
PCIE_TX2N
U33
U32
2 => +3V_GPU
3 => +VGPU_CORE,+1.5V_GPU
V35
U36
PCIE_RX3P
PCIE_RX3N
PCIE_TX3P
PCIE_TX3N
U30
U29 4 => +1.8V_GPU
U38 PCIE_RX4P PCIE_TX4P T33
T37 PCIE_RX4N PCIE_TX4N T32
T35 PCIE_RX5P PCIE_TX5P T30

PEG
R36 T29
PCIE_RX5N PCIE_TX5N
Intel platform: Lane0 ~ Lane15
R38
P37
PCIE_RX6P
PCIE_RX6N
PCIE_TX6P
PCIE_TX6N
P33
P32
Brazos platform: Lane12 ~ Lane15
Comal and Sabine platform: Lane8 ~Lane15
P35 PCIE_RX7P PCIE_TX7P P30
N36 PCIE_RX7N PCIE_TX7N P29
N38 PCIE_RX8P PCIE_TX8P N33

M37 PCIE_RX8N PCIE_TX8N N32
PCI EXPRESS INTERFACE

M35 PCIE_RX9P PCIE_TX9P N30
L36 PCIE_RX9N PCIE_TX9N N29
L38 PCIE_RX10P PCIE_TX10P L33

K37 PCIE_RX10N PCIE_TX10N L32
K35 PCIE_RX11P PCIE_TX11P L30

J36 PCIE_RX11N PCIE_TX11N L29
PEG_TXP3 J38 PCIE_RX12P PCIE_TX12P K33 CPEG_RXP3 C5024 EV@0.1U/10V_4X

(3) PEG_TXP3 PEG_RXP3 (3)
PEG_TXN3 H37 PCIE_RX12N PCIE_TX12N K32 CPEG_RXN3 C5025 EV@0.1U/10V_4X
(3) PEG_TXN3 PEG_RXN3 (3)
PEG_TXP2 H35 PCIE_RX13P PCIE_TX13P J33 CPEG_RXP2 C5026 EV@0.1U/10V_4X

PEG_TXN2 G36 PCIE_RX13N PCIE_TX13N J32 CPEG_RXN2 C5027 EV@0.1U/10V_4X
PEG_TXP1 G38 PCIE_RX14P PCIE_TX14P K30 CPEG_RXP1 C5028 EV@0.1U/10V_4X

PEG_TXN1 F37 PCIE_RX14N PCIE_TX14N K29 CPEG_RXN1 C5029 EV@0.1U/10V_4X
PEG_TXP0 F35 PCIE_RX15P PCIE_TX15P H33 CPEG_RXP0 C5030 EV@0.1U/10V_4X

PEG_TXN0 E37 PCIE_RX15N PCIE_TX15N H32 CPEG_RXN0 C5031 EV@0.1U/10V_4X
CLOCK
(7) CLK_PCIE_VGAP AB35 PCIE_REFCLKP
(7) CLK_PCIE_VGAN AA36 PCIE_REFCLKN
CALIBRATION
PCIE_CALR_TX Y30 R5001 EV@1.27K/F_4
R5000 EV@10K_4 AH16 TEST_PG PCIE_CALR_RX Y29 R5002 EV@2K/F_4 +1V_GPU
(7) PERST#_BUF
R5037 EV@0_4 AA30 PERSTB Quanta Computer Inc.
EV@HEATHROW M2
PROJECT : BY7D
1A
Seymour_M2/ PEG*16
<VGA>
MUTI GFX
U5000B
PART 2 0F 9 14
(16) GENIL_CLK AD29 GENLK_CLK TXCAP_DPA3P AU24 EXT_HDMICLK+ (25)
(16) GENIL_VSYNC AC29 GENLK_VSYNC TXCAM_DPA3N AV23 EXT_HDMICLK- (25)
TX0P_DPA2P AT25 EXT_HDMITX0P (25)
AJ21 SWAPLOCKA
DPA
TX0M_DPA2N AR24 EXT_HDMITX0N (25)
AK21 SWAPLOCKB
TX1P_DPA1P AU26 EXT_HDMITX1P (25)
TX1M_DPA1N AV25 EXT_HDMITX1N (25)
AR8 DVPCNTL_MVP_0 TX2P_DPA0P AT27 EXT_HDMITX2P (25)
AU8 DVPCNTL_MVP_1 TX2M_DPA0N AR26 EXT_HDMITX2N (25)
AP8 DVPCNTL_0
AW8 DVPCNTL_1 TXCBP_DPB3P AR30
AR3 DVPCNTL_2 TXCBM_DPB3N AT29
AR1 DVPCLK
(16) RAM_STRAP0 AU1 DVPDATA_0 TX3P_DPB2P AV31

(16) RAM_STRAP1 AU3 DVPDATA_1 TX3M_DPB2N AU30
DPB
(16) RAM_STRAP2 AW3 DVPDATA_2
(16) RAM_STRAP3 AP6 DVPDATA_3 TX4P_DPB1P AR32

AW5 DVPDATA_4 TX4M_DPB1N AT31
AU5 DVPDATA_5
AR6 DVPDATA_6 TX5P_DPB0P AT33
1.8V GPIO AW6 DVPDATA_7 TX5M_DPB0N AU32
AU6 DVPDATA_8
AT7 DVPDATA_9 TXCCP_DPC3P AU14
AV7 DVPDATA_10 TXCCM_DPC3N AV13
AN7 DVPDATA_11
AV9 DVPDATA_12 TX0P_DPC2P AT15
AT9 DVPDATA_13 TX0M_DPC2N AR14
AR10 DVPDATA_14
DPC
AW10 DVPDATA_15 TX1P_DPC1P AU16
AU10 DVPDATA_16 TX1M_DPC1N AV15
AP10 DVPDATA_17
AV11 DVPDATA_18 TX2P_DPC0P AT17
AT11 DVPDATA_19 TX2M_DPC0N AR16
AR12 DVPDATA_20
+3V_GPU AW12 DVPDATA_21 TXCDP_DPD3P AU20
AU12 DVPDATA_22 TXCDM_DPD3N AT19
AP12 DVPDATA_23
R5005 EV@10K/F_4 GPU_SMBCLK TX3P_DPD2P AT21
R5004 EV@10K/F_4 GPU_SMBDAT TX3M_DPD2N AR20
Tempeature function: Connect to EC
DPD
(32) GPU_SMBCLK GPU_SMBCLK AJ23 SMBCLK TX4P_DPD1P AU22
SMBus
(32) GPU_SMBDAT GPU_SMBDAT AH23 SMBDATA TX4M_DPD1N AV21
<Layout Note>
TX5P_DPD0P AT23 Grounded right away.
TX5M_DPD0N AR22
R5006 EV@10K/F_4 GPU_SCL AK26 SCL
MUST NOT be connected to AVSSQ
+3V_GPU I2C
R5007 EV@10K/F_4 GPU_SDA AJ26 SDA
R AD39 EXT_CRT_RED (30)

GENERAL PURPOSE I/O AVSSN#1 AD37
(16) GPU_GPIO0 AH20 GPIO_0
(16) GPU_GPIO1 AH18 GPIO_1 G AE36 EXT_CRT_GRE (30)

(16) GPU_GPIO2 AN16 GPIO_2 AVSSN#2 AD35
B AF37 EXT_CRT_BLU (30)

R5133 EV@10K_4 AH17 GPIO_5_AC_BATT AVSSN#3 AE38
AJ17 GPIO_6
DAC1
R218 EV@0_4 AK17 GPIO_7_BLON HSYNC AC36 R495 R497 R498
(30) LVDS_BRIGHT EXT_CRT_HSYNC (16,30)
AJ13 GPIO_8_ROMSO VSYNC AC38 EV@150/F_4 EV@150/F_4 EV@150/F_4
(16) GPU_GPIO8 EXT_CRT_VSYNC (16,30)
(16) GPU_GPIO9 AH15 GPIO_9_ROMSI
(16) GPU_GPIO10 AJ16 GPIO_10_ROMSCK

AK16 GPIO_11 RSET AB34 R5011 EV@499/F_4
(16) GPU_GPIO11
(16) GPU_GPIO12 AL16 GPIO_12
AM16 GPIO_13 AVDD AD34 AVDD +1.8V_GPU
(16) GPU_GPIO13
(4,37) SYS_SHDN# AM14 GPIO_14_HPD2 AVSSQ AE34
AM13 GPIO_15_PWRCNTL_0 DAC1 Analog Power
(42) GFX_CORE_CNTRL0
3
AK14 GPIO_16 VDD1DI AC33 VDD1DI 1.8V@18mA

T5003 AG30 GPIO_17_THERMAL_INT VSS1DI AC34
Q24 AN14 GPIO_18_HPD3 AVDD L5000 EV@BLM15BD121SN1D_300MA
2 GPIO_19_CTF AM17 GPIO_19_CTF
AL13 GPIO_20_PWRCNTL_1 NC#1 V13 T5006
(42) GFX_CORE_CNTRL1
*ME2N7002E_200MA AJ14 GPIO_21 NC#2 U13 T5007 C5032 C5033 C5034
(16) GPU_GPIO21
AK13 GPIO_22_ROMCSB NC#3 AC31 T5008 EV@0.1U/10V_4X EV@1U/6.3V_4X EV@4.7U/6.3V_6X
(16) GPU_GPIO22
R226 AN13 CLKREQB NC#4 AD30 T5010
1
*EV@100K_4 NC#5 AC32 T5011

NC#6 AD32 T5012
T5013 AG32 GPIO_29 NC#7 AF32 T5014
T5015 AG33 GPIO_30 NC#8 AA29 T5016 DAC1 Digital Power
NC#9 AG21 T5017 1.8V@117mA
AJ19 GENERICA
AK19 GENERICB VDD1DI L5001 EV@BLM15BD121SN1D_300MA
(16) GPU_GENERICC AJ20 GENERICC
AK20 GENERICD
AJ24 GENERICE_HPD4 NC_TSVSSQ AF33 R5012 EV@0_4 NC_TSVSSQ should be tied C5035 C5036 C5037
AH26 GENERICF_HPD5 to GND on Thames/Whistler/Seymour EV@0.1U/10V_4X EV@1U/6.3V_4X EV@4.7U/6.3V_6X
AH24 GENERICG_HPD6
PS_0 AM34 R5013 EV@0_4 PS_0 should be tied to GND on

+1.8V_GPU Thames/Whistler/Seymour
T5024 AC30 CEC_1
(25) EXT_HDMI_HPD AK24 HPD1 PS_1 AD31

MLPS
R5014
EV@499/F_4
GPU_VREFG AH13 VREFG PS_2 AG31 PS_1,PS_2, PS_3 are NC on

Thames/Whistler/Seymour
R5015 C5038 BACO

EV@249/F_4 P _EN: leave unconnected if not used. AL21 PX_EN PS_3 AD33
EV@0.1U/10V_4X
(doesn't support switch-able graphics)
DEBUG DDC/AUX
DDC1CLK AM26 DDCCLK_AUX1P (25)
<Layout Note> AN26
close to chip R5018 EV@1K_4 AD28 TESTEN
DDC1DATA DDCDATA_AUX1N (25)
HDMI
AUX1P AM27 T5001
+3V_GPU R5019 *EV@5.11K/F_4 AUX1N AL27 T5036
T5063 AM23 JTAG_TRSTB DDC2CLK AM19 EXT_CRT_DDCCLK (30)

T5064 AN23 AL19
T5065 AK23
JTAG_TDI
JTAG_TCK
DDC2DATA
EXT_CRT_DDCDAT (30) CRT
T5066 AL24 JTAG_TMS AUX2P AN20
T5067 AM24 JTAG_TDO AUX2N AM20
DDCCLK_AUX3P AL30 T5000

DDCDATA_AUX3N AM30 T5035
THERMAL
DDCCLK_AUX4P AL29 T5002
T5037 AF29 DPLUS DDCDATA_AUX4N AM29 T5038
T5039 AG29 DMINUS
DDCCLK_AUX5P AN21
DDCDATA_AUX5N AM21
+3V_GPU R5020 EV@10K/F_4 AK32 GPIO_28_FDO
PU:Disable MLPS DDCCLK_AUX6P AK30
PD:Enable MLPS R5021 *EV@10K/F_4 AL31 TS_A DDCDATA_AUX6N AK29 Pin AL29,AM29,AK29,AK30 is NC on Seymour
1.8V@8mA
AJ30
+1.8V_GPU L5002 EV@BLM15BD121SN1D_300MA TSVDD AJ32 TSVDD
DDCVGACLK
DDCVGADATA AJ31
EV_LCD_EDIDCLK
EV_LCD_EDIDDATA
(30)
(30) LVDS
AJ33
on-die thermal sensor power C5039 C5040 C5041
TSVSS
EV@4.7U/6.3V_6X EV@1U/6.3V_4X EV@0.1U/10V_4X EV@HEATHROW M2
PROJECT : BY7D
1A
Seymour_M2/ GPIO_DP_CRT_I2C
<VGA>
15
Display phase-locked loop power.
1.8V@75mA Dedicated analog power pin for the display and DISPCLK PLLs.
+1.8V_GPU L5003 EV@PBY160808T-501Y-N_1.2A DPLL_PVDD
C5042 C5043 C5044

DPE/DPF/LVDS
U5000I
EV@4.7U/6.3V_6X EV@1U/6.3V_4X EV@0.1U/10V_4X
U5000G
PART 9 0F 9 PART 7 0F 9 R5022 EV@10K/F_4
VARY_BL AK27 EXT_DPST_PWM (30)

LVDS CONTROL DIGON AJ27 EV_LVDS_DIGON (30)
Display phase-locked loop power.
1V@140mA Dedicated digital power pin for the display PLLs. AM32 DPLL_PVDD XTALIN AV33 GPU_XTALIN C5045 EV@27P/50V_4N R5023 EV@10K/F_4
2
+1V_GPU L5004 EV@PBY160808T-501Y-N_1.2A DPLL_VDDC AN31 DPLL_VDDC
R5024 Y5000 TXCLK_UP_DPF3P AK35
C5046 C5047 C5048 EV@1M/F_4 EV@27MHZ_20 TXCLK_UN_DPF3N AL36
AN32 DPLL_PVSS
1
EV@4.7U/6.3V_6X EV@1U/6.3V_4X EV@0.1U/10V_4X TXOUT_U0P_DPF2P AJ38
XTALOUT AU34 GPU_XTALOUT R5025 EV@0_4 C5049 EV@27P/50V_4N TXOUT_U0N_DPF2N AK37
TXOUT_U1P_DPF1P AH35
TXOUT_U1N_DPF1N AJ36
Memory phase-locked loop power. H7 MPLL_PVDD
1.8V@150mA Dedicated analog power pin for the memory PLLs. H8 MPLL_PVDD TXOUT_U2P_DPF0P AG38
TXOUT_U2N_DPF0N AH37
+1.8V_GPU L5005 EV@PBY160808T-501Y-N_1.2A MPLL_PVDD XO_IN AW34 T5040
TXOUT_U3P AF35
C5050 C5051 C5052 AM10 SPLL_PVDD TXOUT_U3N AG36
LVTMDP
PLLS/XTAL
AN9 SPLL_VDDC XO_IN2 AW35 T5041

TXCLK_LP_DPE3P AP34 EV_LCD_TXLCLKOUT+ (30)
TXCLK_LN_DPE3N AR34 EV_LCD_TXLCLKOUT- (30)
Engine phase-locked loop power. AN10 SPLL_PVSS TXOUT_L0P_DPE2P AW37 EV_LCD_TXLOUT0+ (30)
1.8V@75mA Dedicated analog power pin for the engine and UVD PLLs. TXOUT_L0N_DPE2N AU35 EV_LCD_TXLOUT0- (30)
+1.8V_GPU L5006 EV@BLM15BD121SN1D_300MA SPLL_PVDD TXOUT_L1P_DPE1P AR37 EV_LCD_TXLOUT1+ (30)

CLKTESTA AK10 CLKTESTA TXOUT_L1N_DPE1N AU39 EV_LCD_TXLOUT1- (30)
C5053 C5054 C5055 AF30 NC_XTAL_PVDD CLKTESTB AL10 CLKTESTB
AF31 NC_XTAL_PVSS TXOUT_L2P_DPE0P AP35 EV_LCD_TXLOUT2+ (30)
EV@4.7U/6.3V_6X EV@1U/6.3V_4X EV@0.1U/10V_4X TXOUT_L2N_DPE0N AR35 EV_LCD_TXLOUT2- (30)
C5056 C5057 TXOUT_L3P AN36
*EV@0.1U/10V_4X *EV@0.1U/10V_4X TXOUT_L3N AP37
Engine phase-locked loop power.

1V@150mADedicated digital power pin for the engine and UVD PLLs. EV@HEATHROW M2
R5026 R5027
+1V_GPU L5007 EV@PBY160808T-501Y-N_1.2A SPLL_VDDC *EV@51.1/F_4 *EV@51.1/F_4 EV@HEATHROW M2
C5058 C5059 C5060
DPLL_PVDD R5028 *EV@0_4
R5029 *EV@0_4

PROJECT : BY7D
1A
Seymour_M2/ XTAL_LVDS
<VGA> +3V_GPU
(14) RAM_STRAP0
R5047
R5137
Sam@10K/F_4
AMD@10K/F_4
+1.8V_GPU
16
CONFIGURATION STRAPS -- SEE EACH DATABOOK FOR STRAP DETAILS
R5030 EV@10K/F_4 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
(14) GPU_GPIO0
THEY MUST NOT CONFLICT DURING RESET
R5031 EV@10K/F_4
(14) GPU_GPIO1
R5049 AMD@10K/F_4 +1.8V_GPU
(14) RAM_STRAP1 Default Setting
R5032 *EV@10K/F_4 STRAPS MLPS GPIO PIN DESCRIPTION OF DEFAULT SETTINGS
(14) GPU_GPIO2
R5050 Sam@10K/F_4
R5033 *EV@10K/F_4
(14) GPU_GPIO9
MLPS_DISABLE NA GPIO_28_FDO Enable MLPS, NA for Thames/Whistler/Seymour X
R5034 EV@10K/F_4 0: Enable MLPS, disable GPIO PINSTRAP
(14) GPU_GPIO11
1: Disable MLPS, enable GPIO PINSTRAP
R5035 *EV@10K/F_4
(14) GPU_GPIO12
R5051 2G@10K/F_4 +1.8V_GPU
(14) RAM_STRAP2
R5036 *EV@10K/F_4 TX_PWRS_ENB PS_1[4] GPIO0 Transmitter Power Savings Enable
(14) GPU_GPIO13
R5134 1GCA@10K/F_4 +1.8V_GPU 0: 50% Tx output swing X
R5038 *EV@10K/F_4 1: Full Tx output swing
(14) GPU_GPIO22
R5039 *EV@10K/F_4 R5052 512M@10K/F_4 TX_DEEMPH_EN PS_1[5] GPIO1 PCIE Transmitter De-emphasis Enable X
(14) GENIL_VSYNC
0: Tx de-emphasis disabled
R500 EV@10K/F_4 R5135 1GEB@10K/F_4 1: Tx de-emphasis enabled
(14,30) EXT_CRT_HSYNC
R499 EV@10K/F_4 BIF_GEN3_EN_A GPIO2 PCIE Gen3 Enable (NOTE: RESERVED for Thames/Whistler/Seymour) 1
(14,30) EXT_CRT_VSYNC PS_1[1]
0: GEN3 not supported at power-on
R5043 *EV@10K/F_4 1: GEN3 supported at power-on
(14) GENIL_CLK
R5044 *EV@10K/F_4 R5053 1GEB@10K/F_4 +1.8V_GPU BIF_VGA DIS GPIO9 VGA Control 0
(14) GPU_GPIO8 (14) RAM_STRAP3 PS_2[4]
0: VGA controller capacity enabled
R5045 *EV@10K/F_4 R5138 2G@10K/F_4 +1.8V_GPU
(14) GPU_GPIO21 1: VGA controller capacity disabled (for multi-GPU)
R5046 *EV@10K/F_4 R5054 512M@10K/F_4
(14) GPU_GENERICC
ROMIDCFG[2:0] PS_0[3..1] GPIO[13:11] Serial ROM type or Memory Aperture Size Select
R5145 *EV@10K/F_4 R5152 1GCA@10K/F_4
(14) GPU_GPIO10
If GPIO22 = 0, defines memory aperture size XXX
If GPIO22 = 1, defines ROM type
100 - 512Kbit M25P05A (ST)
101 - 1Mbit M25P10A (ST)
101 - 2Mbit M25P20 (ST)
101 - 4Mbit M25P40 (ST)
101 - 8Mbit M25P80 (ST)
100 - 512Kbit Pm25LV512 (Chingis)
101 - 1Mbit Pm25LV010 (Chingis)
BIOS_ROM_EN PS_2[3] GPIO22 Enable external BIOS ROM device X

0: Disabled
1: Enabled
AUD[1] NA HSYNC 00 - No audio function XX

AUD[0] NA VSYNC 01 - Audio for DP only
10 - Audio for DP and HDMI if dongle is detected
11 - Audio for both DP and HDMI
HDMI must only be enabled on systems that are legally entitled. It is the
responsibility of the system designer to ensure that the system is entitled to
support this feature.
DDR3 Memory TYPE
CEC_DIS PS_0[4] GENLK_VSYNC Enable CEC function. Reserved for Thames/Whistler/Seymour X
0: Disabled
1: Enabled
RAM_STRAP3 RAM_STRAP2 RAM_STRAP1 RAM_STRAP0

Vendor Vendor P/N STN B/S P/N Size
DVPDATA_3 DVPDATA_2 DVPDATA_1 DVPDATA_0 NOTE: ALLOW FOR PULLUP PADS FOR THE RESERVED STRAPS BUT DO NOT INSTALL RESISTOR
IF THESE GPIOS ARE USEED, THEY MUST KEEP LOW AND NOT CONFLICT DURING RESET
K4W1G1646G-BC11 RESERVED PS_1[3] GENLK_CLK Reserved 0
AKD5EGGT500 *4 512MB
(64M*16) 0 0 0 1 RESERVED
RESERVED
PS_1[2]
NA
GPIO8
GPIO21
Reserved
Reserved
0
0
RESERVED NA GENERICC Reserved (for Thames/Whistler/Seymour only) 0
K4W2G1646C-HC11
(128M*16,C-die) AKD5MGWT500 * 4 1GB 0 1 0 1 AUD_PORT_CONN_PINSTRAP[2] PS_3[5] NA STRAPS TO INDICATE THE NUMBER OF AUDIO CAPABLE DISPLAY OUTPUTS XXX
Samsung AUD_PORT_CONN_PINSTRAP[1] PS_3[4] NA 111 = 0 usable endpoints
NA 110 = 1 usable endpoints
K4W2G1646E-HC11 AUD_PORT_CONN_PINSTRAP[0] PS_0[5]
AKD5MGWT500 * 4 1GB 1 0 0 1 101 = 2 usable endpoints
100 = 3 usable endpoints
(128M*16,E-die) 011 = 4 usable endpoints
K4W2G1646C-HC11 2GB
(128M*16) AKD5MGWT500 * 8 1 1 0 1 000 = all endpoints are usable
23EY2387MC11 512MB
(64M*16) AKD5EZWT700 *4 0 0 1 0 System Memory Aperture size
EEPROM
23EY4187MA11 1GB 0 1 1 0 GPIO9 GPIO13 GPIO12 GPIO11
(128M*16,A-die) AKD5DZWT700 *4
BIOSROM ROMIDCFG2 ROMIDCFG1 ROMIDCFG0
AMD
23EY4187MB11 1GB 1 0 1 0 0 128M 0 0 0
(128M*16,B-die) TBD *4
0 256M 0 0 1
23EY4187MA11 2GB
(128M*16) AKD5DZWT700 *8 1 1 1 0 0 64M 0 1 0
0 32M 0 1 1
www.Teknisi-Indonesia.com Size
Date:
Document Number
PROJECT : BY7D
Seymour_M2/ STRAPS_Thermal
Monday, March 19, 2012 Sheet 16 of 45
Rev
1A
<VGA>
17
U5000E
PCIe IO power. +1.8V_GPU
PART 5 0F 9
+1.5V_GPU (1.8V@440mA)
(1.5V@2.2A / DDR3 128bits 900MHz) MEM I/O
AC7 VDDR1 NC_PCIE_VDDR AA31 PCIE_VDDR L5008 EV@HCB1608KF-181T15_1.5A
AD11 VDDR1 NC_PCIE_VDDR AA32
AF7 VDDR1 NC_PCIE_VDDR AA33
C5062 C5063 C5064 C5065 AG10 VDDR1 NC_PCIE_VDDR AA34 C5066 C5067 C5068 C5069 C5070
EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X AJ7 VDDR1 NC_PCIE_VDDR W30 EV@0.1U/10V_4X EV@0.1U/10V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@4.7U/6.3V_6X
AK8 VDDR1 NC_PCIE_VDDR Y31
AL9 VDDR1 NC_BIF_VDDC V28
G11 VDDR1 NC_BIF_VDDC W29
G14 VDDR1 PCIE_PVDD AB37
PCIE
G17 VDDR1
G20 VDDR1 PCIE_VDDC G30
C5071 C5084 C5072 C5073 C5074 C5085 C5075 G23 VDDR1 PCIE_VDDC G31 PCIe digital power supply. +1V_GPU
EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X G26 VDDR1 PCIE_VDDC H29
G29 VDDR1 PCIE_VDDC H30
H10 VDDR1 PCIE_VDDC J29
J7 VDDR1 PCIE_VDDC J30
J9 VDDR1 PCIE_VDDC L28 C5076 C5077 C5078 C5079 C5086 C5087
K11 VDDR1 PCIE_VDDC M28 EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@4.7U/6.3V_6X
K13 VDDR1 PCIE_VDDC N28
C5080 C5081 C5082 C5083 K8 VDDR1 PCIE_VDDC R28
EV@0.1U/10V_4X EV@0.1U/10V_4X EV@0.1U/10V_4X EV@0.1U/10V_4X L12 VDDR1 PCIE_VDDC T28
L16 VDDR1 PCIE_VDDC U28
L21 VDDR1
+VGPU_CORE Non-BACO design
L23 VDDR1
(BY7 doesn't support switch-able graphics)
L26 VDDR1 BIF_VDDC N27
BACO
L7 VDDR1 BIF_VDDC T27
M11 VDDR1 Separate core power for the PCIe bus logic.
C5088 C5089 C5090 C5091 N11 VDDR1 C5092 C5093 In non-BACO designs, connect to VDDC.
EV@0.1U/10V_4X EV@0.1U/10V_4X EV@0.1U/10V_4X EV@0.1U/10V_4X P7 VDDR1 VDDC AA15 EV@1U/6.3V_4X EV@4.7U/6.3V_6X In BACO designs, must be the same voltage as VDDC when the GPU is operating,
CORE
R11 VDDR1 VDDC AA17
U11 VDDR1 VDDC AA20
U7 VDDR1 VDDC AA22
Y11 VDDR1 VDDC AA24
Y7 VDDR1 VDDC AA27 Dedicated core power, provides power to the internal logic.
VDDC AB16 +VGPU_CORE
Level translation between core and I/O, VDDC AB18 (0.9~1V@30A)
excluding memory receivers. VDDC AB21
VDDC AB23
(1.8V@17mA) LEVEL VDDC AB26
TRANSLATION VDDC AB28 C5094 C5095 C5096 C5097 C5098
+1.8V_GPU L5009 EV@BLM15BD121SN1D_300MA VDDC_CT AF26 VDD_CT VDDC AC17 EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X
AF27 VDD_CT VDDC AC20
AG26 VDD_CT VDDC AC22
C5099 C5100 C5101 AG27 VDD_CT VDDC AC24
I/O power for 3.3-V pins, such as GPIOs. EV@4.7U/6.3V_6X EV@1U/6.3V_4X EV@0.1U/10V_4X VDDC AC27
VDDC AD18
(3.3V@60mA) I/O VDDC AD21
+3V_GPU AF23 VDDR3 VDDC AD23
L5010 EV@FCM1005KF-221T03_300MA VDDR3 AF24 VDDR3 VDDC AD26
AG23 VDDR3 VDDC AF17 C5102 C5103 C5104 C5105 C5106 C5107 C5108 C5109 C5110 C5111
AG24 VDDR3 VDDC AF20 EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X
C5112 C5113 C5114 VDDC AF22
EV@4.7U/6.3V_6X EV@1U/6.3V_4X EV@1U/6.3V_4X DVP VDDC AG16
AD12 VDDR4 VDDC AG18
AF11 VDDR4
Power for all DVP pins; DVPDATA_[23:0]—DVO or GPIO. AF12 VDDR4 VDDC AH22
(1.8V@170mA) AF13 VDDR4 VDDC AH27
VDDC AH28
+1.8V_GPU L5011 EV@FCM1005KF-221T03_300MA VDDR4 VDDC M26
AF15 VDDR4 VDDC N24 C5115 C5116 C5117 C5118 C5119 C5120 C5121 C5122 C5123 C5124
AG11 VDDR4 VDDC R18 EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X
C5125 C5126 C5127 AG13 VDDR4 VDDC R21
EV@4.7U/6.3V_6X EV@1U/6.3V_4X EV@0.1U/10V_4X AG15 VDDR4 VDDC R23
VDDC R26
VDDC T17
VDDC T20
VDDC T22
VDDC T24
VDDC U16
VDDC U18
VDDC U21
VDDC U23
VDDC U26
VDDC V17
VDDC V20
VDDC V22
VDDC V24
VDDC V27 Isolated (clean) core power for the l/O logic.
VDDC Y16
VDDC Y18 (0.9V~1V@3.8A / DDR3 128bits 900MHz)
VDDC Y21 +VGPU_CORE
VDDC Y23
VDDC Y26
VDDC Y28 L5012 EV@HCB1608KF-121T30_3A
VDDCI AA13 VDDCI L5013 EV@HCB1608KF-121T30_3A

VDDCI AB13
VDDCI AC12
VDDCI AC15 C5128 C5129 C5130 C5131
VDDCI AD13 EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X
VDDCI AD16
VDDCI M15
<Layout Note> VDDCI M16
route as differtial pair. VOLTAGE
VDDCI M18
SENESE
VDDCI M23
CORE I/O
VDDCI N13
ISOLATED
R9532 EV@0_4 AF28 FB_VDDC VDDCI N15

(42) VCORE_VCCSSENSE
VDDCI N17 C5132 C5133 C5134 C5135 C5136 C5137
VDDCI N20 EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X
AG28 FB_VDDCI VDDCI N22
VDDCI R12
VDDCI R13
R9533 EV@0_4 AH29 R16
(42) VCORE_VSSSENSE FB_GND VDDCI
VDDCI T12 Quanta Computer Inc.
VDDCI T15
VDDCI V15 PROJECT : BY7D
VDDCI Y13
1A
EV@HEATHROW M2
Seymour_M2/ MainPower
<VGA>
For Thames/Whistler/Seymour
For Thames/Whistler/Seymour
a dedicated BEAD is required

18
a dedicated BEAD is required
for each DPAB_VDD10, DPCD_VDD10, DPEF_VDD10
for each DPAB_VDD18, DPCD_VDD18, DPEF_VDD18
DP/TMDS/LVDS Transmitter Power
0.935V@222mA per port
U5000H
PART 8 0F 9
(1V@222mA)
DPAB_VDD10 L5014 EV@PBY160808T-501Y-N_1.2A +1V_GPU
DP_VDDR DP_VDDC
DP/TMDS/LVDS Transmitter Power DP_VDDC AP31 C5141 C5142 C5143

DP_VDDC AP32
DP mode: 1.8V@188mA per port DP_VDDC AN33 EV@4.7U/6.3V_6X EV@1U/6.3V_4X EV@0.1U/10V_4X
HDMI mode: 1.8V@237mA per port DP_VDDC AP33
AN24 DP_VDDR (1V@222mA)
(1.8V@237mA) AP24 DP_VDDR DP_VDDC AP13
AP25 DP_VDDR DP_VDDC AT13 DPCD_VDD10 L5016 EV@PBY160808T-501Y-N_1.2A +1V_GPU
+1.8V_GPU L5015 EV@PBY160808T-501Y-N_1.2A DPAB_VDD18 AP26 DP_VDDR DP_VDDC AP14
AU28 DP_VDDR DP_VDDC AP15 C5144 C5145 C5146
AV29 DP_VDDR
C5138 C5139 C5140 DP_VDDC AL33 EV@4.7U/6.3V_6X EV@1U/6.3V_4X EV@0.1U/10V_4X
EV@4.7U/6.3V_6X EV@1U/6.3V_4X EV@0.1U/10V_4X DP_VDDC AM33
AP20 DP_VDDR DP_VDDC AK33 (1V@222mA)
AP21 DP_VDDR DP_VDDC AK34
(1.8V@237mA) AP22 DP_VDDR DPEF_VDD10 L5017 EV@PBY160808T-501Y-N_1.2A +1V_GPU
AP23 DP_VDDR
+1.8V_GPU L5018 EV@PBY160808T-501Y-N_1.2A DPCD_VDD18 AU18 DP_VDDR C5147 C5148 C5149

AV19 DP_VDDR
DP GND
C5150 C5151 C5152 DP_VSSR AN27
EV@4.7U/6.3V_6X EV@1U/6.3V_4X EV@0.1U/10V_4X AH34 DP_VDDR DP_VSSR AP27
AJ34 DP_VDDR DP_VSSR AP28
(1.8V@237mA) AF34 DP_VDDR DP_VSSR AW24
AG34 DP_VDDR DP_VSSR AW26
AM37 DP_VDDR DP_VSSR AN29
+1.8V_GPU L5019 EV@PBY160808T-501Y-N_1.2A DPEF_VDD18 AL38 DP_VDDR DP_VSSR AP29
DP_VSSR AP30
DP_VSSR AW30
C5153 C5154 C5155 DP_VSSR AW32
EV@4.7U/6.3V_6X EV@1U/6.3V_4X EV@0.1U/10V_4X DP_VSSR AN17
DP_VSSR AP16
DP_VSSR AP17
DP_VSSR AW14
DP_VSSR AW16
DP_VSSR AN19
DP_VSSR AP18
DP_VSSR AP19
CALIBRATION
DP_VSSR AW20
DP_VSSR AW22
DP_VSSR AN34
DP_VSSR AP39
R5057 EV@150/F_4 AW28 DPAB_CALR DP_VSSR AR39
DP_VSSR AU37
DP_VSSR AF39
DP_VSSR AH39
R5058 EV@150/F_4 AW18 DPCD_CALR DP_VSSR AK39
DP_VSSR AL34
DP_VSSR AV27
DP_VSSR AR28
R5059 EV@150/F_4 AM39 DPEF_CALR DP_VSSR AV17
DP_VSSR AR18
DP_VSSR AN38
DP_VSSR AM35
EV@HEATHROW M2

PROJECT : BY7D
1A
Seymour_M2/ DP_Powers
<VGA>
PART 6 0F 9
U5000F
19
AB39 PCIE_VSS GND A3
E39 PCIE_VSS GND A37
F34 PCIE_VSS GND AA16
F39 PCIE_VSS GND AA18
G33 PCIE_VSS GND AA2
G34 PCIE_VSS GND AA21
H31 PCIE_VSS GND AA23
J31 PCIE_VSS GND AA6
J34 PCIE_VSS GND AB12
K31 PCIE_VSS GND AB15
L31 PCIE_VSS GND AB22
L34 PCIE_VSS GND AB24
M34 PCIE_VSS GND AB27
M39 PCIE_VSS GND AC11
N31 PCIE_VSS GND AC13
N34 PCIE_VSS GND AC16
P31 PCIE_VSS GND AC18
R34 PCIE_VSS GND AC23
T31 PCIE_VSS GND AC26
U31 PCIE_VSS GND AD15
U34 PCIE_VSS GND AD17
V34 PCIE_VSS GND AD20
V39 PCIE_VSS GND AD22
W31 PCIE_VSS GND AD24
W34 PCIE_VSS GND AD27
Y34 PCIE_VSS GND AD9
Y39 PCIE_VSS GND AE2
GND AE6
GND AF10
GND AF16
GND AF18
GND GND AF21
GND AG17
F15 GND GND AG2
F17 GND GND AG20
F19 GND GND AG22
F21 GND GND AG6
F23 GND GND AG9
F25 GND GND AH21
F27 GND GND AJ10
F29 GND GND AJ11
F31 GND GND AJ2
F33 GND GND AJ28
F7 GND GND AJ6
F9 GND GND AK11
G2 GND GND AK31
G6 GND GND AK7
H9 GND GND AL11
J2 GND GND AL14
J27 GND GND AL17
J6 GND GND AL2
J8 GND GND AL20
K14 GND
K7 GND GND AL23
L11 GND GND AL26
L17 GND GND AL32
L2 GND GND AL6
L22 GND GND AL8
L24 GND GND AM11
L6 GND GND AM31
M17 GND GND AM9
M22 GND GND AN11
M24 GND GND AN2
N16 GND GND AN30
N18 GND GND AN6
N2 GND GND AN8
N21 GND GND AP11
N23 GND GND AP7
N26 GND GND AP9
N6 GND GND AR5
R15 GND GND B11
R17 GND GND B13
R2 GND GND B15
R20 GND GND B17
R22 GND GND B19
R24 GND GND B21
R27 GND GND B23
R6 GND GND B25
T11 GND GND B27
T13 GND GND B29
T16 GND GND B31
T18 GND GND B33
T21 GND GND B7
T23 GND GND B9
T26 GND GND C1
U15 GND GND C39
U17 GND GND E35
U2 GND GND E5
U20 GND GND F11
U22 GND GND F13
U24 GND
U27 GND
U6 GND
V11 GND
V16 GND
V18 GND
V21 GND
V23 GND
V26 GND
W2 GND
W6 GND
Y15 GND
Y17 GND
Y20 GND
Y22 GND VSS_MECH A39
Y24 GND VSS_MECH AW1
Y27 GND VSS_MECH AW39
EV@HEATHROW M2
PROJECT : BY7D
1A
Seymour_M2/ GND
<VGA>
(22) VMB_DQ[63..0]
(22) VMB_DM[7..0]
VMB_DQ[63..0]
VMB_DM[7..0]
U5000D
20
U5000C
VMB_RDQS[7..0]
(22) VMB_RDQS[7..0] PART 4 0F 9
PART 3 0F 9 VMB_WDQS[7..0]
VMA_DQ[63..0] (22) VMB_WDQS[7..0] GDDR5/DDR3
GDDR5/DDR3 VMB_DQ0 C5 DQB0_0 MAB0_0/MAB_0 P8 VMB_MA0
(21) VMA_DQ[63..0] VMB_MA[14..0]
VMA_DQ0 C37 DQA0_0 MAA0_0/MAA_0 G24 VMA_MA0 VMB_DQ1 C3 DQB0_1 MAB0_1/MAB_1 T9 VMB_MA1
VMA_DM[7..0] (22) VMB_MA[14..0]
VMA_DQ1 C35 DQA0_1 MAA0_1/MAA_1 J23 VMA_MA1 VMB_DQ2 E3 DQB0_2 MAB0_2/MAB_2 P9 VMB_MA2
(21) VMA_DM[7..0]
VMA_DQ2 A35 DQA0_2 MAA0_2/MAA_2 H24 VMA_MA2 VMB_DQ3 E1 DQB0_3 MAB0_3/MAB_3 N7 VMB_MA3
VMA_RDQS[7..0] VMA_DQ3 E34 DQA0_3 MAA0_3/MAA_3 J24 VMA_MA3 VMB_DQ4 F1 DQB0_4 MAB0_4/MAB_4 N8 VMB_MA4
(21) VMA_RDQS[7..0]
VMA_DQ4 G32 DQA0_4 MAA0_4/MAA_4 H26 VMA_MA4 VMB_BA0 VMB_DQ5 F3 DQB0_5 MAB0_5/MAB_5 N9 VMB_MA5
VMA_WDQS[7..0] (22) VMB_BA0
VMA_DQ5 D33 DQA0_5 MAA0_5/MAA_5 J26 VMA_MA5 VMB_BA1 VMB_DQ6 F5 DQB0_6 MAB0_6/MAB_6 U9 VMB_MA6
(21) VMA_WDQS[7..0] (22) VMB_BA1
VMA_DQ6 F32 DQA0_6 MAA0_6/MAA_6 H21 VMA_MA6 VMB_BA2 VMB_DQ7 G4 DQB0_7 MAB0_7/MAB_7 U8 VMB_MA7
(22) VMB_BA2
VMA_DQ7 E32 DQA0_7 MAA0_7/MAA_7 G21 VMA_MA7 VMB_DQ8 H5 DQB0_8 MAB1_0/MAB_8 Y9 VMB_MA8
VMA_DQ8 D31 H19 VMA_MA8 VMB_DQ9 H6 W9 VMB_MA9
MEMORY INTERFACE A
DQA0_8 MAA1_0/MAA_8 DQB0_9 MAB1_1/MAB_9
VMA_MA[14..0] VMA_DQ9 F30 DQA0_9 MAA1_1/MAA_9 H20 VMA_MA9 VMB_DQ10 J4 DQB0_10 MAB1_2/MAB_10 AC8 VMB_MA10
(21) VMA_MA[14..0]
VMA_DQ10 C30 DQA0_10 MAA1_2/MAA_10 L13 VMA_MA10 VMB_DQ11 K6 DQB0_11 MAB1_3/MAB_11 AC9 VMB_MA11
VMA_DQ11 A30 DQA0_11 MAA1_3/MAA_11 G16 VMA_MA11 VMB_DQ12 K5 DQB0_12 MAB1_4/MAB_12 AA7 VMB_MA12
VMA_BA0 VMA_DQ12 F28 DQA0_12 MAA1_4/MAA_12 J16 VMA_MA12 VMB_DQ13 L4 DQB0_13 MAB1_5/BA2 AA8 VMB_BA2
(21) VMA_BA0
VMA_BA1 VMA_DQ13 C28 DQA0_13 MAA1_5/MAA_BA2 H16 VMA_BA2 VMB_DQ14 M6 DQB0_14 MAB1_6/BA0 Y8 VMB_BA0
(21) VMA_BA1
VMA_BA2 VMA_DQ14 A28 DQA0_14 MAA1_6/MAA_BA0 J17 VMA_BA0 VMB_DQ15 M1 DQB0_15 MAB1_7/BA1 AA9 VMB_BA1
(21) VMA_BA2
VMA_DQ15 E28 DQA0_15 MAA1_7/MAA_BA1 H17 VMA_BA1 VMB_DQ16 M3 DQB0_16
MEMORY INTERFACE B
VMA_DQ16 D27 DQA0_16 VMB_DQ17 M5 DQB0_17 WCKB0_0/DQMB_0 H3 VMB_DM0
VMA_DQ17 F26 DQA0_17 WCKA0_0/DQMA_0 A32 VMA_DM0 VMB_DQ18 N4 DQB0_18 WCKB0B_0/DQMB_1 H1 VMB_DM1
VMA_DQ18 C26 DQA0_18 WCKA0B_0/DQMA_1 C32 VMA_DM1 VMB_DQ19 P6 DQB0_19 WCKB0_1/DQMB_2 T3 VMB_DM2
VMA_DQ19 A26 DQA0_19 WCKA0_1/DQMA_2 D23 VMA_DM2 VMB_DQ20 P5 DQB0_20 WCKB0B_1/DQMB_3 T5 VMB_DM3
VMA_DQ20 F24 DQA0_20 WCKA0B_1/DQMA_3 E22 VMA_DM3 VMB_DQ21 R4 DQB0_21 WCKB1_0/DQMB_4 AE4 VMB_DM4
VMA_DQ21 C24 DQA0_21 WCKA1_0/DQMA_4 C14 VMA_DM4 VMB_DQ22 T6 DQB0_22 WCKB1B_0/DQMB_5 AF5 VMB_DM5
VMA_DQ22 A24 DQA0_22 WCKA1B_0/DQMA_5 A14 VMA_DM5 VMB_DQ23 T1 DQB0_23 WCKB1_1/DQMB_6 AK6 VMB_DM6
VMA_DQ23 E24 DQA0_23 WCKA1_1/DQMA_6 E10 VMA_DM6 VMB_DQ24 U4 DQB0_24 WCKB1B_1/DQMB_7 AK5 VMB_DM7
VMA_DQ24 C22 DQA0_24 WCKA1B_1/DQMA_7 D9 VMA_DM7 VMB_DQ25 V6 DQB0_25
VMA_DQ25 A22 DQA0_25 VMB_DQ26 V1 DQB0_26 EDCB0_0/QSB_0 F6 VMB_RDQS0
VMA_DQ26 F22 DQA0_26 EDCA0_0/QSA_0 C34 VMA_RDQS0 VMB_DQ27 V3 DQB0_27 EDCB0_1/QSB_1 K3 VMB_RDQS1
VMA_DQ27 D21 DQA0_27 EDCA0_1/QSA_1 D29 VMA_RDQS1 VMB_DQ28 Y6 DQB0_28 EDCB0_2/QSB_2 P3 VMB_RDQS2
VMA_DQ28 A20 DQA0_28 EDCA0_2/QSA_2 D25 VMA_RDQS2 VMB_DQ29 Y1 DQB0_29 EDCB0_3/QSB_3 V5 VMB_RDQS3 QSB[7..0]
VMA_DQ29 F20 DQA0_29 EDCA0_3/QSA_3 E20 VMA_RDQS3 VMB_DQ30 Y3 DQB0_30 EDCB1_0/QSB_4 AB5 VMB_RDQS4
VMA_DQ30 D19 DQA0_30 EDCA1_0/QSA_4 E16 VMA_RDQS4 VMB_DQ31 Y5 DQB0_31 EDCB1_1/QSB_5 AH1 VMB_RDQS5
VMA_DQ31 E18 DQA0_31 EDCA1_1/QSA_5 E12 VMA_RDQS5 VMB_DQ32 AA4 DQB1_0 EDCB1_2/QSB_6 AJ9 VMB_RDQS6
VMA_DQ32 C18 DQA1_0 EDCA1_2/QSA_6 J10 VMA_RDQS6 VMB_DQ33 AB6 DQB1_1 EDCB1_3/QSB_7 AM5 VMB_RDQS7
VMA_DQ33 A18 DQA1_1 EDCA1_3/QSA_7 D7 VMA_RDQS7 VMB_DQ34 AB1 DQB1_2
VMA_DQ34 F18 DQA1_2 VMB_DQ35 AB3 DQB1_3 DDBIB0_0/QSB_0B G7 VMB_WDQS0
VMA_DQ35 D17 DQA1_3 DDBIA0_0/QSA_0B A34 VMA_WDQS0 VMB_DQ36 AD6 DQB1_4 DDBIB0_1/QSB_1B K1 VMB_WDQS1
VMA_DQ36 A16 DQA1_4 DDBIA0_1/QSA_1B E30 VMA_WDQS1 VMB_DQ37 AD1 DQB1_5 DDBIB0_2/QSB_2B P1 VMB_WDQS2
VMA_DQ37 F16 DQA1_5 DDBIA0_2/QSA_2B E26 VMA_WDQS2 VMB_DQ38 AD3 DQB1_6 DDBIB0_3/QSB_3B W4 VMB_WDQS3 QSB#[7..0]
VMA_DQ38 D15 DQA1_6 DDBIA0_3/QSA_3B C20 VMA_WDQS3 VMB_DQ39 AD5 DQB1_7 DDBIB1_0/QSB_4B AC4 VMB_WDQS4
VMA_DQ39 E14 DQA1_7 DDBIA1_0/QSA_4B C16 VMA_WDQS4 VMB_DQ40 AF1 DQB1_8 DDBIB1_1/QSB_5B AH3 VMB_WDQS5
VMA_DQ40 F14 DQA1_8 DDBIA1_1/QSA_5B C12 VMA_WDQS5 VMB_DQ41 AF3 DQB1_9 DDBIB1_2/QSB_6B AJ8 VMB_WDQS6
VMA_DQ41 D13 DQA1_9 DDBIA1_2/QSA_6B J11 VMA_WDQS6 VMB_DQ42 AF6 DQB1_10 DDBIB1_3/QSB_7B AM3 VMB_WDQS7
VMA_DQ42 F12 DQA1_10 DDBIA1_3/QSA_7B F8 VMA_WDQS7 VMB_DQ43 AG4 DQB1_11
VMA_DQ43 A12 DQA1_11 VMB_DQ44 AH5 DQB1_12 ADBIB0/ODTB0 T7 VMB_ODT0 (22)
VMA_DQ44 D11 DQA1_12 ADBIA0/ODTA0 J21 VMB_DQ45 AH6 DQB1_13 ADBIB1/ODTB1 W7
VMA_ODT0 (21) VMB_ODT1 (22)
VMA_DQ45 F10 DQA1_13 ADBIA1/ODTA1 G19 VMB_DQ46 AJ4 DQB1_14
VMA_ODT1 (21)
VMA_DQ46 A10 DQA1_14 VMB_DQ47 AK3 DQB1_15 CLKB0 L9 VMB_CLK0
VMB_CLK0 (22)
VMA_DQ47 C10 DQA1_15 CLKA0 H27 VMA_CLK0 VMB_DQ48 AF8 DQB1_16 CLKB0B L8 VMB_CLK0#
VMA_CLK0 (21) VMB_CLK0# (22)
VMA_DQ48 G13 DQA1_16 CLKA0B G27 VMA_CLK0# VMB_DQ49 AF9 DQB1_17
VMA_CLK0# (21)
VMA_DQ49 H13 DQA1_17 VMB_DQ50 AG8 DQB1_18 CLKB1 AD8 VMB_CLK1 VMB_CLK1 (22)
VMA_DQ50 J13 DQA1_18 CLKA1 J14 VMA_CLK1 VMB_DQ51 AG7 DQB1_19 CLKB1B AD7 VMB_CLK1#
VMA_CLK1 (21) VMB_CLK1# (22)
VMA_DQ51 H11 DQA1_19 CLKA1B H14 VMA_CLK1# VMB_DQ52 AK9 DQB1_20
VMA_CLK1# (21)
VMA_DQ52 G10 DQA1_20 VMB_DQ53 AL7 DQB1_21 RASB0B T10 VMB_RAS0# VMB_RAS0# (22)
Place MVREF dividers and Caps close to ASIC VMA_DQ53 G8 DQA1_21 RASA0B K23 VMA_RAS0# VMB_DQ54 AM8 DQB1_22 RASB1B Y10 VMB_RAS1#
VMA_RAS0# (21) VMB_RAS1# (22)
VMA_DQ54 K9 DQA1_22 RASA1B K19 VMA_RAS1# Place MVREF dividers and Caps close to ASIC VMB_DQ55 AM7 DQB1_23
VMA_RAS1# (21)
VMA_DQ55 K10 DQA1_23 VMB_DQ56 AK1 DQB1_24 CASB0B W10 VMB_CAS0# VMB_CAS0# (22)
VMA_DQ56 G9 DQA1_24 CASA0B K20 VMA_CAS0# VMB_DQ57 AL4 DQB1_25 CASB1B AA10 VMB_CAS1#
VMA_CAS0# (21) VMB_CAS1# (22)
+1.5V_GPU VMA_DQ57 A8 DQA1_25 CASA1B K17 VMA_CAS1# +1.5V_GPU VMB_DQ58 AM6 DQB1_26
VMA_CAS1# (21)
VMA_DQ58 C8 DQA1_26 VMB_DQ59 AM1 DQB1_27 CSB0B_0 P10 VMB_CS0# VMB_CS0# (22)
(0.7*VDDR1) VMA_DQ59 E8 DQA1_27 CSA0B_0 K24 VMA_CS0# (0.7*VDDR1) VMB_DQ60 AN4 DQB1_28 CSB0B_1 L10
VMA_CS0# (21)
VMA_DQ60 A6 DQA1_28 CSA0B_1 K27 VMB_DQ61 AP3 DQB1_29
VMA_DQ61 C6 DQA1_29 VMB_DQ62 AP1 DQB1_30 CSB1B_0 AD10 VMB_CS1# VMB_CS1# (22)
Ra R5060 VMA_DQ62 E6 DQA1_30 CSA1B_0 M13 VMA_CS1# Ra R5061 VMB_DQ63 AP5 DQB1_31 CSB1B_1 AC10
VMA_CS1# (21)
EV@40.2/F_4 VMA_DQ63 A5 DQA1_31 CSA1B_1 K16 EV@40.2/F_4
CKEB0 U10 VMB_CKE0 VMB_CKE0 (22)
MVREFDA L18 MVREFDA CKEA0 K21 VMA_CKE0 MVREFDB Y12 MVREFDB CKEB1 AA11 VMB_CKE1
VMA_CKE0 (21) VMB_CKE1 (22)
MVREFSA L20 MVREFSA CKEA1 J20 VMA_CKE1 MVREFSB AA12 MVREFSB
VMA_CKE1 (21)
WEB0B N10 VMB_WE0# VMB_WE0# (22)
+1.5V_GPU R5063 Thames@243/F_4 L27 NC_MEM_CALRN0 WEA0B K26 VMA_WE0# VMA_WE0# (21) WEB1B AB11 VMB_WE1# VMB_WE1# (22)
Rb R5062 C5156 R5065 Seymour@243/F_4 N12 NC_MEM_CALRN1 WEA1B L15 VMA_WE1# Rb R5064 C5157
VMA_WE1# (21)
EV@100/F_4 EV@1U/6.3V_4X R5066 Thames@243/F_4 AG12 NC_MEM_CALRN2 EV@100/F_4 EV@1U/6.3V_4X
MAB0_8/MAB_13 T8 VMB_MA13
R5067 Seymour@243/F_4 M12 NC_MEM_CALRP1 MAA0_8/MAA_13 H23 VMA_MA13 MAB1_8/MAB_14 W8 VMB_MA14
R5068 Thames@243/F_4 M27 MEM_CALRP0 MAA1_8/MAA_14 J19 VMA_MA14 MAB0_9/MAB_15 U12
R5069 Thames@243/F_4 AH12 MEM_CALRP2 MAA0_9/MAA_15 M21 MAB1_9/RSVD V12
MAA1_9/RSVD M20
+1.5V_GPU +1.5V_GPU DRAM_RST AH11 GPU_DRAM_RST
(0.7*VDDR1) (0.7*VDDR1)
EV@HEATHROW M2
Ra R5070 Ra R5071
EV@40.2/F_4 EV@HEATHROW M2 EV@40.2/F_4
Rb R5072 C5158
Ball Name Thames Seymour Rb R5073 C5159
EV@100/F_4 EV@1U/6.3V_4X EV@100/F_4 EV@1U/6.3V_4X
MEM_CALRN0 243R X 25mm (max) 5mm (max) 25mm (max)
GPU_DRAM_RST R5074 EV@10/F_4 R5075 EV@51/F_4

MEM_CALRN1 X 243R MEM_RST# (21,22)
<B3A_20120213>
C5160
MEM_CALRN2 243R X R5076
change R5075 value to 51/F_4
EV@4.99K/F_4 EV@120P/50V_4N
MEM_CALRP0 243R X
MEM_CALRP1 X 243R
MEM_CALRP2 243R X Place all these componets very close to GPU (within 25mm)
and keep all components close to each other
** This basic topology should be used for DRAM_RAT for DDR3/GDDR5
These Capacitors and Resistor values arre an example only

The series R and || cap values will depend on the DRAM loads
and will have to be calculated for differrent Memory, DRAM loads and board
to pass Reset Signal Spec
www.Teknisi-Indonesia.com Size
Date:
Document Number
PROJECT : BY7D
Seymour_M2/ MEM Interface
Wednesday, March 21, 2012 Sheet 20 of 45
Rev
1A
5 4 3 2 1
VMA_DQ[63..0]
CHANNEL A: 512MB DDR3 (64M*16*4pcs) <VGA>
21
(20) VMA_DQ[63..0]
VMA_DM[7..0]
(20) VMA_DM[7..0]
VMA_RDQS[7..0] QSA[7..0]
(20) VMA_RDQS[7..0]
VMA_WDQS[7..0] QSA#[7..0]
(20) VMA_WDQS[7..0]
U5004 U5005
VMA_MA[14..0] U5002 U5003
(20) VMA_MA[14..0]
VREFC_VMA3 M8 E3 VMA_DQ54 VREFC_VMA4 M8 E3 VMA_DQ46
VREFC_VMA1 VMA_DQ5 VREFC_VMA2 VMA_DQ12 VREFD_VMA3 VREFCA DQL0 VMA_DQ50 VREFD_VMA4 VREFCA DQL0 VMA_DQ45
M8 E3 M8 E3 H1 F7 H1 F7
VREFD_VMA1 VREFCA DQL0 VMA_DQ0 VREFD_VMA2 VREFCA DQL0 VMA_DQ14 VREFDQ DQL1 VMA_DQ53 VREFDQ DQL1 VMA_DQ44
H1 F7 H1 F7 F2 F2
VREFDQ DQL1 VMA_DQ6 VREFDQ DQL1 VMA_DQ8 VMA_MA0 DQL2 VMA_DQ49 VMA_MA0 DQL2 VMA_DQ40
F2 F2 N3 F8 N3 F8
VMA_MA0 N3
DQL2
F8 VMA_DQ1 VMA_MA0 N3
DQL2
F8 VMA_DQ11 VMA_MA1 P7
A0 DQL3
H3 VMA_DQ52 6 VMA_MA1 P7
A0 DQL3
H3 VMA_DQ41 5
(20)
(20)
VMA_MA0
VMA_MA1
VMA_MA1 P7
A0
A1
DQL3
DQL4
A0
A1
DQL3
DQL4
A1
A2
DQL4
DQL5
H8 VMA_DQ51 VMA_MA2 P3
A1
A2
DQL4
DQL5
H8 VMA_DQ42
VMA_MA2 P3 H8 VMA_DQ3 VMA_MA2 P3 H8 VMA_DQ15 VMA_MA3 N2 G2 VMA_DQ55 VMA_MA3 N2 G2 VMA_DQ43
(20) VMA_MA2 A2 DQL5 A2 DQL5 A3 DQL6 A3 DQL6
VMA_MA3 N2 G2 VMA_DQ7 VMA_MA3 N2 G2 VMA_DQ9 VMA_MA4 P8 H7 VMA_DQ48 VMA_MA4 P8 H7 VMA_DQ47
D (20) VMA_MA3 A3 DQL6 A3 DQL6 A4 DQL7 A4 DQL7 D
VMA_MA4 P8 H7 VMA_DQ2 VMA_MA4 P8 H7 VMA_DQ13 VMA_MA5 P2 VMA_MA5 P2
(20) VMA_MA4 A4 DQL7 A4 DQL7 A5 A5
VMA_MA5 P2 VMA_MA5 P2 VMA_MA6 R8 VMA_MA6 R8
(20) VMA_MA5 A5 A5 A6 A6
VMA_MA6 R8 VMA_MA6 R8 VMA_MA7 R2 D7 VMA_DQ32 VMA_MA7 R2 D7 VMA_DQ61
(20) VMA_MA6 A6 A6 A7 DQU0 A7 DQU0
VMA_MA7 R2 D7 VMA_DQ24 VMA_MA7 R2 D7 VMA_DQ20 VMA_MA8 T8 C3 VMA_DQ36 VMA_MA8 T8 C3 VMA_DQ58
(20) VMA_MA7 A7 DQU0 A7 DQU0 A8 DQU1 A8 DQU1
VMA_MA8 T8 C3 VMA_DQ31 VMA_MA8 T8 C3 VMA_DQ19 VMA_MA9 R3 C8 VMA_DQ33 VMA_MA9 R3 C8 VMA_DQ63
VMA_MA9 R3 C8 VMA_DQ27 VMA_MA9 R3 C8 VMA_DQ23 VMA_MA10 L7 C2 VMA_DQ37 VMA_MA10 L7 C2 VMA_DQ56
(20) VMA_MA9
VMA_MA10 L7
A9 DQU2
C2 VMA_DQ28 VMA_MA10 L7
A9 DQU2
C2 VMA_DQ17 VMA_MA11 R7
A10/AP DQU3
A7 VMA_DQ34 4 VMA_MA11 R7
A10/AP DQU3
A7 VMA_DQ60 7
(20)
(20)
VMA_MA10
VMA_MA11
VMA_MA11 R7
A10/AP
A11
DQU3
DQU4
A7 VMA_DQ25 3 VMA_MA11 R7
A10/AP
A11
DQU3
DQU4
A7 VMA_DQ22 2 VMA_MA12 N7
A11
A12/BC
DQU4
DQU5
A2 VMA_DQ39 VMA_MA12 N7
A11
A12/BC
DQU4
DQU5
A2 VMA_DQ59
VMA_MA12 N7 A2 VMA_DQ29 VMA_MA12 N7 A2 VMA_DQ16 VMA_MA13 T3 B8 VMA_DQ35 VMA_MA13 T3 B8 VMA_DQ62
(20) VMA_MA12 A12/BC DQU5 A12/BC DQU5 A13 DQU6 A13 DQU6
VMA_MA13 T3 B8 VMA_DQ26 VMA_MA13 T3 B8 VMA_DQ21 VMA_MA14 T7 A3 VMA_DQ38 VMA_MA14 T7 A3 VMA_DQ57
VMA_MA14 T7 A3 VMA_DQ30 VMA_MA14 T7 A3 VMA_DQ18 M7 M7
(20) VMA_MA14 A14 DQU7 A14 DQU7 A15 A15
M7 M7 +1.5V_GPU +1.5V_GPU
A15 +1.5V_GPU A15 +1.5V_GPU
VMA_BA0 M2 B2 VMA_BA0 M2 B2
VMA_BA0 VMA_BA0 VMA_BA1 BA0 VDD#B2 VMA_BA1 BA0 VDD#B2
(20) VMA_BA0 M2 B2 M2 B2 N8 D9 N8 D9
VMA_BA1 BA0 VDD#B2 VMA_BA1 BA0 VDD#B2 VMA_BA2 BA1 VDD#D9 VMA_BA2 BA1 VDD#D9
(20) VMA_BA1 N8 D9 N8 D9 M3 G7 M3 G7
VMA_BA2 BA1 VDD#D9 VMA_BA2 BA1 VDD#D9 BA2 VDD#G7 BA2 VDD#G7
(20) VMA_BA2 M3 G7 M3 G7 K2 K2
BA2 VDD#G7 BA2 VDD#G7 VDD#K2 VDD#K2
K2 K2 K8 K8
VDD#K2 VDD#K2 VDD#K8 VDD#K8
K8 K8 N1 N1
VDD#K8 VDD#K8 VMA_CLK1 VDD#N1 VMA_CLK1 VDD#N1
N1 N1 (20) VMA_CLK1 J7 N9 J7 N9
VMA_CLK0 VDD#N1 VMA_CLK0 VDD#N1 VMA_CLK1# CK VDD#N9 VMA_CLK1# CK VDD#N9
(20) VMA_CLK0 J7 N9 J7 N9 (20) VMA_CLK1# K7 R1 K7 R1
VMA_CLK0# CK VDD#N9 VMA_CLK0# CK VDD#N9 VMA_CKE1 CK VDD#R1 VMA_CKE1 CK VDD#R1
(20) VMA_CLK0# K7 R1 K7 R1 (20) VMA_CKE1 K9 R9 K9 R9
VMA_CKE0 CK VDD#R1 VMA_CKE0 CK VDD#R1 CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU
(20) VMA_CKE0 K9 R9 K9 R9
CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU
VMA_ODT1 K1 A1 VMA_ODT1 K1 A1
(20) VMA_ODT1 ODT VDDQ#A1 ODT VDDQ#A1
VMA_ODT0 K1 A1 VMA_ODT0 K1 A1 VMA_CS1# L2 A8 VMA_CS1# L2 A8
(20) VMA_ODT0 ODT VDDQ#A1 ODT VDDQ#A1 (20) VMA_CS1# CS VDDQ#A8 CS VDDQ#A8
VMA_CS0# L2 A8 VMA_CS0# L2 A8 VMA_RAS1# J3 C1 VMA_RAS1# J3 C1
(20) VMA_CS0# CS VDDQ#A8 CS VDDQ#A8 (20) VMA_RAS1# RAS VDDQ#C1 RAS VDDQ#C1
VMA_RAS0# J3 C1 VMA_RAS0# J3 C1 VMA_CAS1# K3 C9 VMA_CAS1# K3 C9
(20) VMA_RAS0# RAS VDDQ#C1 RAS VDDQ#C1 (20) VMA_CAS1# CAS VDDQ#C9 CAS VDDQ#C9
VMA_CAS0# K3 C9 VMA_CAS0# K3 C9 VMA_WE1# L3 D2 VMA_WE1# L3 D2
(20) VMA_CAS0# CAS VDDQ#C9 CAS VDDQ#C9 (20) VMA_WE1# WE VDDQ#D2 WE VDDQ#D2
VMA_WE0# L3 D2 VMA_WE0# L3 D2 E9 E9
(20) VMA_WE0# WE VDDQ#D2 WE VDDQ#D2 VDDQ#E9 VDDQ#E9
E9 E9 F1 F1
VDDQ#E9 VDDQ#E9 VMA_RDQS6 VDDQ#F1 VMA_RDQS5 VDDQ#F1
F1 F1 F3 H2 F3 H2
VMA_RDQS0 VDDQ#F1 VMA_RDQS1 VDDQ#F1 VMA_RDQS4 DQSL VDDQ#H2 VMA_RDQS7 DQSL VDDQ#H2
F3 H2 F3 H2 C7 H9 C7 H9
VMA_RDQS3 DQSL VDDQ#H2 VMA_RDQS2 DQSL VDDQ#H2 DQSU VDDQ#H9 DQSU VDDQ#H9
C7 H9 C7 H9
DQSU VDDQ#H9 DQSU VDDQ#H9
VMA_DM6 E7 A9 VMA_DM5 E7 A9
VMA_DM0 VMA_DM1 VMA_DM4 DML VSS#A9 VMA_DM7 DML VSS#A9
E7 A9 E7 A9 D3 B3 D3 B3
VMA_DM3 DML VSS#A9 VMA_DM2 DML VSS#A9 DMU VSS#B3 DMU VSS#B3
C D3 B3 D3 B3 E1 E1 C
DMU VSS#B3 DMU VSS#B3 VSS#E1 VSS#E1
E1 E1 G8 G8
VSS#E1 VSS#E1 VMA_WDQS6 VSS#G8 VMA_WDQS5 VSS#G8
G8 G8 G3 J2 G3 J2
VMA_WDQS0 VSS#G8 VMA_WDQS1 VSS#G8 VMA_WDQS4 DQSL VSS#J2 VMA_WDQS7 DQSL VSS#J2
G3 J2 G3 J2 B7 J8 B7 J8
VMA_WDQS3 DQSL VSS#J2 VMA_WDQS2 DQSL VSS#J2 DQSU VSS#J8 DQSU VSS#J8
B7 J8 B7 J8 M1 M1
DQSU VSS#J8 DQSU VSS#J8 VSS#M1 VSS#M1
M1 M1 M9 M9
VSS#M1 VSS#M1 VSS#M9 VSS#M9
M9 M9 P1 P1
VSS#M9 VSS#M9 MEM_RST# VSS#P1 MEM_RST# VSS#P1
P1 P1 T2 P9 T2 P9
MEM_RST# VSS#P1 MEM_RST# VSS#P1 RESET VSS#P9 RESET VSS#P9
T2 P9 T2 P9 T1 T1
(20,22) MEM_RST# RESET VSS#P9 RESET VSS#P9 VMA_ZQ3 VSS#T1 VMA_ZQ4 VSS#T1
T1 T1 L8 T9 L8 T9
VMA_ZQ1 VSS#T1 VMA_ZQ2 VSS#T1 ZQ VSS#T9 ZQ VSS#T9
L8 T9 L8 T9
ZQ VSS#T9 ZQ VSS#T9
B1 B1
VSSQ#B1 VSSQ#B1
B1 B1 B9 B9
VSSQ#B1 VSSQ#B1 R5079 VSSQ#B9 R5080 VSSQ#B9
B9 B9 D1 D1
R5077 VSSQ#B9 R5078 VSSQ#B9 Thames@243/F_4 VSSQ#D1 Thames@243/F_4 VSSQ#D1
D1 D1 D8 D8
Thames@243/F_4 VSSQ#D1 Thames@243/F_4 VSSQ#D1 VSSQ#D8 VSSQ#D8
D8 D8 E2 E2
VSSQ#D8 VSSQ#D8 VSSQ#E2 VSSQ#E2
E2 E2 J1 E8 J1 E8
VSSQ#E2 VSSQ#E2 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8
J1 E8 J1 E8 L1 F9 L1 F9
NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9
L1 F9 L1 F9 J9 G1 J9 G1
NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1
J9 G1 J9 G1 L9 G9 L9 G9
NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
L9 G9 L9 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 100-BALL 100-BALL
100-BALL 100-BALL SDRAM DDR3 SDRAM DDR3
SDRAM DDR3 SDRAM DDR3 Thames@VRAM _DDR3 Thames@VRAM _DDR3
Thames@VRAM _DDR3 Thames@VRAM _DDR3
TOP Left BOT Left TOP Right BOT Right

Group-A0 VREF Group-A1 VREF
+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU
+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU
B B
R5081 R5082 R5083 R5084
Thames@4.99K/F_4 Thames@4.99K/F_4 Thames@4.99K/F_4 Thames@4.99K/F_4 R5085 R5086 R5087 R5088
Thames@4.99K/F_4 Thames@4.99K/F_4 Thames@4.99K/F_4 Thames@4.99K/F_4
VREFC_VMA1 VREFD_VMA1 VREFC_VMA2 VREFD_VMA2

VREFC_VMA3 VREFD_VMA3 VREFC_VMA4 VREFD_VMA4
R5089 C5161 R5090 C5162 R5091 C5163 R5092 C5164

R5093 C5165 R5094 C5166 R5095 C5167 R5096 C5168
Thames@4.99K/F_4 Thames@0.1U/10V_4X Thames@4.99K/F_4 Thames@0.1U/10V_4X Thames@4.99K/F_4 Thames@0.1U/10V_4X Thames@4.99K/F_4 Thames@0.1U/10V_4X
Thames@4.99K/F_4 Thames@0.1U/10V_4X Thames@4.99K/F_4 Thames@0.1U/10V_4X Thames@4.99K/F_4 Thames@0.1U/10V_4X Thames@4.99K/F_4 Thames@0.1U/10V_4X
Group-A0 decoupling CAP Group-A1 decoupling CAP

MEM_A0 CLK
+1.5V_GPU MEM_A1 CLK
+1.5V_GPU
VMA_CLK0 VMA_CLK1
VMA_CLK0# C5172 C5173 C5174 C5175 C5176 C5177 C5183 C5184 VMA_CLK1#
C5169 C5170 C5171 C5178 C5179 C5180 C5181 C5182 Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X
Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X
R5097 R5098
Thames@56.2/F_4 Thames@56.2/F_4 R5099 R5100
+1.5V_GPU Thames@56.2/F_4 Thames@56.2/F_4
+1.5V_GPU
C5189 C5190 C5191 C5192 C5193 C5194 C5195 C5201 C5202

Thames@0.01U/25V_4X C5186 C5187 C5188 C5196 C5197 C5198 C5199 C5200 Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X C5185
A Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@1U/6.3V_4X Thames@0.01U/25V_4X A
+1.5V_GPU
+1.5V_GPU
C5208 C5209 C5210 C5211 C5212

C5203 C5204 C5205 C5206 C5207 Thames@4.7U/6.3V_6X Thames@4.7U/6.3V_6X Thames@4.7U/6.3V_6X Thames@4.7U/6.3V_6X Thames@4.7U/6.3V_6X
Thames@4.7U/6.3V_6X Thames@4.7U/6.3V_6X Thames@4.7U/6.3V_6X Thames@4.7U/6.3V_6X Thames@4.7U/6.3V_6X Quanta Computer Inc.
PROJECT : BY7D
1A
VRAM_A: DDR3*4PCS
5 4 3 2 1
5 4 3 2 1
CHANNEL B: 512MB DDR3 (64M*16*4pcs)

(20) VMB_DQ[63..0]
(20) VMB_DM[7..0]
(20) VMB_RDQS[7..0]
VMB_DQ[63..0]
VMB_DM[7..0]
VMB_RDQS[7..0]
VMB_WDQS[7..0]
QSA[7..0]
<VGA>
22
(20) VMB_WDQS[7..0] QSA#[7..0]
U5006 U5007 U5008 U5009
VMB_MA[14..0]
(20) VMB_MA[14..0]
VREFC_VMB1 M8 E3 VMB_DQ23 VREFC_VMB2 M8 E3 VMB_DQ1 VREFC_VMB3 M8 E3 VMB_DQ55 VREFC_VMB4 M8 E3 VMB_DQ62
VREFD_VMB1 VREFCA DQL0 VMB_DQ16 VREFD_VMB2 VREFCA DQL0 VMB_DQ4 VREFD_VMB3 VREFCA DQL0 VMB_DQ51 VREFD_VMB4 VREFCA DQL0 VMB_DQ61
H1 F7 H1 F7 H1 F7 H1 F7
VREFDQ DQL1 VMB_DQ21 VREFDQ DQL1 VMB_DQ2 VREFDQ DQL1 VMB_DQ54 VREFDQ DQL1 VMB_DQ63
F2 F2 F2 F2
VMB_MA0 N3
DQL2
F8 VMB_DQ17 2 VMB_MA0 N3
DQL2
F8 VMB_DQ5 0 VMB_MA0 N3
DQL2
F8 VMB_DQ50 VMB_MA0 N3
DQL2
F8 VMB_DQ60
(20)
(20)
VMB_MA0
VMB_MA1
VMB_MA1 P7
A0
A1
DQL3
DQL4
H3 VMB_DQ22 VMB_MA1 P7
A0
A1
DQL3
DQL4
H3 VMB_DQ0 VMB_MA1 P7
A0
A1
DQL3
DQL4
H3 VMB_DQ52 6 VMB_MA1 P7
A0
A1
DQL3
DQL4
H3 VMB_DQ59 7
VMB_MA2 P3 H8 VMB_DQ19 VMB_MA2 P3 H8 VMB_DQ7 VMB_MA2 P3 H8 VMB_DQ49 VMB_MA2 P3 H8 VMB_DQ58
(20) VMB_MA2 A2 DQL5 A2 DQL5 A2 DQL5 A2 DQL5
VMB_MA3 N2 G2 VMB_DQ20 VMB_MA3 N2 G2 VMB_DQ3 VMB_MA3 N2 G2 VMB_DQ53 VMB_MA3 N2 G2 VMB_DQ57
D (20) VMB_MA3 A3 DQL6 A3 DQL6 A3 DQL6 A3 DQL6 D
VMB_MA4 P8 H7 VMB_DQ18 VMB_MA4 P8 H7 VMB_DQ6 VMB_MA4 P8 H7 VMB_DQ48 VMB_MA4 P8 H7 VMB_DQ56
(20) VMB_MA4 A4 DQL7 A4 DQL7 A4 DQL7 A4 DQL7
VMB_MA5 P2 VMB_MA5 P2 VMB_MA5 P2 VMB_MA5 P2
(20) VMB_MA5 A5 A5 A5 A5
VMB_MA6 R8 VMB_MA6 R8 VMB_MA6 R8 VMB_MA6 R8
(20) VMB_MA6 A6 A6 A6 A6
VMB_MA7 R2 D7 VMB_DQ26 VMB_MA7 R2 D7 VMB_DQ15 VMB_MA7 R2 D7 VMB_DQ41 VMB_MA7 R2 D7 VMB_DQ38
(20) VMB_MA7 A7 DQU0 A7 DQU0 A7 DQU0 A7 DQU0
VMB_MA8 T8 C3 VMB_DQ30 VMB_MA8 T8 C3 VMB_DQ10 VMB_MA8 T8 C3 VMB_DQ47 VMB_MA8 T8 C3 VMB_DQ32
VMB_MA9 R3 C8 VMB_DQ28 VMB_MA9 R3 C8 VMB_DQ14 VMB_MA9 R3 C8 VMB_DQ40 VMB_MA9 R3 C8 VMB_DQ36
(20) VMB_MA9
VMB_MA10 L7
A9 DQU2
C2 VMB_DQ31 3 VMB_MA10 L7
A9 DQU2
C2 VMB_DQ8 1 VMB_MA10 L7
A9 DQU2
C2 VMB_DQ46 VMB_MA10 L7
A9 DQU2
C2 VMB_DQ33
(20)
(20)
VMB_MA10
VMB_MA11
VMB_MA11 R7
A10/AP
A11
DQU3
DQU4
A7 VMB_DQ24 VMB_MA11 R7
A10/AP
A11
DQU3
DQU4
A7 VMB_DQ12 VMB_MA11 R7
A10/AP
A11
DQU3
DQU4
A7 VMB_DQ44 5 VMB_MA11 R7
A10/AP
A11
DQU3
DQU4
A7 VMB_DQ37 4
VMB_MA12 N7 A2 VMB_DQ27 VMB_MA12 N7 A2 VMB_DQ9 VMB_MA12 N7 A2 VMB_DQ45 VMB_MA12 N7 A2 VMB_DQ35
(20) VMB_MA12 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5
VMB_MA13 T3 B8 VMB_DQ25 VMB_MA13 T3 B8 VMB_DQ13 VMB_MA13 T3 B8 VMB_DQ43 VMB_MA13 T3 B8 VMB_DQ39
VMB_MA14 T7 A3 VMB_DQ29 VMB_MA14 T7 A3 VMB_DQ11 VMB_MA14 T7 A3 VMB_DQ42 VMB_MA14 T7 A3 VMB_DQ34
M7 M7 M7 M7
A15 +1.5V_GPU A15 +1.5V_GPU A15 +1.5V_GPU A15 +1.5V_GPU
VMB_BA0 M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2

(20) VMB_BA0 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2
VMB_BA1 N8 D9 VMB_BA1 N8 D9 VMB_BA1 N8 D9 VMB_BA1 N8 D9
(20) VMB_BA1 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
VMB_BA2 M3 G7 VMB_BA2 M3 G7 VMB_BA2 M3 G7 VMB_BA2 M3 G7
(20) VMB_BA2 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
K8 K8 K8 K8
N1 N1 N1 N1
VMB_CLK0 VDD#N1 VMB_CLK0 VDD#N1 VMB_CLK1 VDD#N1 VMB_CLK1 VDD#N1
(20) VMB_CLK0 J7 N9 J7 N9 (20) VMB_CLK1 J7 N9 J7 N9
VMB_CLK0# CK VDD#N9 VMB_CLK0# CK VDD#N9 VMB_CLK1# CK VDD#N9 VMB_CLK1# CK VDD#N9
(20) VMB_CLK0# K7 R1 K7 R1 (20) VMB_CLK1# K7 R1 K7 R1
VMB_CKE0 CK VDD#R1 VMB_CKE0 CK VDD#R1 VMB_CKE1 CK VDD#R1 VMB_CKE1 CK VDD#R1
(20) VMB_CKE0 K9 R9 K9 R9 (20) VMB_CKE1 K9 R9 K9 R9
CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU
VMB_ODT0 K1 A1 VMB_ODT0 K1 A1 VMB_ODT1 K1 A1 VMB_ODT1 K1 A1

(20) VMB_ODT0 ODT VDDQ#A1 ODT VDDQ#A1 (20) VMB_ODT1 ODT VDDQ#A1 ODT VDDQ#A1
VMB_CS0# L2 A8 VMB_CS0# L2 A8 VMB_CS1# L2 A8 VMB_CS1# L2 A8
(20) VMB_CS0# CS VDDQ#A8 CS VDDQ#A8 (20) VMB_CS1# CS VDDQ#A8 CS VDDQ#A8
VMB_RAS0# J3 C1 VMB_RAS0# J3 C1 VMB_RAS1# J3 C1 VMB_RAS1# J3 C1
(20) VMB_RAS0# RAS VDDQ#C1 RAS VDDQ#C1 (20) VMB_RAS1# RAS VDDQ#C1 RAS VDDQ#C1
VMB_CAS0# K3 C9 VMB_CAS0# K3 C9 VMB_CAS1# K3 C9 VMB_CAS1# K3 C9
(20) VMB_CAS0# CAS VDDQ#C9 CAS VDDQ#C9 (20) VMB_CAS1# CAS VDDQ#C9 CAS VDDQ#C9
VMB_WE0# L3 D2 VMB_WE0# L3 D2 VMB_WE1# L3 D2 VMB_WE1# L3 D2
(20) VMB_WE0# WE VDDQ#D2 WE VDDQ#D2 (20) VMB_WE1# WE VDDQ#D2 WE VDDQ#D2
E9 E9 E9 E9
VDDQ#E9 VDDQ#E9 VDDQ#E9 VDDQ#E9
F1 F1 F1 F1
VMB_RDQS2 VDDQ#F1 VMB_RDQS0 VDDQ#F1 VMB_RDQS6 VDDQ#F1 VMB_RDQS7 VDDQ#F1
F3 H2 F3 H2 F3 H2 F3 H2
VMB_RDQS3 DQSL VDDQ#H2 VMB_RDQS1 DQSL VDDQ#H2 VMB_RDQS5 DQSL VDDQ#H2 VMB_RDQS4 DQSL VDDQ#H2
C7 H9 C7 H9 C7 H9 C7 H9
DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9
VMB_DM2 E7 A9 VMB_DM0 E7 A9 VMB_DM6 E7 A9 VMB_DM7 E7 A9

VMB_DM3 DML VSS#A9 VMB_DM1 DML VSS#A9 VMB_DM5 DML VSS#A9 VMB_DM4 DML VSS#A9
C D3 B3 D3 B3 D3 B3 D3 B3 C
DMU VSS#B3 DMU VSS#B3 DMU VSS#B3 DMU VSS#B3
E1 E1 E1 E1
VSS#E1 VSS#E1 VSS#E1 VSS#E1
G8 G8 G8 G8
VMB_WDQS2 VSS#G8 VMB_WDQS0 VSS#G8 VMB_WDQS6 VSS#G8 VMB_WDQS7 VSS#G8
G3 J2 G3 J2 G3 J2 G3 J2
VMB_WDQS3 DQSL VSS#J2 VMB_WDQS1 DQSL VSS#J2 VMB_WDQS5 DQSL VSS#J2 VMB_WDQS4 DQSL VSS#J2
B7 J8 B7 J8 B7 J8 B7 J8
DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8
M1 M1 M1 M1
M9 M9 M9 M9
P1 P1 P1 P1
MEM_RST# VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1
T2 P9 T2 P9 T2 P9 T2 P9
(20,21) MEM_RST# RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
VMB_ZQ1 VSS#T1 VMB_ZQ2 VSS#T1 VMB_ZQ3 VSS#T1 VMB_ZQ4 VSS#T1
L8 T9 L8 T9 L8 T9 L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
B1 B1 B1 B1
VSSQ#B1 VSSQ#B1 VSSQ#B1 VSSQ#B1
B9 B9 B9 B9
R5101 VSSQ#B9 R5102 VSSQ#B9 R5103 VSSQ#B9 R5104 VSSQ#B9
D1 D1 D1 D1
EV@243/F_4 VSSQ#D1 EV@243/F_4 VSSQ#D1 EV@243/F_4 VSSQ#D1 EV@243/F_4 VSSQ#D1
D8 D8 D8 D8
VSSQ#D8 VSSQ#D8 VSSQ#D8 VSSQ#D8
E2 E2 E2 E2
VSSQ#E2 VSSQ#E2 VSSQ#E2 VSSQ#E2
J1 E8 J1 E8 J1 E8 J1 E8
NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8
L1 F9 L1 F9 L1 F9 L1 F9
NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9
J9 G1 J9 G1 J9 G1 J9 G1
NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1
L9 G9 L9 G9 L9 G9 L9 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
EV@VRAM _DDR3 EV@VRAM _DDR3 EV@VRAM _DDR3 EV@VRAM _DDR3
TOP Up BOT Up TOP Down BOT Down
Group-B0 VREF Group-B1 VREF

+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU
B B
R5105 R5106 R5107 R5108 R5109 R5110 R5111 R5112

EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4
VREFC_VMB1 VREFD_VMB1 VREFC_VMB2 VREFD_VMB2 VREFC_VMB3 VREFD_VMB3 VREFC_VMB4 VREFD_VMB4
R5113 C5213 R5114 C5214 R5115 C5215 R5116 C5216 R5117 C5217 R5118 C5218 R5119 C5219 R5120 C5220
EV@4.99K/F_4 EV@0.1U/10V_4X EV@4.99K/F_4 EV@0.1U/10V_4X EV@4.99K/F_4 EV@0.1U/10V_4X EV@4.99K/F_4 EV@0.1U/10V_4X EV@4.99K/F_4 EV@0.1U/10V_4X EV@4.99K/F_4 EV@0.1U/10V_4X EV@4.99K/F_4 EV@0.1U/10V_4X EV@4.99K/F_4 EV@0.1U/10V_4X
Group-B0 decoupling CAP Group-B1 decoupling CAP

MEM_B0 CLK MEM_B1 CLK
+1.5V_GPU +1.5V_GPU
VMB_CLK1
VMB_CLK0 C5221 C5222 C5223 C5224 C5225 C5226 C5227 C5228 C5229 C5230 C5231 C5232 C5233 C5234 C5235 VMB_CLK1#
VMB_CLK0# EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X
R5121 R5122
R5123 R5124 EV@56.2/F_4 EV@56.2/F_4

+1.5V_GPU +1.5V_GPU
EV@56.2/F_4 EV@56.2/F_4
A C5238 C5239 C5240 C5241 C5242 C5243 C5244 C5245 C5246 C5247 C5248 C5249 C5250 C5251 C5252 A
C5236
C5237 EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@0.01U/25V_4X
EV@0.01U/25V_4X
+1.5V_GPU +1.5V_GPU
C5253 C5254 C5255 C5256 C5257 C5258 C5259 C5260 C5261 C5262 Quanta Computer Inc.
EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X EV@4.7U/6.3V_6X
PROJECT : BY7D
1A
VRAM_B: DDR3*4PCS
5 4 3 2 1
5 4 3 2 1
Non-BACO design
(Brazos doesn't support Muxless Switch-able Graphics)
23
D D
C C
B B
A A

PROJECT : BY7D
Seymour_M2/ Baco 1A
Date: Tuesday, March 06, 2012 Sheet 23 of 45
5 4 3 2 1
5 4 3 2 1
USB 3.0 Power switch <USB> <U3B>
+3V_S5 +5V_S5
USB w S&C MAXIM solution
+5V_S5
C133
S&C@0.1U/10V_4X
<SLC>
U5
S&C@MAX14600ETA+T USBP10+_R1
USBP10-_R1
R331
R323
NS&C@0_4
NS&C@0_4
24
<B3A_20120130> 5 6 USB_S&C_RR R329 S&C@0_4 USBP10+
VCC TDP USBP10+ (6)
<B3A_20120130> R71 14617@10K_4 7 USB_S&C#_RR R321 S&C@0_4 USBP10-
R262 U4
reserve 1206 package cap R69 14617@0_4 TDM USBP10- (6)
change to 100K ohm 100K_4 +5VSUS_USBP1 (34) USB_BUS_SW4 USB_BUS_SW3 R62 14566@0_4
2 8 (34) USB_BUS_SW3 1
(for leakage issue) IN1 OUT3 CB1(CEN#)
3 7 (34) USB_BUS_SW2 8
IN2 OUT2 CB USB_S&C_R R313 S&C@0_4 USBP10+_R2
6 3
USB_SC_EN# OUT1 C127 C128 + C130 C131 C136 R338 DP USB_S&C#_R R307 S&C@0_4 USBP10-_R2
(34) USB_SC_EN# 4 EN# DM 2
1
GND *470P/50V_4X *0.1U/10V_4X 100U/6.3V_3528P_E45b *10U/6.3V_8X *100U/6.3V_1206 470/F_4 USBP10+_R1 R308 NS&C@0_4
9 5
C132 GND-C OC# USBP10-_R1 R311 NS&C@0_4
D
9 GND GND 4 D
UP7534BRA8-15
1U/16V_6X R59 146XX@0_4 USB_BUS_SW3
3
USB_SC_OC# R53 14566@0_4
USB_SC_OC# (6,34)
Q18
ME2N7002E_200MA <C3B_20120321>
stuff for USB discharger 14617
1
14566/14600
CB0 CB1 CB2 Status
CB0 CB1 Status
X X 1 Force Apple 2A Charger Mode
0 0 Auto mode
0 0 0 Autodetection charger mode
0 1 Force dedicated charger mode
0 1 0 Force-Dedicated Charger Mode
R69 R62 R59 R53 R71 1 X Pass-Through(USB) mode:
Connect DP/DM to TDP/TDM for 14566 1 0 0 USB Pass-Through Mode
14566 V V Connect DP/DM to TDP/TDM
14600 V 1 0 Pass-Through(USB) mode for 14600 USB Pass-Through Mode with CDP
14617(with CB2) V V 1 1 pass-through(USB) with CDP 1 1 0 Emulation.Auto connect DP/DM to
Emulation for 14600 TDP/TDM depending on CDP status
14617(no CB2) V V
USB 3.0 CONN RIGHT <U3B> <USB> <EMI> <U3B> <U2B>

<20111207_Lincan> USB 2.0 CONN RIGHT
reserve for external USB port.
<B3A_20120202>
CN22
change to short pad
C309 *10P/50V_4C R397 *300_4 CN1
6
RP1 +5VSUS_USBP1 1
USBP10-_R2 USBP10-_CN 1 VBUS +5VSUS_USBP1
<C3B_20120313> 2 1 2
2 D- 1
C USBP10+_R2 4 3 USBP10+_CN 3 USBP10-_CN C
del L2 for layout request 3 D+ USBP10+_CN 2
4
USB3_RXN0 R30 UR3@0_4 USB30_RX0- *0X2_short 4 GND D24 3
(6) USB3_RXN0 5
USB3_RXP0 R31 UR3@0_4 USB30_RX0+ 5 SSRX- 4
(6) USB3_RXP0 6 6 *UR2@AZ5125-01J
7 SSRX+
7 GND
5
USB3_TXN0 R32 UR3@0_4 USB30_TX0-_R1 C134 UR3@0.1U/10V_4X USB30_TX0-_C 8 UR2@UARCF-4K1986
(6) USB3_TXN0 8 SSTX-
(6) USB3_TXP0 USB3_TXP0 R33 UR3@0_4 USB30_TX0+_R1 C135 UR3@0.1U/10V_4X USB30_TX0+_C 9
9 SSTX+
13
12
11
10
ESD1
USB30_TX0+_C 1 10 USB30_TX0-_C
13
12
11
10
+5VSUS_USBP1 1 10 UR3@TARAH-9V1391
2 VDD GND 9 USB3.0 UR-3@TARAH-9V1391
3 8 USB2.0 UR-2@UARCF-4K1986
USBP10-_CN NC NC1 USBP10+_CN
4 7
USB30_RX0+ 4 7 USB30_RX0-
5 6
5 6
*UR3@AZ1065-06F
USB3.0 DFHS09FR085 ULU3@TARA9-9V1391

USB 3.0 Power switch USB CONN LEFT UP USB2.0 DFHS04FR487 ULU2@UARC6-4K1926
<B3A_20120202>
+USB_RE_PWR <20111207_Lincan>
C308 *ULU@10P/50V_4C R393 *ULU@300_4
change to short pad CN2
reserve for external USB port. RP2 *0X2_short +5VSUS_USBP0 1 VBUS
USBP11- USBP11-_R 1
(6) USBP11- 3 4 2 D-
USBP11+ USBP11+_R 2
(6) USBP11+ 1 2 3 3
R550 R559 R561 R565 R570 R41 *ULU3@4.7K_4 D+
+USB_RE_PWR 4
*ULU3@4.7K_4 *ULU3@4.7K_4 *ULU3@4.7K_4 *ULU3@4.7K_4 R569 *ULU3@4.7K_4 USB3_RXN1_RE R34 ULU3@0_4 USB30_RX1- 4 GND
5
*ULU3@4.7K_4 R39 *ULU3@4.7K_4 USB3_RXP1_RE R35 ULU3@0_4 USB30_RX1+ 5 SSRX-
6
6 SSRX+
7 7
EQ_A EQ_B DE_A DE_B OSA OSB USB3_TXN1_RE R36 ULU3@0_4 USB30_TX1-_R1 8 GND
+USB_RE_PWR USB3_TXP1_RE R37 ULU3@0_4 USB30_TX1+_R1 8 SSTX-
9
EQ_A
DE_A
9 SSTX+
OSA
13
12
11
10
R557 R560 R564 R567 R568 R571
ULU3@4.7K_4 ULU3@4.7K_4 *ULU3@4.7K_4 *ULU3@4.7K_4 *ULU3@4.7K_4 *ULU3@4.7K_4
13
12
11
10
ULU3@TARA9-9V1391
6
5
4
3
2
1
U22
B B
DE_A
EQ_A
NC
RXD_EN
NC
VDD
<C3B_20120316> 7
NC HGND
25
C760 ULU3@0.1U/10V_4X USB3_TXN1_C 8 24
stuff R557 and unstuff R567(re-driver IC vendor suggest) (6) USB3_TXN1
C762 ULU3@0.1U/10V_4X USB3_TXP1_C RXA- NC USB3_TXN1_RE_C C757 ULU3@0.1U/10V_4X USB3_TXN1_RE
(6) USB3_TXP1 9 23
RXA+ TXA- USB3_TXP1_RE_C C758 ULU3@0.1U/10V_4X USB3_TXP1_RE
10 22
C753 ULU3@0.1U/10V_4X USB3_RXN1_C EN_A# TXA+
(6) USB3_RXN1 11 21
C754 ULU3@0.1U/10V_4X USB3_RXP1_C TXB- EN_B# USB3_RXN1_RE
(6) USB3_RXP1 12 20
TXB+ RXB- USB3_RXP1_RE
19
RXB+
EQ_B
DE_B
VDD
NC
NC
NC
ULU3@PI3EQX7502ZDE ESD2
13
14
15
16
17
18
USB30_TX1+_R1 1 10 USB30_TX1-_R1 CN5
6
+5VSUS_USBP0 1 10
2 9
VDD GND +5VSUS_USBP0
3 8
EQ_B
DE_B
NC NC1 1
OSB
USBP11-_R 4 7 USBP11+_R USBP11-_R

R43 *ULU3@4.7K_4 USB30_RX1+ 4 7 USB30_RX1- USBP11+_R 2
+USB_RE_PWR 5 6
5 6 3
R45 ULU3@4.7K_4 *ULU3@AZ1065-06F 4
30 mils
1
+USB_RE_PWR
5
D1 D2 ULU2@UARC6-4K1926
+3V_S5 R10 ULU3@0_6 D25 *5V/30V/0.2p_4 *5V/30V/0.2p_4
*AZ5125-01J
2
+3V R13 *ULU3@0_6 C723 C763 C751 C45 C46
ULU3@10U/6.3V_6X ULU3@0.1U/10V_4X ULU3@0.1U/10V_4X ULU3@2.2U/10V_6X ULU3@470P/50V_4X <B3A_20120102>

<C3B_20120313> change ESD solution(del U5037)
del L3 for layout request
+3V_S5 +5V_S5
USB 2.0 CONN LEFT DOWN
<20111207_Lincan> CN3
6
<B3A_20120130> <B3A_20120130> C307 *UL@10P/50V_4C R395 *UL@300_4
reserve for external USB port. +5VSUS_USBP0
R269 U6 RP3
change to 100K ohm 100K_4 +5VSUS_USBP0
reserve 1206 package cap USBP0- USBP0-_R 1
2 IN1 OUT3 8 (6) USBP0- 4 3 2
A (for leakage issue) 3 7 USBP0+ 2 1 USBP0+_R A
IN2 OUT2 (6) USBP0+ 3
OUT1 6 4
USB_NORMAL_EN# 4 C138 C139 + C140 C142 C141 R340 *0X2_short
(34) USB_NORMAL_EN# EN#
1
1
GND <B3A_20120202>
5
9 5 *470P/50V_4X *0.1U/10V_4X 100U/6.3V_3528P_E45b *10U/6.3V_8X *100U/6.3V_1206 470/F_4 D3 D4 ULD@UARC6-4K1926
C143 GND-C OC# change to short pad
*5V/30V/0.2p_4 *5V/30V/0.2p_4
UP7534BRA8-15
2
1U/16V_6X
3
USB_NORMAL_OC# <B3A_20120102> change ESD solution(del U5037)

USB_NORMAL_OC# (6,34)
2
Q20 <C3B_20120321>
ME2N7002E_200MA <C3B_20120313>
PROJECT : BY7D
stuff for USB discharger Size Document Number Rev
del L4 for layout
1
request USB2.0/USB3.0 1A

5 4 3 2 1
5 4 3 2 1
HDMI
(14) EXT_HDMITX0N
(14) EXT_HDMITX0P
C137
C129
EHM@0.1U/10V_4X
EHM@0.1U/10V_4X
HDMI_TXDN0
HDMI_TXDP0
+3V
R83
DDC5V
R85
<Layout Note>
close to connector
R86 HM@499/F_4 HDMI_TXDP0

HDMI_TXDP2
HDMI_TXDN2
HDMI_TXDP1
1
2
3
CN4
D2+
SHELL1
D2 Shield
D2-
20
25
4
R452 IHM@0_4 D1+
(4) INT_HDMI_TXDN0 *HM@0_4 HM@0_4 5
D1 Shield
3
R446 IHM@0_4 R87 HM@499/F_4 HDMI_TXDN0 HDMI_TXDN1 6
(4) INT_HDMI_TXDP0 D1-
Q7 HDMI_TXDP0 7
R89 HM@499/F_4 HDMI_TXDP1 D0+
8
HDMI_TXDN0 D0 Shield
2 9 23
C118 EHM@0.1U/10V_4X HDMI_TXDN1 R91 HM@499/F_4 HDMI_TXDN1 HDMI_TXCP D0- GND
(14) EXT_HDMITX1N 10
C111 EHM@0.1U/10V_4X HDMI_TXDP1 CK+
(14) EXT_HDMITX1P 11 22
HM@FDV301N_200MA R93 HM@499/F_4 HDMI_TXDP2 HDMI_TXCN CK Shield GND
12
HDMI_CON_CEC CK-
13
1
R442 IHM@0_4 R96 HM@499/F_4 HDMI_TXDN2 CE Remote
(4) INT_HDMI_TXDN1 14
D
R445 IHM@0_4 R97 HM@100K_4 HDMI_SCL NC D
(4) INT_HDMI_TXDP1 15
R98 HM@499/F_4 HDMI_TXCP DDC5V HDMI_SDA DDC CLK
16
DDC DATA
17
C172 HM@0.1U/10V_4X R99 HM@499/F_4 HDMI_TXCN R90 NCEC@0_6 F1 +5V_HDM DDC5V GND
+5V 2 1 2 1 18
C100 EHM@0.1U/10V_4X HDMI_TXDN2 *HM@SMD1206P110TFT D11 *HM@B130LAW-7-F_1A HDMI_HPD_L +5V
(14) EXT_HDMITX2N 19
C107 EHM@0.1U/10V_4X HDMI_TXDP2 R88 CEC@0_6 HP DET
(14) EXT_HDMITX2P +5VPCU 21
C168 SHELL2
HM@HMR2N-AK120N
R451 IHM@0_4 HM@0.1U/10V_4X
(4) INT_HDMI_TXDN2
R455 IHM@0_4 Q10
(4) INT_HDMI_TXDP2
3 1
IN OUT
2
GND
C158 EHM@0.1U/10V_4X HDMI_TXCN HM@AP2331SA-7 D30
(14) EXT_HDMICLK-
C159 EHM@0.1U/10V_4X HDMI_TXCP *HM@AZ5125-01J
(14) EXT_HDMICLK+
C382
*HM@220P/50V_4X
R467 IHM@0_4
(4) INT_HDMI_TXCN
R468 IHM@0_4 for EMI
(4) INT_HDMI_TXCP
<Layout Note>
close to connector
+3V DDC5V
ESD5
EMI reserve for HDMI(EMC) HDMI_SDA 1 10 HDMI_SDA +3V
HDMI_SCL 1 10 HDMI_SCL
2 9
3
2
GND_3/8
9 R547 R546 HDMI HPD SENSE
HDMI_TXDN2 R73 *HM@100_4 HDMI_TXDP2 DDC5V 4 7 DDC5V HM@2K/F_4 HM@2K/F_4
HDMI_HPD_L 4 7 HDMI_HPD_L R553 +3V
5 6
5 6
2
HDMI_TXDN1 R74 *HM@100_4 HDMI_TXDP1 HM@10K/F_4
*HM@RClamp0524P
HDMI_TXDN0 R75 *HM@100_4 HDMI_TXDP0 (4) INT_HDMI_AUXN R469 IHM@0_4 1 3 HDMI_SDA
R545 EHM@0_4 HDMI_HPD R554
(14) EXT_HDMI_HPD
C HDMI_TXCN R76 *HM@100_4 HDMI_TXCP ESD4 (14) DDCDATA_AUX1N R474 EHM@0_4 Q8 HM@10K/F_4 C
3
HDMI_TXDP0 1 10 HDMI_TXDP0 HM@FDV301N_200MA
HDMI_TXDN0 1 10 HDMI_TXDN0 Q28
2 9
2 9 HM@ME2N7002E_200MA
3
HDMI_TXCP GND_3/8 HDMI_TXCP R542 IHM@0_4
4 7 (4) INT_HDMI_HPD 2
HDMI_SCL HDMI_TXCN 4 7 HDMI_TXCN +3V DDC5V
5 6
5 6
3
HDMI_SDA *HM@RClamp0524P
1
DDC5V 2 HDMI_DET_R HDMI_HPD_L
C165 ESD3 R577 R576 R283 R282
C166 C167 HDMI_TXDN1 1 10 HDMI_TXDN1 HM@2K/F_4 HM@2K/F_4 HM@200K/F_4 HM@0_4
HM@0.1U/10V_4X *HM@56P/50V_4N *HM@56P/50V_4N HDMI_TXDP1 1 10 HDMI_TXDP1 Q27
<B3A_20120207> 2
2 9
9
2
3 HM@ME2N7002E_200MA R284
stuff C165 for EMI
1
HDMI_TXDN2 GND_3/8 HDMI_TXDN2 HM@100K_4
4 7
HDMI_TXDP2 4 7 HDMI_TXDP2 R470 IHM@0_4 HDMI_SCL
5 6 (4) INT_HDMI_AUXP 1 3
5 6
<Layout Note> *HM@RClamp0524P (14) DDCCLK_AUX1P R475 EHM@0_4 Q9
HM@FDV301N_200MA
close to connector
<Layout Note>
close to connector
CEC Output <CEC>

HDMI CEC <CEC> CEC SMBus Level Shift <CEC>
(To Connect)
+3VPCU HDMI_CON_CEC
(To CECC)
0.013A(20mils)
C5279 C5280 C5286 *CEC@47P/50V_4N
U5014
3
CEC@1U/6.3V_4X CEC@0.1U/10V_4X
7 1 3ND_MBCLK +3VPCU
B VCC SCL 3ND_MBCLK (32,34) B
16 20 3ND_MBDATA 3ND_MBDATA (32,34)
VCC SDA HDMI_CEC_DDCDATA CEC_OUT R9556 CEC@22K_4
18 1
RP21 3 DDCSDA
+3VPCU 4 CEC@4.7KX2 XIN_CEC 4 17 HDMI_CEC_DDCCLK
XOUT_CEC XOUT DDCSCL
1 2 6
XIN CEC-TEST1 RP13
13 4 3 CEC@4.7KX2 +3VPCU R9557 Q5018
RP14 3 TEST1
4 CEC@4.7KX2 CEC-RESET# 3 12 CEC-TEST2 2 1 R9561
2
CEC-MODE RESET TEST0 CEC@100K_4 CEC@2SK3541T2L_100MA
1 2 8
MODE CEC_OUT CEC@4.7K_4
10
CEC OUT
2
5 9 CEC_IN
VSS CEC IN
15
NC HPDET HDMI_SDA HDMI_CEC_DDCDATA
14 19 6 1
NC HPDET CEC-RESET# CEC-TEST1
11 2
NC NC Q5022A CEC@2N7002KDW_115MA
CEC@R5F211B4D61SP#W4 R9537 R9538 R9539

*CEC@0_4 *CEC@0_4
*CEC@47K_4
CEC-MODE CEC-TEST2
CEC Input <CEC> +3VPCU
(To CECC) +3VPCU
U5017
CEC HotPlug <CEC> 1
2
5 C5285 CEC@0.1U/10V_4X R9569
5
3 4 CEC@4.7K_4
+3VPCU CEC@SN74LVC1G14DCKR HDMI_SCL HDMI_CEC_DDCCLK
3 4
Q5022B CEC@2N7002KDW_115MA
U5015
C5283 CEC@0.1U/10V_4X 5 1
2 R9541 CEC@1K/F_4 HDMI_HPD_L
CEC_EC_HP R9542 CEC@33_4 +3VPCU +3VPCU
(34) CEC_EC_HP 4 3
CEC@SN74LVC1G17DCKR
A HPDET R9544 A
D2008 R9555
+3VPCU CEC@470K_4
CEC@RB500V-40_100MA *CEC@10K_4
CEC_IN
3
R9558
C5284 *CEC@0.1U/10V_4X CEC@27K_4
5
1 HDMI_CON_CEC 1
HDMI_HPD R161 *CEC@1K_4 4
2 Q5019
U5016
+3V
*CEC@2SK3541T2L_100MA Quanta Computer Inc.
3
*CEC@TC7SH08FU(F)
2
PROJECT : BY7D
1A
HDMI/CEC
5 4 3 2 1
5 4 3 2 1
<LAN> <LNG> <LAN> <LNG> <LN1>

Atheros Lan
26
AR8152,AR8162 Co-Lay
LAN_VDD33
0.163A(20mils) LAN_VDD33 R548 LAN@10K_4 R549 LAN@0_4 CKREQ#

LAN_VDD33
U9
C174 C175 C176
1 39 LAN_LINKLED# C177 *LAN@470P/50V_4X
LAN@4.7U/6.3V_6X LAN@1U/10V_6Y LAN@0.1U/16V_4Y VDD33 LED1/LED_LINK10/100n LAN_ACTLED C178 *LAN@470P/50V_4X FCH_PCIE_LAN_CLKREQ#
38 (6) FCH_PCIE_LAN_CLKREQ#
LED0/LED_ACTn R551 52@0_4 CKREQ#
23
LED2/CLKREQn
D C179 LAN@1U/10V_6Y D
20110719 del 10U/6.3_8X for saving spacing
37 DVDDL C180 LAN@0.1U/16V_4Y
DVDD_REG DVDDL C181 LAN@0.1U/16V_4Y
24
R579 0_4 FCH_PCIE_RST#_LAN DVDDL AVDDL C182 LAN@0.1U/16V_4Y
2 31
(6,28) FCH_PCIE_RST#
CKREQ# R562 62@0_4
PCIE_WAKE# 3
4
PERSTn
WAKEn
Atheros
AVDDL
AVDDL
34 AVDDL C183 LAN@0.1U/16V_4Y LAN-Wake up function <LAN>
R552 52@0_4 VDDCT_REG/CKRn
33 CLK_PCIE_LANP (7)
C184 52@0.1U/16V_4Y AVDD_CEN REFCLKP
5
VDDCT REFCLKN
32 CLK_PCIE_LANN (7) Pull UP 10K to +3V_S5 in FCH
+3V 36 PCIE_WAKE#
RX_N PCIE_TXN_LAN (7) PCIE_WAKE# (6,28)
C185 52@1U/10V_6Y R575 62@30K/F_4 35
AVDDL RX_P PCIE_RXP_LAN_C C186 LAN@0.1U/10V_4X PCIE_TXP_LAN (7)
6 30 PCIE_RXP_LAN (7)
AVDDL_REG
AR8151/AR8152 TX_P
TX_N
29 PCIE_RXN_LAN_C C187 LAN@0.1U/10V_4X
PCIE_RXN_LAN (7)
C188 C189 C190 LAN@33P/50V_4N LAN_XTLO 7 28
XTLO TEST_RST
27
2
LAN@0.1U/16V_4Y LAN@1U/10V_6Y Y1 TESTMODE
LAN_XTLI 8
XTLI SMDATA
26
25
SB_SMBDATA1_LAN
SB_SMBCLK1_LAN
LAN-SM-Bus <LAN>
LAN@25MHZ_30 SMCLK SB_SMBDATA1_LAN R104 *LAN@0_4 SMB_LAN_DAT (6,28)
1
C191 LAN@33P/50V_4N 40
AVDDH LX
9
AVDDH_REG SB_SMBCLK1_LAN R105 *LAN@0_4 SMB_LAN_CLK (6,28)
R103 LAN@2.37K/F_4 RBIAS 10 41
C192 C193 RBIAS GND1
TX0P 11
LAN@0.1U/16V_4Y LAN@1U/10V_6Y TX0N TRXP0
12
TRXN0 AVDDH C194 LAN@0.1U/16V_4Y
22
TX1P AVDDH
14
TX1N TRXP1
15
TRXN1 C268 62@0.1U/16V_4Y
16
AVDDH
17 19
C TRXP2 AVDDL C275 62@0.1U/16V_4Y C276 62@1U/6.3V_4X C
18
TRXN2 AVDDL
13 separate LAN power for RTC wakeup support on S5
20 R106 62@0_6
GND10
TRXP3 LAN_VDD33
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
21 +3V_S5 LAN_VDD33
TRXN3
<B3A_20111226>
AR8152-BL1A-R
Add (for AR8162) R102 *LAN@0_6
42
43
44
45
46
47
48
49
50
GIGA:AR8151-BL1A-R
+3V_S5
AL008151005 1 3
LAN_P (34)
Q25 LAN@ME1303_3A R328
10/100:AR8152-BL1A-R C126 C270
2
AL008152009 LAN@0.01U/25V_4X *LAN@0.01U/25V_4X LAN@4.7K_4 Q26
LAN@LTC044EUBFS8TL_30MA
R164 LAN@3.01K/F_4 3 1
<B3A_20120207>
stuff C126,Q25,R164,R328,Q26
unstuff R102
PLACE NEAR LAN IC SIDE TRANSFORMER CONN <LAN> <LNG>

B
10/100:DB0EF7LAN01
RJ45 <LAN> <LNG> <LN1>
B
<LAN> <LNG> U21

GIGA: DB0Z06LAN00 LED0 = LAN_ACTLED 1 Over-clocking enable (default = 1)
TX0N 8 9 X-TX0N Over-clocking disable
L15 TX0P 7
TD-
TD+
TX-
TX+
10 X-TX0P 0
AVDD_CEN AVDD_CEN_R 6 11 TERM0
52@HCB1608KF-601T10_1A CT CT
5 12 SWR switch-mode regulator select
TX0N
TX1N
TX0P
TX1P
NC NC
4 13
3
NC
CT
NC
CT
14 TERM1 C422 1 Giga LAN pull High (default = 1)
TX1N 2 15 X-TX1N LED1 = LAN_LINKLED#
C423 C424 C273 TX1P RD- RX- X-TX1P C421 LAN@0.01U/100V_6X
1 16
RD+ RX+
2
4
2
4
LAN@0.1U/16V_4Y LAN@0.1U/16V_4Y LAN@1U/10V_6Y LDO linear regulator select

RN5 RN6 LAN@0.01U/100V_6X
LAN@NS681610 0 10/100M LAN pull Low
LAN@49.9X2 LAN@49.9X2
1
3
1
3
TERM2 TERM3 CN20

1 Normal function
C197 R108 R109 C198 CKREQ# or CKREQ_G#
C199 C201 C200 C202
*LAN@0.1U/10V_4X LAN@75/F_8 *LAN@0.1U/10V_4X TERM5 8 ATE test mode
LAN@1000P/50V_4X LAN@0.1U/16V_4Y LAN@1000P/50V_4X LAN@0.1U/16V_4Y LAN@75/F_8 NC4/3- 0
TERM5 7
NC/3+
X-TX1N 6
RX-/1-
TERM5 5
NC2/2-
For EMI Power on Strapping pin
TERM5
TERM5
4
NC1/2+ LAN_ACTLED R110 LAN@5.1K/F_6
A U13 C564 E@6.8P/50V_4N TX0P X-TX1P A
3
TX0N TX0P C425 LAN@220P/3KV_1808X RX+/1+
1 6
CH1 CH4 C565 E@6.8P/50V_4N TX0N X-TX0N LAN_LINKLED# R111 LAN@5.1K/F_6
2
TX-/0-
2 5 LAN_VDD33
GND VDD C567 E@6.8P/50V_4N TX1P X-TX0P 1
TX1N TX1P TX+/0+
3 4 9
CH2 CH3 C568 E@6.8P/50V_4N TX1N GND R348 *SHORT_6
10
*LAN@AZ1013-04S.R7G GND
<C3B_20120309> Quanta Computer Inc.
Del C195,C196 for hi-pot issue
<B3A_20120130> LAN@130456-031
PROJECT : BY7D
stuff for EMI Size Document Number Rev
1A
ATHEROS LAN (AR8152B)
5 4 3 2 1
5 4 3 2 1
HP <ADO> <EMC>
Codec (CX20671-21Z) <ADO> <EMI>
Output
FILT_1.65V
Output
AVDD_3.3
27
C203 C204 C205 C206 CN6
1
1U/10V_6Y 0.1U/16V_4Y 4.7U/6.3V_6X 0.1U/16V_4Y HPOUT-L R112 5.1/F_6 HPOUT-L2 R664 0_6 HPOUT-L3 2 7
<B3A_20120207> 6 8
HPOUT-R R113 5.1/F_6 HPOUT-R2 R665 0_6 HPOUT-R3 3 9
change to short pad
4 10
ADOGND ADOGND
+3V R114 *0/short_6 1.2mA(20mils) +3AVDD Port_A# 5
D D
C207 C211 C212 2SJ3013-009311F Shield_GND GND
C208 C209 C210 Normal Open Jack
4.7U/6.3V_6X 0.1U/16V_4Y 0.1U/16V_4Y
Layout Note: Path from +5V_IC to LPWR_5.0 and *100P/50V_4N *100P/50V_4N *0.1U/25V_6X
Near chip RPWR_5.0 must be very low resistance ( <0.01 ohms).
GND Place bypass caps very close to device.

ADOGND ADOGND
Port_A#
+3V_S5 R115 *0_6 0.061mA(15mils) +3AVDD_S5 +5AVDD 1A(100mils) R666 0_6 +5V
+3V R153 0_6 C213 C214 C215 C216 D14

*VPORT 0603 220K-V05
*10U/6.3V_8X 0.1U/16V_4Y *10U/6.3V_8X 0.1U/16V_4Y D15 *VPORT 0603 220K-V05 HPOUT-L3
Determining HDA use +1.5V/+3V
GND
GND GND D16 *VPORT 0603 220K-V05 HPOUT-R3
GND
48.7mA(20mils) +3AVDD
C217 C218 (40mils)

*10U/6.3V_8X 0.1U/16V_4Y
Output FILT_1.8V
C219 C220 C221 C222 C223 C224 C225

<B3A_20120207> External MIC <ADO> <EMC>
change to short pad
GND 4.7U/6.3V_6X 0.1U/16V_4Y 0.1U/16V_4Y 0.1U/16V_4Y 0.1U/16V_4Y 10U/6.3V_8X 10U/6.3V_8X
R116 *0/short_4 +3AVDD
SENSE_A_R MIC1-VREFO
GND
18
26
29
27
28
12
15
17
3
2
7
U10 SENSE PIN A C227
GND R117 R118 R119
VDD_IO
CLASSDREF
FILT_1.8
VAUX_3.3
DVDD_3.3
FILT_1.65
AVDD_3.3
LPWR_5.0
RPWR_5.0
AVDD_HP
AVDD_5V
GND C226 0.1U/16V_4Y 5.11K/F_4 3.3K/F_4 3.3K/F_4 *4.7U/6.3V_6X
(6) ACZ_RST# 9 CN7

RESET# ADOGND 1
C REV-00 for EMI R120 39.2K/F_4 Port_A# MIC1_L1 R123 100/F_6 MIC1_L2 R667 0_6 MIC1_L3 2 7 C
R121 0_4 ACZ_BITCLK_R 5 36 SENSE_A R122 20K/F_4 Port_B# 6 8
(6) ACZ_BITCLK BIT_CLK SENSE_A
8 MIC1_R1 R125 100/F_6 MIC1_R2 R668 0_6 MIC1_R3 3 9
(6) ACZ_SYNC SYNC
(6) ACZ_SDIN0 R124 33_4 SDATA_IN 6 4 10
SDATA_IN
(6) ACZ_SDOUT 4
SDATA_OUT Port_B# 5
35 MIC1-RR C228 2.2U/6.3V_6X MIC1_R1 2SJ3013-009311F Shield_GND GND

PORTB_R MIC1-LL C229 2.2U/6.3V_6X MIC1_L1 C230 C231 C232
34
PORTB_L MIC1-VREFO_B R126 0_4 MIC1-VREFO
B_BIAS
33
100P/50V_4N 100P/50V_4N *0.1U/25V_6X
Normal Open Jack
R127 33_4 PCBEEP_R C233 0.1U/16V_4Y PCBEEP_C 10 32 TP1
(6) PCBEEP PC_BEEP C_BIAS
31 TP2
R128 *10K_4 PORTC_R TP3
GND 39 30
SPDIF PORTC_L
TP4 38
AMP_MUTE# GPIO0/EAPD# ADOGND ADOGND Port_B#
(34) AMP_MUTE# 37
GPIO1/SPK_MUTE# CX20671-21Z
Low Active NC_DR
25
Place close to audio codec. 24 D18
NC_DL D17 2 1 *VPORT 0603 220K-V05 MIC1_L3 *VPORT 0603 220K-V05
23 HPOUT-R
R129 100_4 DMIC PORTA_R HPOUT-L
(30) DMIC_CLK 40 22 GND
DMIC_DATA DMIC_CLK PORTA_L
(30) DMIC_DATA 1
DMIC_1/2 AVEE
21
AVEE D19
20 FLY_N 2 1 *VPORT 0603 220K-V05 MIC1_R3 GND
FLY_N FLY_P C234 1U/10V_6Y
19
FLY_P C235 C236
EP_GND
RIGHT+
RIGHT-
Internal Speaker
LEFT+
LEFT-
0.1U/16V_4Y 4.7U/6.3V_6X
CN8
<ADO> <EMC> SPK_R+ R130 0_6 INSPKR+N 1
11
13
14
16
41
GND SPK_R- R131 0_6 INSPKR-N 1

2
DMIC MIC1-LL SPK_L- R132 0_6 INSPKL-N 2
3
C237 0.1U/16V_4Y SPK_L+ R133 0_6 INSPKL+N 3
4
DMIC_DATA C238 0.1U/16V_4Y MIC1-RR 4
C241 *0.1U/16V_4Y <Layout Note> 88266-040L
C244 *0.1U/16V_4Y
C239 C240 C242 C243 close to connector
B B
*0.47U/6.3V_4X *0.47U/6.3V_4X R574 *0_4 *0.47U/6.3V_4X *0.47U/6.3V_4X INSPKL-N
R573 *0_4 INSPKL+N
R572 *0_4 Add for EMI INSPKR-N
INSPKR+N
GND GND GND GND
C245 C246 C247 C248
GND ADOGND E@2200P/50V_4X E@2200P/50V_4X E@2200P/50V_4X E@2200P/50V_4X
For EMI GND GND GND GND
ACZ_BITCLK ACZ_SDOUT ACZ_RST#

SPK_R+
C249 C250 C251
SPK_R- INSPKR+N INSPKR-N INSPKL+N INSPKL-N
*10P/50V_4C *10P/50V_4C *10P/50V_4C
SPK_L- D20 D21 D22 D23
SPK_L+
*VPORT 0603 220K-V05 *VPORT 0603 220K-V05 *VPORT 0603 220K-V05 *VPORT 0603 220K-V05
GND
A A

PROJECT : BY7D
1A
AUDIO CODEC (CX20671-21Z)
5 4 3 2 1
5 4 3 2 1
MINI Card Slot#1 (WiFi) <MNW>
+1.5V WIMAX_P
28
Before RAMP must to remove
debug card component
C414 C410 C416 C413 C271 C411 C417 C272
D D
E@0.01U/25V_4X E@0.1U/16V_4Y *10U/6.3V_8X E@0.1U/16V_4Y 0.1U/16V_4Y *C@0.1U/16V_4Y *C@0.1U/16V_4Y *C@10U/6.3V_8X
CN19
BT_RFCTRL_BT 51 52
PLTRST# R420 NMP@0_4 PLTRST#_debug
49
NC
C-Link_RST
+3.3V
GND
50 SMBus
(6,7,29,34) PLTRST# 47 C-Link_DAT +1.5V 48
R339 NMP@0_4 PCLK__debug_R 45 46
(7) PCLK_DEBUG C-Link_CLK LED_WPAN#
43 44 R356 AOAC@0_4
GND LED_WLAN#
41 NC NC 42
39 NC NC 40
37 38 USBP7+ NAOAC@2N7002KDW_115MA
GND USB_D+ USBP7+ (6)
35 36 USBP7- PU 2.2K to +3V_S5 in FCH Q79B
GND USB_D- USBP7- (6)
33 34 3 4 WLCGCLK_SMB
(7) PCIE_TXP_WLAN PETp0 GND (6,26) SMB_LAN_CLK
31 32 WLCGDAT_SMB R400 *300_4 C556 *10P/50V_4C
(7) PCIE_TXN_WLAN PETn0 SMB_DATA WLCGCLK_SMB
29 30
GND SMB_CLK R335
27 28 <20111207_Lincan>
5
GND +1.5V NAOAC@4.7K_4
(7) PCIE_RXP_WLAN 25 26 reserve for external USB port.
PERp0 GND
(7) PCIE_RXN_WLAN 23 24
PERn0 +3.3Vaux FCH_PCIE_RST#_WLAN R578 0_4
21 22 FCH_PCIE_RST# (6,26)
GND PERST# RF_EN
19 20 RF_EN (34) WIMAX_P
+3V NC W_DISABLE#
17 NC GND 18
15 16 LFRAME#_PCIE RN8 2 1 NMP@0X2 R381

GND NC LAD3_PCIE LFRAME# (7,34) NAOAC@4.7K_4
(7) CLK_PCIE_WLANP 13 REFCLK+ NC 14 4 3
2
11 12 LAD2_PCIE RN7 2 1 NMP@0X2 LAD3 (7,34)
(7) CLK_PCIE_WLANN REFCLK- NC
C FCH Integrated PU 8.2K to +3V 9 10 LAD1_PCIE 4 3 LAD2 (7,34) PU 2.2K to +3V_S5 in FCH C
FCH_PCIE_WLAN_CLKREQ# CLKREQ# GND NC LAD0_PCIE R330 NMP@0_4 LAD1 (7,34) WLCGDAT_SMB
(6) FCH_PCIE_WLAN_CLKREQ# 1 3 7 CLKREQ# NC 8 (6,26) SMB_LAN_DAT 6 1
BT_RFCTRL_BT R582 *0_4 5 6 LAD0 (7,34)
Q22 BT_CHCLK +1.5V Q79A
3 BT_DATA GND 4
AOAC@ME2N7002E_200MA WLAN_WAKE# 1 2 NAOAC@2N7002KDW_115MA
WAKE# +3.3V
PU 10K to +3V_S5 in FCH AAA-PCI-052-P01 R360 AOAC@0_4
PCIE_WAKE# 3 1
(6,26) PCIE_WAKE#
Q21 <B3A_20120209>
NAOAC@ME2N7002E_200MA
reserve 0 ohm
2
WIMAX_P R580 NAOAC@10K_4
FCH_PCIE_WLAN_CLKREQ# R343 NAOAC@0_4 CLKREQ#

R165 10K_4 BT_RFCTRL_BT
(34) BT_RFCTRL WIMAX_P
PCIE_WAKE# R341 AOAC@0_4 WLAN_WAKE#
2
Q13 1 3 LTC044EUBFS8TL_30MA
B B
AOAC NAOAC: WIMAX_P->+3V

AOAC: WIMAX_P->+3V_S5
+3V_S5 WIMAX_P +3V
R166 *0_6 R168 NAOAC@0_6

R169 *0_6 R186 NAOAC@0_6
WLAN_P (34)
1 3 +3V_S5
Q2
C22 AOAC@ME1303_3A R16
2
C23
*0.01U/25V_4X Q3
AOAC@0.01U/25V_4X AOAC@4.7K_4
AOAC@LTC044EUBFS8TL_30MA
A 3 1 A
R17 AOAC@3.01K/F_4

PROJECT : BY7D
MINI CARD 1A

5 4 3 2 1
5 4 3 2 1
2 IN 1 CARD READER (Type: MMC/SD)

Card Reader (AU6437B53-GDL-GR)
<MMC> 29
VCC_XD
30mils
D D
C252 C253 C254 C255

4.7U/6.3V_6X 0.1U/16V_4Y *0.1U/16V_4Y *0.1U/16V_4Y
C256 R142 *0_4
0.1U/10V_4X R143 *0_4
XTALSEL
DATA1
DATA0
CTRL1
CTRL3
NBMD
+1.8V_Card <Layout Note>
+3V_Card close to IC
<Layout Note> C257 Clock input selection
close to IC 0.1U/10V_4X 1 : 48MHz input (default)
0 : 12MHz input
+3V
48
47
46
45
44
43
42
41
40
39
38
37
U11
C258 *33P/50V_4N CTRL3 R9773 33_4 SD_CD#
VDDHM2
GND2
VDD3
XTALSEL
NC5
CTRL1
CTRL3
DATA1
DATA0
DATA7
NC4
NBMD
NBMD Power saving mode enable VCC_XD
R147
*10K_4 1 : enable (default)
1 GPON7 NC3 36 0 : disable
R146 0_4 48M_CARD_R 2 35
11
12
EXT48IN DATA6
4
R148 0_4 (7) CLK_48M_CARD 3 34 CTRL0 CN9
(6,7,28,34) PLTRST# RSTN CTRL0
R151 330_4 4 33
VDD
C/D
CD COM
REXT DATA5 CTRL2 CTRL1 R9772 BLM15BD121SN1D_300MA SD_WP
+3V_Card 5
VD33P CTRL2
32 CTRL0 trace surround with GND 10
W/P
C259 USBP5+ 6 AU6437B53-GDL-GR DATA4 31 DATA2 R9781 33_4 SD_D2 9
USBP5- DP DATA3 DATA1 R9774 33_4 SD_D1 DATA2
*1U/6.3V_4X 7 30 8
C260 DM DATA3 DATA2 DATA0 R9776 33_4 SD_D0 DATA1
8 29 7
4.7U/6.3V_6X VS33P DATA2 DATA0
9
XI XDWPN
28 SD XD MS 6
VSS2
WP COM
C C261 10 27 CTRL0 R9775 BLM15BD121SN1D_300MA SD_CLK 5 15 C
XO XDCEN CLK GND3
11 26 3
VDD1 EEPDATA VSS1
GND2
4.7U/6.3V_6X 12 25 CTRL0 SDCLK XDALE MSBS CTRL2 R9777 33_4 SD_CMD 2
V18 EEPCLK DATA3 R9779 33_4 SD_D3 CMD
1
SDWPEN
+1.8V_Card
VDDHM1
DATA3
AGND5V
AVDD5V
CF_V33
CTRL1 SDWP XDCLE MSCLK
XDCDN
CTRL4
GND1
VDD2
SDR009-11-F <B3A_20120206>
13
14
NC1
NC2
V33
(6) USBP5+ USBP5+ CTRL2 SDCMD XDRBD for EMI
USBP5- change CN9 value to SDR009-11-F
(6) USBP5-
CTRL3 SDCDN XDWRN
13
14
15
16
17
18
19
20
21
22
23
24
C310 *10P/50V_4C R398 *300_4 AU6437B53-GDL-GR
CTRL4 XDRDN MSINS
<20111207_Lincan> VCC_XD
SDWP R157 *0_4
reserve for external USB port.
<Layout Note> CTRL4
close to IC 0.5A(30mils) +1.8V_Card SD write protect enable
+3V_Card 1 : decided by SDWP(default)
+3V +3V_Card
0 : SD always write-able
R158 *0/short_8 +3V_Card C262 C263 CTRL4 SD_CLK
0.1U/10V_4X 0.1U/10V_4X
<B3A_20120207>
C265 C266 <Layout Note> C267 C14 close C264
change to short pad 4.7U/6.3V_6X 0.1U/10V_4X *270P/50V_4X to CN2 *33P/50V_4N
close to IC
B B
A A

PROJECT : BY7D
1A
CARD READER
5 4 3 2 1
5 4 3 2 1
CCD [CCD] LCD POWER SWITCH <LDS> HALL SENSOR&BACK LIGHT SWITCH <HSR>
R46 *0/short_4
+3VPCU
<B3A_20120207>
R159
R408
*100K_4 30
change to 0 ohm
0_6
+3V
USBP6+_LCD USBP6+_LCD_CN
(6) USBP6+_LCD
USBP6-_LCD USBP6-_LCD_CN 1 2 LID591#
(6) USBP6-_LCD LID591# (34)
R399 300_4 C428 10P/50V_4C MR1
R44 *0/short_4 C405 R325 <B3A_20120207> D42 D44
1U/10V_6X *0/short_1206 LCDVCC *VPORT 0603 220K-V05 C269 APX9132H AI-TRG *VPORT 0603 220K-V05
change to short pad
3
<B3A_20120202> <20111207_Lincan> 1U/10V_6X
U19
D change to short pad Internal USB isochronous devices need to stuff D
res and cap on USB negative data signal 6 1
IN OUT
<C3B_20120313>
4 2 C406 C528 C526
del L5 for layout request IN GND
R171 IV@0_4 3 5 0.1U/16V_4Y 0.01U/25V_4X 10U/6.3V_6X
(4) INT_LVDS_DIGON ON/OFF GND DISPON_I R167 IV@0_4
(34) DISPON_I INT_LVDS_BLON (4)
R327 IV@100K_4
AP2821KTR-G1 R183 EV@0_4
LVDS_BRIGHT (14)
R178 EV@0_4
(15) EV_LVDS_DIGON
R173 IV@100K_4
PD 10K to GND in GPU
+3V F2 2 1 *SMD1206P110TFT CCD_POWER
C274 10U/6.3V_8X
+
R170 0_8
LCD Panel Module [LDS]

CN10
LCD_BK_POWER 1 INT_LCD_TXLCLKOUT+ RP8 3 4 IV@0X2 LCD_TXLCLKOUT+
1 (4) INT_LCD_TXLCLKOUT+
2 INT_LCD_TXLCLKOUT- 1 2 LCD_TXLCLKOUT-
2 (4) INT_LCD_TXLCLKOUT-
3
3
+3V 4
R174 0_8 LCD_BK_POWER C277 *47P/50V_4N LCD_EDIDCLK 4 EV_LCD_TXLCLKOUT+ RP15 EV@0X2
C VIN 5 (15) EV_LCD_TXLCLKOUT+ 4 3 C
LCD_EDIDDATA 5 EV_LCD_TXLCLKOUT-
6 (15) EV_LCD_TXLCLKOUT- 2 1
6
7
C279 C280 LCD_TXLOUT0- 7
8
LCD_TXLOUT0+ 8
9
1000P/50V_4X 0.1U/25V_6X 9 INT_LCD_TXLOUT2+ RP7 IV@0X2 LCD_TXLOUT2+
10 (4) INT_LCD_TXLOUT2+ 3 4
LCD_TXLOUT1- 10 INT_LCD_TXLOUT2- LCD_TXLOUT2-
11 (4) INT_LCD_TXLOUT2- 1 2
LCD_TXLOUT1+ 11
12
12
13
LCD_TXLOUT2- 13 EV_LCD_TXLOUT2+ RP16 EV@0X2
LVDS Enable 14 (15) EV_LCD_TXLOUT2+ 4 3
LCD_TXLOUT2+ 14 EV_LCD_TXLOUT2-
15 (15) EV_LCD_TXLOUT2- 2 1
15
16
R175 IV@4.7K_4 LCD_EDIDCLK LCD_TXLCLKOUT- 16
+3V 17
R176 IV@4.7K_4 LCD_EDIDDATA LCD_TXLCLKOUT+ 17 INT_LCD_TXLOUT1+ RP6 IV@0X2 LCD_TXLOUT1+
18 (4) INT_LCD_TXLOUT1+ 3 4
18 INT_LCD_TXLOUT1- LCD_TXLOUT1-
19 (4) INT_LCD_TXLOUT1- 1 2
LVDS_VADJ 19 INT_LCD_EDIDDATA C298 *22P/50V_4N
20
R58 EV@2K/F_4 LCD_EDIDCLK DISPON R172 1.2K/F_4 DISPON 20
(34) EC_FPBACK# 21
R60 EV@2K/F_4 LCD_EDIDDATA LCDVCC 21 EV_LCD_TXLOUT1+ RP17 EV@0X2
LCDVCC 22 (15) EV_LCD_TXLOUT1+ 1 2
C278 *10U/6.3V_4X 22 EV_LCD_TXLOUT1- INT_LCD_EDIDCLK C300 *22P/50V_4N
23 (15) EV_LCD_TXLOUT1- 3 4
D39 23
LCP0G050M0R2R
INT_LCD_TXLOUT0+ RP5 2 1 IV@0X2 LCD_TXLOUT0+
(4) INT_LCD_TXLOUT0+
INT_LCD_TXLOUT0- 4 3 LCD_TXLOUT0- +3VPCU C285 0.1U/10V_4X
(4) INT_LCD_TXLOUT0-
R177 IV@0_4 LVDS_VADJ
(4) INT_DPST_PWM
24 34
R184 EV@0_4 CCD_POWER 24 34 EV_LCD_TXLOUT0+ RP10 EV@0X2 C284 0.1U/10V_4X
(15) EXT_DPST_PWM 25 (15) EV_LCD_TXLOUT0+ 1 2 +3VPCU
USBP6-_LCD_CN 25 EV_LCD_TXLOUT0-
26 33 (15) EV_LCD_TXLOUT0- 3 4
R189 *0_4 C283 *22P/50V_4N USBP6+_LCD_CN 26 33
(34) EC_DPST_PWM <C3B_20120306> 27
27
reserve R189 for PWM signal issue 28 32
R421 0_6 DMIC_DATA_R 28 32 INT_LCD_EDIDCLK RP4 IV@0X2 LCD_EDIDCLK
(27) DMIC_DATA 29 (4) INT_LCD_EDIDCLK 4 3
C282 *0.1U/10V_4X R419 0_6 DMIC_CLK_R 29 INT_LCD_EDIDDATA LCD_EDIDDATA
(27) DMIC_CLK 30 31 (4) INT_LCD_EDIDDATA 2 1
30 31
C288 *22P/50V_4N 50373-03001-002
EV_LCD_EDIDCLK RP11 2 1 EV@0X2
(14) EV_LCD_EDIDCLK
EV_LCD_EDIDDATA 4 3
(14) EV_LCD_EDIDDATA
C286 *4.7P/50V_4C USBP6+_LCD_CN
C287 *4.7P/50V_4C USBP6-_LCD_CN
B B
C289 CRT@0.1U/16V_4Y
CRT [CRT] <C3B_20120314>
2 1 2 1 5V_CRT2
change L18,L19,L20 to BLM18PG330SN1B(33 ohm @100M) +5V
D26 CRT@SS14L_1A F3 CRT@SMD1206P110TFT
16
R138 ICRT@0_4 CRT_RED CRT_RED L18 CRT@BLM18PG330SN1B_3A CRT_RED_L
(4) INT_CRT_RED
R152 ICRT@0_4 CRT_GRE CRT_GRE L19 CRT@BLM18PG330SN1B_3A CRT_GRE_L 6
(4) INT_CRT_GRE
CRT_RED_L 1 11
R107 ICRT@0_4 CRT_BLU CRT_BLU L20 CRT@BLM18PG330SN1B_3A CRT_BLU_L 7
(4) INT_CRT_BLU
CRT_GRE_L 2 12 CRTDDAT
8
R465 ECRT@0_4 CRT_BLU_L 3 13 CRTHSYNC
(14) EXT_CRT_RED
C292 C293 C294 C295 C296 C297 9
R494 ECRT@0_4 R180 R181 R182 CRT@6.8P/50V_4N CRT@6.8P/50V_4N CRT@6.8P/50V_4N CRT@6.8P/50V_4N 4 14 CRTVSYNC
(14) EXT_CRT_GRE
CRT@150/F_4 CRT@6.8P/50V_4N CRT@6.8P/50V_4N 10
R461 ECRT@0_4 CRT@150/F_4 CRT@150/F_4 5 15 CRTDCLK
(14) EXT_CRT_BLU
CN11
CRT@DHR48-15K1200
17
+5V +3V
R144 ICRT@0_4 CRT_DDCCLK +5V +3V
(4) INT_CRT_DDCCLK
U12
R136 ICRT@0_4 CRT_DDCDAT 5V_CRT2 1 16 VSYNC1 R190 CRT@39/F_4 CRTVSYNC CRTDCLK R192 ICRT@4.7K_4 5V_CRT2
(4) INT_CRT_DDCDAT VCC_SYNC SYNC_OUT2
14 HSYNC1 R191 CRT@39/F_4 CRTHSYNC CRTDDAT R193 ICRT@4.7K_4
R150 ICRT@0_4 CRT_HSYNC SYNC_OUT1
(4) INT_CRT_HSYNC +5V 7
C303 C304 C299 CRT@0.22U/10V_4X VCC_DDC
8
R145 ICRT@0_4 CRT_VSYNC C291 C290 BYP CRT_VSYNC C301 C302 CRTDCLK R204 ECRT@2K/F_4
(4) INT_CRT_VSYNC 15
CRT@0.1U/25V_6X CRT@0.1U/25V_6X SYNC_IN2 CRT_HSYNC CRTDDAT R195 ECRT@2K/F_4
CRT@0.1U/16V_4Y CRT@0.1U/16V_4Y +3V 2 13 CRT@10P/50V_4C CRT@10P/50V_4C
VCC_VIDEO SYNC_IN1
A R478 ECRT@0_4 A
(14) EXT_CRT_DDCCLK
CRT_RED_L 3 10 CRT_DDCCLK CRT_DDCDAT R185 ICRT@4.7K_4 +3V
R480 ECRT@0_4 CRT_GRE_L VIDEO_1 DDC_IN1 CRT_DDCDAT CRT_DDCCLK R187 ICRT@4.7K_4
(14) EXT_CRT_DDCDAT 4 11
CRT_BLU_L VIDEO_2 DDC_IN2
5
R493 ECRT@0_4 VIDEO_3 CRTDCLK
(14,16) EXT_CRT_HSYNC 9
DDC_OUT1 CRTDDAT CRT_DDCDAT R522 ECRT@2K/F_4
6 12
R479 ECRT@0_4 GND DDC_OUT2 CRT_DDCCLK R525 ECRT@2K/F_4
(14,16) EXT_CRT_VSYNC
CRT@IP4772CZ16
C306 C305
CRT@10P/50V_4C CRT@10P/50V_4C

PROJECT : BY7D
1A
LVDS/CCD/DRT
5 4 3 2 1
5 4 3 2 1
SATA ODD [ODD]

ODD Zero power [OZP]
31
+5V_ODD
CN12
14 +5V L23 HCB1608KF-121T30_3A
D GND14 D
1 C426
GND1 SATA_TXP1_C C812 0.01U/25V_4X
2 SATA_TXP1 (8)
RXP SATA_TXN1_C C808 0.01U/25V_4X 0.1U/10V_4X
3 SATA_TXN1 (8)
RXN
4
GND2 SATA_RXN1_C C311 0.01U/25V_4X
5 SATA_RXN1 (8)
TXN SATA_RXP1_C C312 0.01U/25V_4X
6 SATA_RXP1 (8)
TXP
7
GND3
8 ODD_PRSNT# R303 1K/F_4

DP
9
+5V +5V_ODD
10 +5V_ODD
+5V
11
RSVD
12
GND C313 C314 C315 C316 C317 + C318
13
GND
15 *0.1U/10V_4X *0.1U/10V_4X *0.1U/10V_4X 0.1U/10V_4X 10U/6.3V_8X *100U/6.3V_3528P_E45b
GND15
C18526-11305-L
C C
SATA HDD [HDD]
CN13
23
GND23
1
GND1 SATA_TXP0_C C817 0.01U/25V_4X
2 SATA_TXP0 (8)
RXP SATA_TXN0_C C815 0.01U/25V_4X
3 SATA_TXN0 (8)
RXN
4
GND2 SATA_RXN0_C C321 0.01U/25V_4X
5 SATA_RXN0 (8)
TXN SATA_RXP0_C C322 0.01U/25V_4X
6 SATA_RXP0 (8)
TXP
7
B GND3 B
8
3.3V
9
3.3V
10
3.3V
11
GND
12
GND
13
GND
14
5V
15
5V
16
5V
GND
17 <B3A_20120202>
18 change to short pad
RSVD
19
GND
20
12V +5V_HDD1 R201 *0/short_8
21 +5V
12V
22
12V
24 C325 C326 C327 + C328
GND24
*0.1U/16V_4Y 0.1U/16V_4Y 10U/6.3V_8X *100U/6.3V_3528P_E45b
SAT-22ESAB
A A

PROJECT : BY7D
1A
HDD/ODD
5 4 3 2 1
5 4 3 2 1
+3V_GPU
Thermal Sensor <THC>

32
2
PU 4.7K to +3VPCU in EC PU 10K to +3V_GPU in GPU
(25,34) 3ND_MBCLK 6 1 GPU_SMBCLK GPU_SMBCLK (14)

D D
Q19A EV@2N7002KDW_115MA
+3V_GPU
5
PU 4.7K to +3VPCU in EC PU 10K to +3V_GPU in GPU
(25,34) 3ND_MBDATA 3 4 GPU_SMBDAT GPU_SMBDAT (14)
Q19B EV@2N7002KDW_115MA
C C
Thermal dGPU Int Thermal
EC(M) 3ND_SMB
EC(M) 3ND_SMB dGPU int SMBUS
dGPU(M) SMB dGPU int SMBUS
B B
+3V
FAN Control <THC>
+5V
R217
40 MIL FANPWR = 1.6*VSET 10K_4

CN17
40 MIL
U14 (34) FANSIG1 FANSIG1
C358 2.2U/6.3V_4X 2 3 +5V_FAN
VIN VO 1
GND 5 2
pin1 internal PU to VIN 1 /FON GND 6 3
GND 7
(34) VFAN1 4 8 C569 C359 C360
VSET GND
APE8872M 2.2U/6.3V_6X 0.01U/25V_4X *0.01U/25V_4X 50273-0037L-001
<B3A_20120130>
8 7 6 5 G995 layout notice change value to 50273-0037L-001
Gnd shape
D28 2 1 FANSIG1
A A
*VPORT 0603 220K-V05 1 2 3 4
D29 2 1 +5V_FAN
*VPORT 0603 220K-V05 Quanta Computer Inc.

PROJECT :BY7D
1A
THERMAL
5 4 3 2 1
5 4 3 2 1
KEY BOARD Connector <KBC> <EMI> TOUCH PAD BOARD <TPD> <EMI>
C329
C330
C331
ESD@39P/50V_4N
ESD@39P/50V_4N
ESD@39P/50V_4N
MX7
MX2
MX3
CN14
36
1
K_LED_P
MY16
33
MX4 2 MY16 (34)
C333 ESD@39P/50V_4N
3 MY17 CN15
4 MY17 (34)
+5V 1
5 +5V 1
K_LED_P L25 0_6 TPCLK_L 2 ID_Detect default
6 (34) TPCLK 2
C337 ESD@39P/50V_4N MX0 MY2 L24 0_6 TPDATA_L 3
D
MX5 7 MY1 MY2 (34) (34) TPDATA 3 D
C338 ESD@39P/50V_4N
8 MY1 (34)
C332 C5547 4 4 Metal/IMR H
C339 ESD@39P/50V_4N MX6 MY0 4.7U/6.3V_6X E@0.1U/16V_4X BOARD_ID10 5
MX1 9 MY4 MY0 (34) (6,8) BOARD_ID10 5
C340 ESD@39P/50V_4N
10 MY4 (34)
C335 C336
+3V 6 6 TEXTURE L
MY3
11 MY3 (34)
MY5 *10P/50V_4C *10P/50V_4C 88513-064N
12 MY14 MY5 (34)
C5549
13 MY14 (34)
C341 ESD@39P/50V_4N MY7 MY6 C5561 C5548
14 MY6 (34)
C342 ESD@39P/50V_4N MY13 MY7 E@1000P/50V_4X E@2200P/50V_4X E@0.1U/16V_4X
15 MY7 (34)
C343 ESD@39P/50V_4N MY12 MY13
16 MY13 (34)
C344 ESD@39P/50V_4N MY15 MY8
17 MY8 (34)
MY9 <B3A_20120130>
18 MY9 (34)
MY10
C345 ESD@39P/50V_4N MY3 19 MY11
MY10 (34) add for EMI (close to TP CONN)
20 MY11 (34)
C346 ESD@39P/50V_4N MY5 MY12
21 MY12 (34)
C347 ESD@39P/50V_4N MY14 MY15
MY6 22 MX7 MY15 (34)
C348 ESD@39P/50V_4N
23 MX7 (34)
MX2
24 MX2 (34)
C349 ESD@39P/50V_4N MY2 MX3
C350 ESD@39P/50V_4N MY1
MY0
25
26
MX4
MX0
MX3
MX4
(34)
(34)
Power Board (UIF) <PSW> TP board <TPD> EMI Pad <OTH>
C351 ESD@39P/50V_4N
MY4 27 MX5 MX0 (34)
C352 ESD@39P/50V_4N
28 MX5 (34)
MX6
29 MX6 (34) PAD1 PAD2 PAD3
C357 ESD@39P/50V_4N MY16 MX1 CN16
30 MX1 (34)
C373 ESD@39P/50V_4N MY17 K_LED_P
31 CAPSLED NBSWON# 1
32 CAPSLED (34) (34) NBSWON# 2
ESD Issue 33 3
34 4 CN23
C355 ESD@39P/50V_4N CAPSLED 88513-044N +5V 1
C353 ESD@39P/50V_4N K_LED_P D33 C354 TPCLK_L 1
C
35 2 2
C
<B3A_20120130> ESD@LCP0G050M0R2R
220P/50V_4X TPDATA_L 3
91504-344N 3
<C3B_20120313> change value to 91504-344N 4 4 <C3B_20120312>
BOARD_ID10 5
stuff for ESD 5 add Pad1 for EMI
PU to +3V in FCH +3V 6 6
R205 150_4 K_LED_P +3VPCU SMB_RUN_DAT 7
+3V (6,11,12) SMB_RUN_DAT 7
SMB_RUN_CLK 8
(6,11,12) SMB_RUN_CLK 8
RP25 <C3B_20120316>
10 1 10KX8 MX7 PU to +3V in FCH *50503-0080N-001
MX1 MX2 stuff ESD solution for power board
9 2
<C3B_20120321> MX6 8 3 MX3
MX5 7 4 MX4
UMA: stuff 100pF for EMI MX0 6 5
DIS: stuff 39pF
EMI PAD <EMI> HOLE <OTH>

HOLE8 HOLE9 HOLE11 HOLE1 HOLE2 HOLE3
+5V +5V +5V +5V +5V +5V +5V +5V +5VPCU
C319 C320 C334 C356 C402 C429 C583 C584 C600
1
*0.1U/10V_4X *0.1U/10V_4X *0.1U/10V_4X *0.1U/10V_4X *0.1U/10V_4X *0.1U/10V_4X *0.1U/10V_4X *0.1U/10V_4X E@2200P/50V_4X
<B3A_20120130> *H-TC276BC217D146P2 *H-TC276BC217D146P2 *H-TC276BC217D146P2 *H-TC315BC276D118P2 *H-TC315BC276D118P2 *H-TC276BC236D118P2
add (BOT: -6475, 2880)
+3V +3V +3V +3V +3V +3V +3V +3V VIN +3V
B B
HOLE12 HOLE10 HOLE5 HOLE6 HOLE7
C431 C432 C436 C549 C550 C573 C574 C575 C595

C603
*0.1U/10V_4X *0.1U/10V_4X *0.1U/10V_4X *0.1U/10V_4X *0.1U/10V_4X *0.1U/10V_4X *0.1U/10V_4X *0.1U/10V_4X E@1000P/50V_4X E@220P/50V_4X
<B3A_20120209> <B3A_20120207>
1
add (TOP: -5515, 6125) add (TOP: -490, 1825) *H-C256D146PT *H-C256D146PT H-TC236D161PB H-TC236D161PB H-TC236D161PB
VIN VIN VIN VIN VIN VIN VIN VIN VIN
<B3A_20120130>
change value to H-C256D146PT <B3A_20120130>
C553 C554 C555 C559 C561 C563 C572 C594
C602
change value to H-TC236D161PB
E@0.1U/25V_4X E@1000P/50V_4X *0.1U/25V_4X E@1U/25V_6X E@1000P/50V_4X *0.1U/25V_4X E@1000P/50V_4X E@1000P/50V_4X E@220P/50V_4X
<B3A_20120130> <B3A_20120207> HOLE21 HOLE20 HOLE22 HOLE23 HOLE14
add (TOP: -4560. 5970) add (BOT: -540, 1495) 7 6
8 5
+1.5VSUS +1.5VSUS +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 9 4
1
2
3
C558 C591 C577 C578 C579 C580 C581 C582 C597
*H-C276D118P2 *H-C91D91N *H-C91D91N *H-C91D91N
E@680P/50V_4X *0.1U/10V_4X E@2200P/50V_4X *0.1U/10V_4X *0.1U/10V_4X *0.1U/10V_4X *0.1U/10V_4X *0.1U/10V_4X E@2200P/50V_4X *HG-C276D118P2-A
<B3A_20120130> HOLE15 HOLE16 HOLE17 HOLE18 HOLE19

add (TOP: -2390, 525) 7 6 7 6 7 6 7 6 7 6
+3VPCU +5V_S5 +5V_S5 +5V_S5 +5V_S5 +5V_S5 +1.8V +1.1V 8 5 8 5 8 5 8 5 8 5
9 4 9 4 9 4 9 4 9 4
A C576 C585 C586 C588 C589 C598 C590 C592 A

1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
*0.1U/10V_4X E@2200P/50V_4X E@2200P/50V_4X E@2200P/50V_4X *0.1U/10V_4X E@2200P/50V_4X *0.1U/10V_4X E@2200P/50V_4X
*HG-C276D118P2 *HG-C276D118P2 *HG-C276D118P2 *HG-C276D118P2 *HG-C276D118P2
<B3A_20120130> <B3A_20120130>
+VGPU_CORE HOLE24 HOLE25 HOLE26 HOLE27
add (BOT: -10740, 5500) add (TOP: -2695, 1340) Quanta Computer Inc.
C604 PROJECT : BY7D
E@220P/50V_4X Size Document Number Rev
1
1
<B3A_20120207> KBC/TP/FP CONN. 1A
*O-BY7-1 *H-C236D118P2 *H-TC197BC131D91P2 *H-TC197BC131D91P2
close to PC132 Date: Wednesday, March 21, 2012 Sheet 33 of 45
5 4 3 2 1
5 4 3 2 1
EC <KBC> <B3A_20120130>
change R223 to 2.2 ohm (ESD solution for EC)
Intel Turbo mode only <CPU>
APU_PROCHOT#_VDDIO (4,7) 34
3
unstuff D31 and stuff R223
Q23
+3VPCU D31 *RB500V-40_100MA
+3V H_PROCHOT_EC 2
L21 HCB1608KF-601T10_1A +A3VPCU +3V_VDD_EC R223 2.2_6

FDV301N_200MA
R221 C370 C361 C362 C363 R224
1
2.2_6 100K_4
0.1U/10V_4X 10U/6.3V_6X 0.1U/10V_4X 10U/6.3V_6X
D C364 C365 C366 C367 C368 C369 C717 8769AGND D
115
102
19
46
76
88
4
10U/6.3V_6X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X ESD@39P/50V_4N U5030
AVCC
VDD
VCC1
VCC2
VCC3
VCC4
VCC5
<C3B_20120306> R225 *100K/F_4
reserve for ESD
H=1.6mm +3VPCU
SMBUS Table
(7,28) LFRAME# 3
LFRAME GPIO90/AD0
97 TEMP_MBAT (36)
SM BUS PU <KBC>
126 98 ICMNT SMBUS Devices Address
(7,28) LAD0 LAD0 GPIO91/AD1 ICMNT (36)
127 A/D 99 AC SET_EC
(7,28) LAD1 LAD1 GPIO92/AD2 AC SET_EC (36)
128 100 USB_BUS_SW4 1 Battery
(7,28) LAD2 LAD2 GPIO93/AD3 USB_BUS_SW4 (24)
1 108 R179 0_4
(7,28) LAD3 LAD3 GPIO05/AD4 USB_SC_OC# (6,24)
(7) PCLK_591 2 96 GPU_MAINON (42)
LCLK GPIO04/AD5 NBSWON#_R R202 1.2K/F_4
GPIO03/AD6 95 NBSWON# (33)
(7) CLKRUN# CLKRUN# 8 94 PCH SML1
GPIO11/CLKRUN GPIO07/AD7 SLP_S3# (6)
<B3A_20120130>
+3VPCU
2
(6) EC_A20GATE 121
GPIO85/GA20 change R202 to 1.2K ohm (ESD solution for EC) 3D Sensor 32H
D/A GPIO94/DA0
101 GPU_VRON (42)
MBCLK R222 4.7K_4
(6) EC_KBRST# 122 KBRST/GPIO86 GPIO95/DA1 105 VFAN1 (32) EC EEPROM A0H
106 MBDATA R227 4.7K_4
GPIO96/DA2 WLAN_P (28)
(6) EC_EXT_SCI# EC_EXT_SCI# 29 LPC 2ND_MBCLK R101 4.7K_4 VGA Board Thermal Sensor 98H
ECSCI/GPIO54 2ND_MBDATA R100 4.7K_4
6 3ND_MBCLK R229 4.7K_4 3 Touch Sensor 58H
GPIO24 EC_FPBACK# (30)
64 3ND_MBDATA R230 4.7K_4
GPIO01/TB2 ACIN (36)
(6) LPCPD# 124 79 SKU_STRAP_2 HDMI CEC 34H
GPIO10/LPCPD GPIO02
93 LID591# (30)
GPIO06/IOX_DOUT
(6,7,28,29) PLTRST# 7
LREST GPIO16
114 TP12 Light Sensor 52H
109 PWRLED#
GPIO30 PWRLED# (35)
(24) USB_NORMAL_EN# 123 GPIO67/PWUREQ GPIO36 15 VRON (41)
80 SKU_STRAP_3
SERIRQ GPIO41 H_PROCHOT_EC
125 17 SHBM
(7) SERIRQ SERIRQ GPIO42/TCK
GPIO43/TMS
20
TP5
AMP_MUTE# (27)
Strap <KBC>
R188 0_4 9 21 SHBM=0: Enable shared memory with host BIOS
(6,24) USB_NORMAL_OC# GPIO65/SMI GPIO44/TDI ID (36)
GPIO 24 USB_BUS_SW3 RF_EN R231 10K_4
GPO47/SCL4 USB_BUS_SW3 (24) Disabled ('1') if using FWH device on LPC.
GPIO50/PSCLK3/TDO 25 D/C# (36)
54 26 Enabled ('0') if using SPI flash for both system BIOS and EC firmware
(33) MX0 KBSIN0 GPIO51 S5_ON (37)
55 27 R203 0_4
(33) MX1 KBSIN1 GPIO52/PSDAT3/RDY DISPON_I (30)
56 28 HWPG
(33) MX2 KBSIN2 GPIO53/SDA4
(33) MX3 57 73 SLP_S5# (6)
KBSIN3 GPIO70 MPWROK +3VPCU
58 74
(33)
(33)
MX4
MX5 59
KBSIN4
KBSIN5
GPIO71
GPIO72
75 RSMRST_GATE#
MPWROK (10)
RSMRST_GATE# (6)
ID EEPROM <KBC> U16
60 82 USB_BUS_SW2_EC R149 0_4 2ND_MBCLK 6 1
(33)
(33)
MX6
MX7 61
KBSIN6
KBSIN7
GPIO75
GPO76/SHBM 83 RF_EN
USB_BUS_SW2 (24)
RF_EN (28) 2ND_MBDATA 5
SCL
SDA
A0
A1 2 0.003A(20mils)
84 CEC_EC_HP (25) 3
GPIO77 DNBSWON#_uR R233 *0_4 A2
(33) MY0 53 91 DNBSWON# (6)
C KBSOUT0/JENK GPIO81 GPIO82 C
(33) MY1 52 110 7 8
KBSOUT1/TCK GPO82/IOX_LDSH/TEST TP6 D32 1SS355_100MA WP VCC
(33) MY2 51 KBSOUT2/TMS GPO84/IOX_SCLK/XORTR 112 GND 4
50 107 Remove Zero Power ODD funciton C371
(33) MY3 KBSOUT3/TDI GPIO97
49 KB TP11 M24C08-WMN6TP
(33) MY4 KBSOUT4/JENO
48 0.1U/10V_4X
(33) MY5 KBSOUT5/TDO
47 31 SKU_STRAP_1
(33) MY6 KBSOUT6/RDY GPIO56/TA1
(33) MY7 43 KBSOUT7 TIMER GPIO20/TA2/IOX_DIN_DIO 117
TP7
ADDRESS: A0H
(33) MY8 42 63 FANSIG1 (32)
KBSOUT8 GPIO14/TB1
(33) MY9 41
KBSOUT9/SDP_VIS
(33) MY10 40
KBSOUT10/P80_CLK RF_LED#
(33) MY11 39 KBSOUT11/P80_DAT GPIO15/A_PWM 32 RF_LED# (35)
38 118
(33)
(33)
MY12
MY13 37
KBSOUT12/GPIO64
KBSOUT13/GPIO63 TIMER
GPIO21/B_PWM
GPIO13/C_PWM
62
SUSLED_EC# (35)
BAT_SAT0# (35)
SPI FLASH <KBC>
(33) MY14 36 65 BAT_SAT1# (35)
KBSOUT14/GPIO62 GPIO32/D_PWM
(33) MY15 35 22 SUSON (38)
KBSOUT15/GPIO61/XOR_OUT GPIO45/E_PWM
(33) MY16 34 GPIO60/KBSOUT16 GPIO40/F_PWM 16 MAINON (37,39,40)
(33) MY17 33
GPIO57/KBSOUT17 GPIO66/G_PWM
81 CAPSLED (33) BY6-A1A Del SPI ROM
GPIO33/H_PWM 66 EC_DPST_PWM (30) <C3B_20120306>
reserve for PWM signal issue
(6,36) MBCLK 70 14 BT_RFCTRL (28)
GPIO17/SCL1 GPIO34
(6,36) MBDATA 69
2ND_MBCLK GPIO22/SDA1
(4) 2ND_MBCLK
2ND_MBDATA
67
GPIO73/SCL2 SMB TP_ON_OFF
(4) 2ND_MBDATA 68 113
3ND_MBCLK GPIO74/SDA2 GPIO87/SIN_CR
(25,32) 3ND_MBCLK
3ND_MBDATA
119
GPIO23/SCL3 IR GPIO46/TRST
23
LAN_P R239 10K_4
+1.1V_DUAL_EN (40)
(25,32) 3ND_MBDATA 120 111
GPIO31/SDA3 GPO83/SOUT_CR/TRIST
LAN_P (26)
R358 0_4
FCH_SPI_SI (8)
72 86 SPI_SDI_uR R242 *100K/F_4
(33) TPCLK GPIO37/PSCLK1 F_SDI/F_SDIO1
71 87 SPI_SDO_uR R489 33_4
(33) TPDATA GPIO35/PSDAT1 F_SDIO&F_SDIO0 FCH_SPI_SO (8)
GFXPG_1V_EN 10 PS/2 FIU 90 SPI_CS0#_uR R490 33_4 MX25L3205DM2I-12G: AKE39FP0Z00
(7,39,42) GFXPG_1V_EN GPIO26/PSCLK2 F_CS0 FCH_SPI_CS0# (8)
11 92 SPI_SCK_uR R491 33_4
(24) USB_SC_EN# GPIO27PSDAT2 F_SCK FCH_SPI_CLK (8)
W25Q16BVSSIG: AKE38FP0N01
(7,10) RTC_CLK 77
GPIO00/EXTCLK GPIO55/CLKOUT/IOX_DIN_DIO
30 Make sure that the rise time of VCC_POR is less than 10?sec.
85 VCC_POR# R243 4.7K_4 +3VPCU
VCC_POR
VCORF
12 VTT
AGND
GND1
GND2
GND3
GND4
GND5
GND6
13 104 VREF_uR R309 *0/short_4 +A3VPCU

PECI VREF
<Note>
When the PECI interface isn't used, VTT should be connected to GND. <B3A_20120207> INTERNAL KEYBOARD STRIP
change to short pad SET
5
18
45
78
89
116
103
44
NPCE885LA0DX
+3VPCU
<KBC>
VCORF_uR
PCLK_591 MY0 R245 10K_4

B NPCE791LA0DX: AJ007910F00 (w/o CIR) B
+3V L22 0_6
R246 R257 *10K_4 SERIRQ FCH Integrated PU 8.2K to +3V C374

R258 *10K_4 CLKRUN# FCH Integrated PU 7.5K to +3V
*22_4 1U/10V_6X LED PU/PD <LED> HWPG circuit <KBC>
8769AGND
C375 +3V_S5 <B3A_20120130>
*10P/50V_4C R261 *10K_4 EC_EXT_SCI# change value to 50273-0037L-001
FCH Integrated PU 10K to +3V_S5
CN18
RF_LED# R247 NAOAC@10K_4 +3VPCU +3V
+5V
TP_ON_OFF
1 R249 AOAC@10K_4
2 +5V_S5
LAN_P
3 R251 R252
Close to U11
*10K_4 10K_6
*DEBUG@50273-0037L-001
+5VPCU
AC SET_EC ICMNT R154 0_4

PWRLED# R248 10K_4
D45 *1SS355_100MA R260 *0/short_4 HWPG
C377 C378 TP interface PU <KBC> SUSLED_EC# R266 10K_4
(37) SYS_HWPG
R155 0_4 <B3A_20120202>
*10U/6.3V_8X *10U/6.3V_8X BAT_SAT0# R259 10K_4
+3V D46 *1SS355_100MA change to short pad
(38) HWPG_1.5V
BAT_SAT1# R265 10K_4
R255 *10K_4 TPCLK <C3B_20120306>
8769AGND 8769AGND R256 *10K_4 TPDATA R156 *0_4
unstuff R156 for HWPG issue
D47 *1SS355_100MA
(40) 1.8V_PWROK
R160 0_4
D34 *1SS355_100MA
(40) +1.1V_HWPG
SKU strap pin <KBC> Power Button <KBC> R162 0_4
D40 *1SS355_100MA
(39) +1V_HWPG
+3VPCU
A A
SKU_STRAP_1(GPIO56) SKU_STRAP_2(GPIO02) SKU_STRAP_3(GPIO41) SKU
0 0 0 Brazos UMA R263 R264 R279 DNBSWON#_uR C376 *0.1U/10V_4X

*10K_4 *10K_4
EV@10K_4
0 0 1 Brazos DIS
SKU_STRAP_3 NBSWON#_R SW2 *SHORT_ PAD
SKU_STRAP_2
0 1 0 COMAL UMA SKU_STRAP_1
D36
0 1 1 COMAL DIS *LCP0G050M0R2R
R267 R278 R268
IV@10K_4 10K_4 10K_4
1 0 0 Deccan UMA
PROJECT :BY7D
1 0 1 Deccan DIS Size Document Number Rev
1A
EC NPCE795CA0DX
5 4 3 2 1
5 4 3 2 1
RF LED
LED <LED>
BATERRY
<LED>
35
+5VPCU
3
+5V R64 NAOAC@0_4 2 1 RF_LED_R R140 1.2K/F_4
LED3 -BATLED0 R139 2.2K_4 RF_LED# (34)
2
BAT_SAT0# (34) R66 AOAC@0_4 LED4 12-21/S2C-AQ2R2B/2C
(Amber)
(White) +5V_S5
1
3 -BATLED1 R141 1.2K/F_4 (Amber)

D BAT_SAT1# (34) D
12-12Z/S2ST3D-C31/2C(QN)
POWER <LED> ESD Protect <ESD>

+5VPCU
LED1 2 -PWRLED R135 *1.5K/F_4 PWRLED#

PWRLED# (34)
1
-PWRLED -BATLED0 RF_LED_R

SUSLED R137 1.2K/F_4 SUSLED_EC# 1 1 1
3
SUSLED_EC# (34)
3 3 3
12-11Z/T3D-CP2Q2B12Y/2C(QN) SUSLED -BATLED1
2 D2033 2 D2034 2 D2035
*PJMBZ5V6 *PJMBZ5V6 *PJMBZ5V6
C C
LED P/N Behavior res

BEWY0007ZA0 power on: White LED bright R135: stuff 1.5K
(White/Amber) sleep: Amber LED blink R137: stuff 1.2K
BEWH0051Z00 power on: White LED bright R135: unstuff
(White) sleep: White LED blink R137: stuff 1.5K
B B
A A
PROJECT : BY7D
1A
LED
5 4 3 2 1
5 4 3 2 1
PCN1
4 DC_JACK 1
PF1
F1206HA15V024TM
2 VA0
VA1 PD1
1
3 VA2 1
0.01_3720
PR1
R1
2 VA3
1
2
PQ1
TPCA8109
5
VIN
1
2
PQ27
TPCA8109
5
36
BAT-V
2 3 3
3
SBR1045SP5-13
1
PC1 PC33 PC2 PC34 PC20 PR22 PC95
4
2 1000P/50V_4X E@0.1U/50V_6X 1000P/50V_4X E@0.1U/50V_6X 0.1U/25V_4X 220K/F_4 1U/25V_6X PR127
PD2 33K_6
D
1 D
PR105 PR109
2
<C3B_20120312> 20111026 TVS_SMAJ20A 10/F_6 10/F_6
PD3 20111026 PC101 PR126
50322-0044L-001
stuff PC33,PC34(0.1uF) for EMI stuff PC1,PC2 for EMI 1SS355_100MA
PC33(TOP: -2270, 6920)
( Near by sense R side) stuff PC95,PC101 for EMI 2200P/50V_4X 10K_6
1 6
PC34(TOP: -2065, 6805)
PR20 2 5
3
220K/F_4
3 4
PQ28
PR12 CSIN PQ4 2 2N7002K_300MA
(34) D/C#
82.5K/F_6 IMD2AT108
+3VPCU
CSIP
(34) AC SET_EC
1
VIN
10U/6.3V_8X
PR138 B-TEST change

PC18
PR10 10K/F_4 PC76 1U/6.3V_4X

10K/F_4 B-TEST DEL 1 2
10U/25V_8X
10U/25V_8X
10U/25V_8X
*2200P/50V_4X
*E@10U/25V_8X
0.1U/25V_4X
PC82
PC15
PC16
PC17
PC85
PC87
B-TEST DEL B-TEST change
PR33
( Near by IC side) PC68 4.7_6 B-TEST change
0.1U/10V_4X PC24 1U/6.3V_4X
1 2
<C3B_20120309>
ACIN
33
32
31
30
28
27
26
21
C C
(34) ACIN stuff PC82,PC85
5
B-TEST change +3VPCU
PC91 0.1U/10V_4X
CSSP
VDDP
NC
GND
GND
GND
GND
CSSN
VCC
PQ24
PR122 PC89
2.7_6 0.1U/50V_6X 4 AON7410
(6,34) MBDATA MBDATA 11 25
VDDSMB BOOT
0.01_3720
3
2
1
(6,34) MBCLK MBCLK 9 24 88731A_U_GATE PR129
SDA UGATE
PL2
10 23 88731A_PHASE 1 2 BAT-V
SCL PHASE
0.1U/25V_4X PC145
10U/25V_8X PC69
10U/25V_8X PC99
PD4 3.3UH_7X7_TOK
TVLST2304AD0 13 20 88731A_L_GATE
ID MBDATA ACOK LGATE PQ26 PR102
1 CH1 CH4 6
PC93 2.2/F_6
2 5 +3VPCU PR139 0.1U/25V_6X 19 4 AON7410
VN VP 49.9/F_6 PU4 PGND PR34 PR44
TEMP_MBAT 3 4 MBCLK DCIN 22 ISL88731CHRTZ-T 10/F_6 10/F_6
CH2 CH3 DCIN PC66
3
2
1
PR16 B-TEST change 1000P/50V_4X
82.5K/F_6 3.2V 18
88731ACIN CSOP
2 ACIN ( Near by sense R side) 20111026
20111101 modify netname to ID_CN PC25
0.1U/10V_4X CSOP add PC145 for
PR15 3 ( Near by IC side) EMI
22K/F_6 VREF CSON
+3VPCU CSON 17
B B
BTS1E-9K8040 4 B-TEST change
B-TEST CHANGE ICOMP
NC 16
PR6 <C3B_20120307>
*100K_4 PR5 5
*0/short_4
change to short pad NC
B-TEST ADD FOR ESD PF2 15 PR25 100_4 BAT-V
F1206HA15V024TM VBF
10 6 VCOMP
MBAT+ 1 2 BAT-V 29 (Please place this R near by battery pack side)
1 1K_4 GND
GND
2
ICM
ID_CN NC
NC
3 ID (34)
4 TEMP_MBAT_C PR182
7
14
12
5 M-DATA
6 M-CLOCK PR104
7 2.21K/F_6
8 PC6 +3VPCU PR108
9 PC10 *10K/F_4 B-TEST DEL B-TEST DEL
11
2
PC5 47P/50V_4N
PR8 PR9 *1U/10V_4X PC70
PCN2 100/F_4 PR3 0.01U/25V_4X PR124
1
100/F_4 ICMNT (34)

100K_4 B-TEST change
47P/50V_4N MBDATA PC7 100_4
10U/6.3V_8X
1K_4 0.01U/25V_4X PC79
MBCLK B-TEST change
TEMP_MBAT (34) B-TEST DEL
PR4
08/29 change pin define
1
A PC3 A
0.01U/25V_4X
2
B-TEST change

PROJECT : BY7D
CHARGER-ISL88731C 1A
5 4 3 2 1
5 4 3 2 1
VIN
(Peak 0mA) VIN
37
10U/25V_8X
VIN
+5VPCU PC102
PC97
10U/25V_8X
PC108 0.1U/25V_4X
(4,14) SYS_SHDN#
PC105
PC103
1 2
0.1U/25V_4X PR39 (Peak 35mA)
2.2/F_6 10U/6.3V_6X
B-TEST change
+3VPCU +2VREF
PR149
D D
<C3B_20120307>
10U/6.3V_6X
1
1
*0/short_4 PC109 PC84
change to short pad PC74
0.1U/25V_6X 1U/6.3V_4X
2
PR13
PQ36 *0_2/S
5
B-TEST change B-TEST change
16
17
8
5
(Peak 9.212A ,AVG 6.499A) AON7410 PU5 PQ34
(Peak 3.418A, AVG 2.392A)
VREG3
VREG5
VIN
REF
OCP:11.5A 13 4 AON7410
EN TONSEL
4
5V_UGATE1 21 10 3V_UGATE2 4
OCP:5A
PC98 PR136 UGATE1 UGATE2 PR131 PC96
+5V_S5 1 25V_BST1 22 9 1 2 +3V_S5
1
2
3
BOOT1 BOOT2
3
2
1
PL7 B-TEST change 0.1U/25V_6X 2.2_6 RT8223P 2.2_6 0.1U/25V_6X PL6
+5V_1 5V_PHASE1 20 11 3V_PHASE2 +3.3V_1
2.2UH_7X7_TOK PHASE1 TOP Side PHASE2 B-TEST change 2.2UH_7X7_TOK
5
PC120 5V_LGATE1 19 12 3V_LGATE2
PR155 LGATE1 LGATE2
220U/6.3V_7343P_E25b
24
ENTRIP1
ENTRIP2
SKIPSEL
+ 2.2/F_6 5V_FB1 VOUT1 PR153
2 7
FB1 OUT2 PC119
4 4
EMC
GND
GND
PR123 DDPWRGD_R 23 5 3V_FB2 2.2/F_6 PR110 +
PGOOD FB2
220U/6.3V_7343P_E25b
*0_2/S PQ35 PQ33 PR116 6.8K/F_4
*0_2/S
1
2
3
18
14
25
15
3
2
1
PC111 AON7702A AON7702A PC104
1000P/50V_4X B-TEST change B-TEST change
PR113 PR111 1000P/50V_4X
Rds(on) 13m ohm
15.4K/F_4 162K/F_4
B-TEST change PR115

+3VPCU Rds(on) 13m ohm
69.8K/F_4
PR107 <B3A_20120210>
1
PR112 PR148
10K/F_4 PR37 *0_4/S
change PC119 to 220U/6.3V_7343P_E25b CC7343
C C
10K/F_4 *0/short_6 PR114
B-TEST change
2
10K/F_4
PC37 <C3B_20120307> +3VPCU
2 (34) S5_ON
0.1U/25V_6X
PD7
change to short pad
B-TEST change BAV99W-7-F_150MA 3
1
PR130
0.1U/25V_4X
PC50
2 *10K/F_4
3V_LGATE2
3
PC110
1 PD8 0.1U/25V_6X DDPWRGD_R
SYS_HWPG (34)
PR158 B-TEST change
BAV99W-7-F_150MA
+15V_ALWP B-TEST change
+15V
0.1U/25V_6X
+5V_S5
PC117
22_8
+3V_S5 <C3B_20120308> +3V_S5

+15V
B-TEST change change power source
VIN
+3V
2N7002KDW_115MA
PR54
1
2
5
6
PR24 1M/F_4
1
2
5
6
1
2
5
6
B-TEST change 1M/F_4 PR19
22_8 B-TEST change MAIND 3 PQ18
2N7002KDW_115MA MAIND AO6402A GPU_MAIND 3 PQ17 MAIND 3 PQ39
MAIND (38) (38,40,42) GPU_MAIND EV@AO6402A AO6402A
4
4
6
B
B-TEST change PQ5A TOP Side B
4
3
5 TOP Side
PR32 2
2 1M/F_4 5 2 PQ9B
(34,39,40) MAINON PC42
3
PQ5B PQ9A 2200P/50V_4X

+3V
1
PQ3 2N7002KDW_115MA
+3V_GPU
1
*22_8 +5V (Peak 1.237A, AVG 0.866A)

PR35 +1.1V (Peak 0.06A)
100K_4 22_8 PR56
(Peak 4.7683A, AVG 3.338A)
PR145 2N7002KDW_115MA
LTC044EUBFS8TL_30MA PR55
*22_8 +1.5V
+5V
3
PQ8
*2N7002K_300MA
1
20111028 unstuff
PR55,PQ8
A A
PROJECT : BY7D
System 3V/5V(TPS51123A) 1A
5 4 3 2 1
5 4 3 2 1
<C3B_20120307> PR23
+3V_S5 S3_1.5V S5_1.5V
38
change to short pad
Be careful to this two net name. *0/short_4
1
PR120 S3_1.5V PR137 <C3B_20120307>
SUSON (34)
*10K/F_4 change to short pad VIN
200K_4
PR125
PR132
76.8K/F_4
PR141 *0_4
S5_1.5V
SUSON (34)
2
D *0/short_4 D
(34) HWPG_1.5V
PR143 PC107 20111026
PR147
100K_4 0.1U/25V_6X
stuff PC113 for EMI
10U/25V_8X
10U/25V_8X
PC112
PC41
2.2/F_6 B-TEST CHANGE PC113
OCP:19A
23
22
21
20
19
18
17
16
0.1U/25V_4X
(Peak 0.5A, AVG 0.35A) PU6 (Peak 16.32A, AVG 11.5A)
5
PGOOD
MODE
TRIP
PwPad-2
PwPad-1
PwPad
S3
S5
1 15 PQ37 f : 400k Hz
+SMDDR_VTERM VTTSNS VBST
2 14 1.5SUS_HG 4 AOL1428A ESR : 9mΩ
+1.5VSUS_SRC VLDOIN DRVH
10U/6.3V_6X
10U/6.3V_6X
3 TPS51216RUKR 13
1
2
3
VTT SW PL3
PC77
PC72
VDDQSNS
4 12 1.5UH_10X10
VTTGND V5IN
PwPad-3
PwPad-4
PwPad-5
1.5SUS_PHASE +1.5VSUS_SRC
+1.5VSUS
REFIN
PGND
VREF
B-TEST CHANGE 5 11
GND
VTTREF DRVL
5
+5V_S5
PQ30
PR134 PC114
24
25
26
10
1.5SUS_LG 4 +
+SMDDR_VREF
330U/2V_7343P_E9c
C 2.2/F_6 C
B-TEST DEL
1
2
3
1
AOL1412
(Peak 0.1A, AVG 0.07A) PC106
1U/6.3V_4X
2
B-TEST CHANGE PC94
PC45
PC78 0.22U/10V_4X 1000P/50V_4X *0.1U/10V_4X
B-TEST CHANGE
B-TEST CHANGE
RDSon=3.3m ohm
PC86
PR128
0.1U/10V_4X 10K/F_4 R1 Vout = (R1/R2) X 0.75 + 0.75
B +1.5VSUS +1.5VSUS B
5
PR133 R2 PC92
52.3K/F_4 0.01U/25V_4X
PQ16
1
2
5
6
GPU_MAIND 4
(37,40,42) GPU_MAIND EV@AON7202
MAIND 3 PQ2
(37) MAIND AO6402A
3
2
1
4
+1.5V_GPU
A
(Peak 4.1A, AVG 2.87A) A
+1.5V
(Peak 0.5A, AVG 0.35A)
PROJECT : BY7D
DDR 1A
5 4 3 2 1
5 4 3 2 1
39
D D
VIN
+5V_S5
10U/25V_8X
PC124
PC122
PC123 0.1U/25V_4X
5
PQ41
1 2
AON7410
1U/6.3V_4X B-TEST change 4
B-TEST change TPS51211DSCR
<C3B_20120307> PU7 PR160 PC121
PR162 51211_V5IN_2 7 10 1 2 (Peak 8.54A, AVG 6A)
change to short pad
3
2
1
124K/F_4 V5IN VBST
1 2 2 9 2.2_6 0.1U/25V_6X 51211_DRVH_2
PR163 TRIP DRVH PL8
51211_EN_2 3 8 51211_SW_2
(34,37,40) MAINON EN SW +1.0V
2.2UH_7X7_TOK
*0/short_4 51211_VFB_2 4 1
VFB PGOOD +1V_HWPG (34)
1
PC125
*1U/6.3V_4X 5 6
0.1U/10V_4X
+3V
5
B-TEST change TST DRVL
GND
GND
GND
GND
GND
2
*10K_4 PR161
PC129
1 11 +
GND PR164
PR165
16
15
14
13
12
470K/F_4 51211_DRVL_2 4 2.2/F_6 PC128
PR166 PR167 B-TEST change
R2 R1 PQ40
C C
2
AON7702A PC126
3
2
1
B-TEST change
10K/F_4 4.53K/F_4 1000P/50V_4X
PC127 RDSon=13m ohm
2 1
390U/2.5V_105CS_E10f
*39P/50V_4N
Vout=0.704V*(R1+R2)/R2
VIN +15V
PR67
EV@1M/F_4 PR68 +1.0V
EV@1M/F_4
B-TEST change
B-TEST change PQ14
5
EV@AON7202
PQ11A
3
EV@2N7002KDW_115MA 4
5 2
GFXPG_1V_EN 2
(7,34,42) GFXPG_1V_EN
3
2
1
PR69 PQ11B PC55
PQ12
EV@1M/F_4 EV@2N7002KDW_115MA EV@2200P/50V_4X
EV@2SK3018
3
B B
PR65 B-TEST change (Peak 2.84A ,AVG 2A )
1
EV@100K_4
EV@22_8
PR66 +1V_GPU
+1V_GPU
<C3B_20120306>
change PQ12 to 2SK3018 for HWPG issue
A A
PROJECT : BY7D
1A
+1.0V
5 4 3 2 1
5 4 3 2 1
+5V_S5
VIN
40
10U/25V_8X
PC143
PC139
PC141
1 2 0.1U/25V_4X
5
PQ43
1U/6.3V_4X B-TEST change AON7410
B-TEST change TPS51211DSCR
<C3B_20120307> PU8 PR181 PC144 4
PR176 51211_V5IN_1 7 10 1 2 (Peak 4.292A ,AVG 3.005A)
D change to short pad 57.6K/F_4 V5IN VBST D
1 2 2 9 2.2_6 0.1U/25V_6X 51211_DRVH_1
3
2
1
PR177 TRIP DRVH PL10
51211_EN_1 3 8 51211_SW_1 +1.1V_S5
(34) +1.1V_DUAL_EN EN SW 2.2UH_7X7_TOK
*0/short_4 51211_VFB_1 4 1 +1.1V_HWPG (34)
5
PC142 VFB PGOOD
*1U/6.3V_4X 5 6
0.1U/10V_4X
TST DRVL +3V_S5
GND
GND
GND
GND
GND
2
B-TEST change *10K_4 PR180
PC136
11 +
1
GND 51211_DRVL_1 PR174
4
PR179
16
15
14
13
12
470K/F_4 PQ44 2.2/F_6 PC137 +1.1V_S5
PR178 PR175 B-TEST change
R2 R1
3
2
1
AON7702A
2
PC138
B-TEST change
10K/F_4 6.04K/F_4 1000P/50V_4X PQ22
RDSon=14m ohm
5
AON7410
PC140
2 1
*39P/50V_4N 330U/2V_7343P_E9c 1.8V_PWROKD 4
<B3A_20120130>
Vout=0.704V*(R1+R2)/R2 change PC137 to 330U/2V_7343P_E9c CC7343
3
2
1
VIN
(Peak 3.832A, AVG 2.682A)
+1.1V
10U/25V_8X
PC80
+5V_S5 PC81
0.1U/25V_4X
PC26
C C
1 2
5
PQ23
1U/6.3V_4X AON7410
B-TEST change TPS51211DSCR B-TEST change
PU2 PR38 PC30 4
20111028 change PR41 value to 10K, PR40 51211_V5IN_3 7 10 1 2
48.7K/F_4 V5IN VBST
PC38 value to 0.22uF (for power sequence issue) (Peak 4A ,AVG 2.8A)
1 2 2 9 2.2_6 0.1U/25V_6X 51211_DRVH_3
3
2
1
TRIP DRVH PL1
PR41 51211_EN_3 3 8 51211_SW_3 +1.8V
(34,37,39) MAINON 10K_4 EN SW 2.2UH_7X7_TOK
51211_VFB_3 4 1 1.8V_PWROK
1.8V_PWROK (34)
1
5
PC38 VFB PGOOD +1.8V
0.22U/10V_4X 5 6
0.1U/10V_4X
TST DRVL +3V
B-TEST change
GND
GND
GND
GND
GND
2
10K_4 PR53 PQ10
PC88
11 +
1
5
GND 51211_DRVL_3 PR100 EV@AON7410
4
PR26
16
15
14
13
12
470K/F_4 <C3B_20120306> PQ25 2.2/F_6 PC75 B-TEST change

PR30 PR31
R2 R1 AON7702A
stuff PR53 for HWPG issue
3
2
1
B-TEST change GPU_MAIND 4
2
PC65 (37,38,42) GPU_MAIND
10K/F_4 15.8K/F_4 1000P/50V_4X

RDSon=14m ohm
3
2
1
PC29
2 1
(Peak 1.85A ,AVG 1.3A)
*39P/50V_4N
+1.8V_GPU
330U/2.5V_3528P_E9b
Vout=0.704V*(R1+R2)/R2
B B
VIN +15V
PR28 PR36
1M/F_4 1M/F_4
1.8V_PWROKD
3
PR27
1.8V_PWROK 2 1M/F_4 2
PQ6
PQ7A PC28
2SK3018 B-TEST change
PR48 2N7002KDW_115MA 2200P/50V_4X
1
100K_4
1
A <C3B_20120306> A
change PQ6 to 2SK3018 for HWPG issue
PROJECT : BY7D
1A
+1.1V/+1.8V
5 4 3 2 1
5 4 3 2 1
41
PR57
CPU_CORE_1
49.9/F_6
PR61
PR52
(4) CPU_VDD_FB_H SNS_POS_VDD_0 8380RSP1 8380CSN1
8380CSP1
6800P/50V_4X
*0/short_4 665/F_4 PC36
PR45
100P/50V_4N
470P/50V_4X
VRON (34)
PC44
PR62
2
PR47 +1.8V
PC43
(4) CPU_VDD_FB_L SNS_NEG_VDD_0 8380RSN1 *0/short_4
PR49 VIN <B3A_20120210>
665/F_4
*0/short_4 <C3B_20120307> 100K_4
D change PC44 value to 6800P/50V_4 D
PR58 change to short pad
<C3B_20120307>
PR150 <C3B_20120309>
change to short pad 49.9/F_6 10K/F_6
stuff PC118 PC40
PR42
8380VREF 2 1 CPU_PWRGD_SVID_REG (4)
27.4K/F_4
0.047U/25V_4X
PC39
1000P/50V_4X PR46
2200P/50V_6X
PC54
PC53
PC47
PC51
10U/25V_8X
10U/25V_8X
PC116
PC118
0.1U/50V_6X
*10U/25V_8X
*10U/25V_8X
PR159 2.2/F_4
PQ38
5
PR50 Close to Phase
Inductor
5.62K/F_4
8380HDR1 4
+5V_S5 NTC_10K_6
PR51 CPU_CORE
1
2
3
2011/09/20 for EMI 3.92K/F_4 CPU_CORE_1
8380RSN1
8380CSN1
8380RSP1
8380CSP1
8380SC
AOL1428A PL4
8380LX1
PR43 B-TEST change 0.56UH_7X7
+5V_S5
RB500V-40_100MA
20/F_6
DCR=3.7mohm
1
0.01U/25V_4X
0.22U/25V_6X
0.1U/10V_4X
PR146
1
PQ31 + (Peak 11.000A, AVG 7.700A)
42
41
22
24
23
20
21
19
18
17
38
39
40
VIN
PC35
PC32
2.2/F_6 PC52 PC46
PD6
4 AOL1412
RSN1
RSP1
CSN1
CSP1
HDR1
GNDA
GNDA
PWR_OK
GNDA
GNDA
GNDA
SC
EN
2
2
C PC31 PC100 C
1
2
3
8380VREF 1U/10V_4X 25 16 B-TEST change
COMPV1 LX1 PR29
26 15 1000P/50V_4X
8380VREF VDDA BST1 8380LDR1 330U/2V_7343P_E9c
27 VREF LDR1 14 2.2/F_6
28 PU1 13
TSET GNDP
PC27
0.22U/10V_4X
29 OZ8380ALN VDDP 12
8380TSET
ILIM PC22
8380ILIM
30 SVD HDR2 8
31 SVC BST2 10
8380VREF
2200P/50V_6X
32 9 1U/10V_4X PQ29
COMPV2 LX2
10U/25V_8X
0.1U/50V_6X
+5VPCU
GNDA
GNDA
GNDA
GNDA
GNDA
PC90
PC83
RSN2
CSN2
RSP2
CSP2
LDR2
VFIX
VIN
PC73
PR21
PG
2.2/F_6 8380HDR2
2.55K/F_4
49.9K/F_4
*0/short_4
4
PR152
PR142
PR144
PD5 (Peak 10.000A, AVG 7.000A)
33
34
1
2
3
5
4
6
7
11
35
36
37
<C3B_20120307> 1 2 +5V_S5 Close to Phase
1
2
3
8380RSN2
8380CSN2
8380RSP2
8380CSP2
change to short pad Inductor
8380VFIX
RB500V-40_100MA CPU_VDDNB_CORE_1 CPU_VDDNB_CORE
PC19 AOL1428A
DCR=3.7mohm
0.22U/25V_6X PL5
0.1U/10V_4X
PC21 0.01U/25V_4X 8380LX2

49.9K/F_4
10.2K/F_4
*49.9K/F_4
1000P/50V_4X
PR151
PR140
PC23
PR135
PC14
0.56UH_7X7
PR124 Change PN to CS29302FB01
0.1U/10V_4X
8380LDR2 PQ32 PR103
1
PC48
PR154 3.92K/F_4 +
2
+3V
PC49
PR156
B-TEST change 2.2/F_6
2
B-TEST change PR101
4
DB to SI modfiy PR119 5.62K/F_4
(4) CPU_SVD CPU_SVD PR18 *0/short_4 8380SVD 1.91K/F_4
1
2
3
PC115 NTC_10K_6 B-TEST change
B B
(4) CPU_SVC CPU_SVC PR17 *0/short_4 8380SVC PR157
1000P/50V_4X 2.2/F_4 330U/2V_7343P_E9c
8380VREF 2 PR11 1 8380RSN2 CPU_COREPG
8380VREF CPU_COREPG (4,10)
<C3B_20120307> 32.4K/F_4 AOL1412
change to short pad SNS_NEG_VDD_1
PR59 PR14 PC12
2 1 VIN
49.9/F_6 27.4K/F_4
PR63
PR7
(4) CPU_VDDNB_FB_L SNS_NEG_VDD_1 8380RSN2 PC11 0.047U/25V_4X
1.2K/F_4 1000P/50V_4X PC8
*0/short_4 PC13 100P/50V_4N
220P/50V_4X
PR64 8380CSP2
SNS_POS_VDD_1 PR2 8380RSP2 8380CSN2
(4) CPU_VDDNB_FB_H
1.2K/F_4
1
6800P/50V_4X
PC9
*0/short_4
PR121 PR118
PR117
<C3B_20120307> *100K/F_4 10K/F_4
PR60
change to short pad CPU_VDDNB_CORE_1
2
49.9/F_6 <B3A_20120210>
+3V *0/short_6
change PC9 value to 6800P/50V_4
Signal Ground Power Ground
<C3B_20120307>
change to short pad
A A

PROJECT : BY7D
1A
CPU CORE
5 4 3 2 1
1 2 3 4 5
+5V_S5
42
PC58 PR78
2 1
EV@1U/10V_4X EV@2.2/F_6 PR79

EV@2.2/F_6
<C3B_20120309>
stuff PC134
VIN
EV@10U/25V_8X
EV@10U/25V_8X
<C3B_20120307> PQ42 EV@FDMS3660S
PC134
OCP:25A
change to short pad
PC57
PC135
EV@0.1U/25V_4X
20
1
G1
D1
D1
D1
PC59 (Peak 21.6A ,AVG 15.12 )
EV@4.7U/10V_6X +3V_S5
LGATE
PVCC
A A
PR171 PC56 Total capacitor : 660 uF
S1/D2
EV@10K/F_4
2 19 ISL95870A_AGND *EV@2200P/50V_4X
PGND VCC
PR77
ISL95870A_AGND *0/short_6 9 ESR :4.5mΩ
PR81 PC60
3 18 f : 300k Hz
G2
GND BOOT
S2
S2
S2
EV@2.2/F_6 EV@0.1U/25V_6X Max. DCR=1.0m
5
4 17 B-TEST change 20111026
RTN UGATE EV@0.24UH_7X7
B-TEST change PL9
stuff PC132 for EMI
GFX_CORE_CNTRL1 5 16
(14) GFX_CORE_CNTRL1 VID1 PHASE +VGPU_CORE
PU3
PR85
GFX_CORE_CNTRL0 6 15
(14) GFX_CORE_CNTRL0 VID0 EN GPU_VRON (34)
20111028 PC131
EV@ISL95870AHRUZ-T *0/short_4 PR168 +
change PR84 to 68.1K,PR87 to 332K
EV@330U/2V_7343P_E9c
7 14 PC130 PC132 Seymour
SREF PGOOD GFXPG_1V_EN (7,34,39)
20111028 change to +3V_S5 EV@2.2/F_6 +
EV@330U/2V_7343P_E9c
R1 EV@0.1U/25V_6X
+3V_S5 8 13 ISL95870A_AGND PR95 GFX_CORE_CNTRL1 GFX_CORE_CNTRL0 +VGPU_CORE
PR84 SET0 FSEL PR96
*0_2/S
*EV@0.1U/50V_6X
EV@68.1K/F_4 PC133 *0_2/S 1 1 0.9V
9 12
SET1 VO
PC62
<C3B_20120307> 1 0 1.0V
OCSET
PR173 PR170
*EV@10K/F_4
EV@0.022U/16V_4X
change to short pad
0 1 1.05V
FB
*EV@10K/F_4
R2 B-TEST change
PC61
PR89 PR87 0 0 1.15V
10
11
GFX_CORE_CNTRL0 GFX_CORE_CNTRL1 EV@31.6K/F_4 EV@332K/F_4 B-TEST change
EV@1000P/50V_4X
R4 PR91 R7 B-TEST change
95870A_FB
PR172 PR169
*EV@10K/F_4 *EV@10K/F_4 Roc
R3 EV@4.3K/F_4 Seymour
B B
PR88
EV@590K/F_4 PC63 PR75 R1 60.4K/F_4
EV@10/F_6 PR76
PR93
EV@10/F_6 R2 31.6K/F_4
<20110922_Lincan> EV@0.1U/25V_6X
B-TEST change R3 590K/F_4
reserve, don't installed by default EV@3.09K/F_4
Csen PR92 R4 294K/F_4
ISL95870A_AGND
R5/R6 3.65K/F_4
EV@4.3K/F_4
R8 R7/R8 4.3K/F_4
PR82
EV@3.09K/F_4
R5
PR90 PR74
VCORE_VCCSSENSE
VCORE_VCCSSENSE (17)
EV@2.4K/F_4 *0/short_4
PR80 PR72
VCORE_VSSSENSE
VCORE_VSSSENSE (17)
EV@2.4K/F_4 *0/short_4
R6 <C3B_20120307>
VIN +15V
change to short pad +VGPU_CORE
C 20111110 change PR80,PR90 to 2.4K C
VIN
PR86
EV@1M/F_4 PR83
EV@1M/F_4 PR71 PR73
B-TEST change EV@1M/F_4 EV@22_8
GPU_MAIND
GPU_MAIND (37,38,40)
EV@LTC044EUBFS8TL_30MA PQ19A
3
3
EV@2N7002KDW_115MA
2 5 2 GPU_VRON 2
(34) GPU_MAINON 2
PR94 PQ19B PC64
PQ21 EV@1M/F_4 EV@2N7002KDW_115MA *EV@2200P/50V_4X PR70 PQ15
1
1
PQ13 EV@2N7002K_300MA
PR97 EV@LTC044EUBFS8TL_30MA EV@1M/F_4
1
EV@100K_4 B-TEST change
EV@22_8 B-TEST change
PR98
+1.5V_GPU
4
D D
PQ20B
EV@2N7002KDW_115MA
3
EV@22_8
PR99
PROJECT : BY7D
+1.8V_GPU
GPU 1A
1 2 3 4 5
5 4 3 2 1
+5VPCU
AC/DC Insert enable 43
+5_S5+-5% +5V
Power Tree Table AO6402A
RT8223 S5_ON enable P.33 MAIND enable

D D
+3VPCU
P.33 +3.3V
AC/DC Insert enable AO6402A
+3_S5 +-5% P.33 MAIND enable
S5_ON enable
AC System +3V_GPU
AO6402A
Charger
ISL88731 P.33 GPU_MAIND enable
DC P.31
AO6402
+1.5V
+1.5VSUS P.34 MAIND enable
SUSON enable
C C
TPS51216 +SMDDR_VTERM +1.5V_GPU

AON7202
SUSON enable GPU_MAIND enable
P.34
P.34
+SMDDR_VREF
SUSON enable
+1V_GPU
+1.0V AON7410
TPS51211 MAINON enable GPU_MAIND enable
P.35 P.34
CPU_CORE
OZ8380ALN VRON enable
B B
P.37 CPU_VDDNB_CORE
VRON enable
+VGPU_CORE
ISL95870A
P.38 GPU_VRON enable
+1.1V
+1.1_S5
TPS51211 AON7410
1.8V_PWROKD enable
P.36 +1.1V_DUAL_EN enable P.36
A A
+1,8V +1.8V_GPU Quanta Computer Inc.

TPS51211 AON7410 PROJECT : BY7D
P.36 MAINON enable GPU_MAIND enable Size Document Number Rev
P.36 Power Tree 1A
Date: Monday, December 26, 2011 Sheet 43 of 45

5 4 3 2 1
5 4 3 2 1
44
BY7D Power On Sequence: S5 > S0
+3V_RTC
D D
+VIN APU Power on sequence required:
+5VPCU/+3VPCU/+15V APU:
AC not present equal to LOW; AC present equal to High 1.GROUP A(VDD10,VDD18, VDDIO, VDD33)ramp before GROUP B(VDDCR,VDDNB)
ACIN
Power button from switch to EC
NBSWON#
To turn on dual power rails
S5+ NOT implemented
HUDSON-M2/M3:
S5_ON/S5_CORE_EN 1.+3V_S5 ramp before +1.1V_DUAL
S5+ implemented S5_CORE_EN S5+ implemented to turn off dual power rails 2.+3V ramp before +1.1V
3.+3V_RTC must ramp at least 5 secs before the +3V_S5
+3V_S5
+1.1V_DUAL
20ms delay at least
RSMRST_GATE# Seymour XT S3 package Power-on sequence

50ms Max
RTCLK All power rails reach nominal within 20ms

32ms Min 1 => +3V_GPU
Power button from EC to FCH 2 => +VGPU_CORE/+1V_GPU
PWR_BTN#_EC 3 => +VGPU_CORE PWRGD to enable +1.5V_GPU
C
4.=> +1V_GPU PWRGD to enable +1.8V_GPU C
SLP_S5# NOTE
SUS_ON 1.+3V to turn on +3V_GPU
+1.5V_SUS 2.+3V_GPU ready to enable +VGPU_CORE/+1V_GPU

+0.75V_DDR_VTT only will be shut down in S3 mode and for DDR3 SODIMM only ( +1V_GPU will ramp up before +VGPU_CORE )
APU GROUP A power +0.75V_DDR_VTT
3.+VGPU_CORE PWRGD to enable +1.5V_GPU
VDRAM_PWRGD
3.+1V_GPU PWRGD to enable +1.8V_GPU
SLP_S3#
RUN_ON
+5V/+3V
+1.0V/+1.8V
1.8V_PWRGD
+1.5V_RUN/+1.1V/+1.5V Default controlled by +3.3V
+1V_PWRGD
B B
APU GROUP B power +VDDNB_CORE
+VDD_CORE
VRM_PWRGD
98ms < T <150ms
FCH_PWRGD 50ms Max
APU_CLKP/N
38ms Max
APU_PWRGD
101ms < T <113ms
A_RST#(PLTRST#) 75ns < T <100ns
PCIRST# 1ms < T <2.3ms
APU_RST#
A A
5
4 3 2
Size
Date:
Document Number
Tuesday, March 06, 2012

1
PROJECT : BY7D
POWER SEQUENCE
Sheet 44 of 45
Rev
1A
5 4 3 2 1
45
MODEL BY7D
Model REV CHANGE LIST PAGE FROM
D D
1 A1A
2 A1A
A1A 3 A1A
BY7D MB
4 A1A
5 A1A
6 A1A
7 A1A
8 A1A
9 A1A
10 A1A
11 A1A
12 A1A
13 A1A
14 A1A
15 A1A
16 A1A
17 A1A
18 A1A
19 A1A
20 A1A
21 A1A
C
22 A1A C
23 A1A
24 A1A
25 A1A
26 A1A
27 A1A
28 A1A
29 A1A
30 A1A
31 A1A
32 A1A
33 A1A
34 A1A
35 A1A
36 A1A
37 A1A
38 A1A
39 A1A
40 A1A
41 A1A
42 A1A
43 A1A
44 A1A
B B
45 A1A
PROJECT MODEL : BY7D APPROVED BY: DATE:

DOC NO. 204
PART NUMBER: DRAWING BY: REVISON: A1A
A A
5
4 3 2
Size
Date:
Document Number
Change List
1
PROJECT : BY7D
Monday, December 26, 2011 Sheet 45 of 45

Rev
1A

.By7d Brazos 2.0 MB SCH (8L) - Ramp1 Final - (Mindy) - (E201203-6361) - 20120321C R1a 0312 PDF

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5 4 3 2 1

C UMI LINK POWER SYSTEM

LPC USB2-11 USB3.0 Con. +SMDDR_VTERM P38

GND PLANE PAGE

(11) M_A_CLKN3 L17 M_CLK_L3 M_DATA48 Y20 M_A_DQ48

M_DATA56 AC17 M_A_DQ56

(11) M_A_CS#2 U17 M1_CS_L0

(11) M_A_CS#3 V16 M1_CS_L1 M_VREF M23 +M_VREF

(11,12) M_A_RAS# U18 M_RAS_L

(11,12) M_A_CAS# V19 M_CAS_L

Quanta Computer Inc.

(25) INT_HDMI_TXDN2 INT_HDMI_TXDN2 IHM@0.1U/10V_4X C5584 PEG_HDMI_TXDN2 B8 TDP1_TXN0 Q5024 R9796

(41) CPU_VDDNB_FB_H R9818 0_4 VDDCR_NB_SENSE F4 VDDCR_NB_SENSE TEST36 N5 APU_TEST36 T5056

(41) CPU_VDDNB_FB_L R9820 0_4 F1 VSS_SENSE

(41) CPU_VDD_FB_L R9821 0_4 B4 RSVD_1

Thermal Management Signals +3V

To indicate SVI interface is active

R9852 1K/F_4 APU_ALERT#

Rset(Kohm)=0.0012T*T-0.9308T+96.147,Shut down on R9863 0_4

INT_CRT_RED R9866 IV@150/F_4

R9869 *0/short_8 CPU_CORE CPU_CORE CPU_CORE

1U/6.3V_4X 1U/6.3V_4X 10U/6.3V_8X C706 C704 C707 C711 C712

Quanta Computer Inc.

EC will Conflict with FCH, did not mount R315&R318

G2 *SHORT_PAD EC FCH Device I2C_Device(S)

I2Ce_1(M) I2Cf_2(M) Charger Battery ALL/S5

I2Ce_3(M) VGA Thermal

2 1 KSO_5 I2Cf_1(M) Lan WLan S5 Quanta Computer Inc.

Note : C5559 EV@0.1U/10V_4X

Note: CLK_PCIE_TRAVISP/N is 100MHZ non-SSC GPP_CLK5N LFRAME# LFRAME# (28,34)

Note: GPP_CLK(0:8)P/N is 100MHZ SSC capable R23

GPP_CLK8N APU_PG APU_PWRGD (4)

H7 S5_CORE_EN S5_CORE_EN is necessary to connect enable pin of

Quanta Computer Inc.

Date: Wednesday, March 21, 2012 Sheet 7 of 45

(31) SATA_TXP0 AK19

R684 NS&C@10K_4 BOARD_ID5 R683 S&C@10K_4

R703 IMR@10K_4 BOARD_ID10 R423 TEXTURE@10K_4

Date: Wednesday, March 21, 2012 Sheet 8 of 45

PLACE ALL THE DECOUPLING CAPS ON

+1.1V_S5 +1.1V +VDDPL_1.1V

Quanta Computer Inc.

Date: Wednesday, March 21, 2012 Sheet 9 of 45

OVERLAP COMMON PADS WHERE

Remove PCI_CLK2 function

-------- PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4 LPC_CLK0 LPC_CLK1 EC_PWM2 RTC_CLK

PULL FORCE IGNORE FUSION EC CLKGEN SPI ROM S5 PLUS MODE

R345 R401 R402 R351 R350

Quanta Computer Inc.

Date: Monday, March 19, 2012 Sheet 10 of 45

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

TERMINATOR DECOUPLING CAPACITOR 9.12A(VCC plane from source)

C5685 C5686 C5687

10U/6.3V_8X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 2.2U/6.3V_6X 0.1U/10V_4X *C@0.1U/10V_4X

C5703 C5704 C5705

Close to DIMM1 Quanta Computer Inc.

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

C 9.12A(VCC plane from source) C

TERMINATOR DECOUPLING CAPACITOR

+SMDDR_VTERM +SMDDR_VREF_DQ +SMDDR_VREF_CA

C5718 C5719 C5720

CHANNEL B: 512MB DDR3 (64M164pcs)