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RUN SW 5V 80
1A
ICTRL VFB 75
OVLO EXTVCC 47µF
70
IMON CURRENT
VPRG2
MONITOR 65
PLLIN/MODE ITH VIN = 12V
60 VIN = 24V
FREQ INTVCC
55 VIN = 48V
SGND PGND VIN = 72V
1µF
50
0.1 1 10 100 1000
7101 TA01a
LOAD CURRENT (mA)
7101 TA01b
Rev. 0
PGND
PGND
VIN
VIN
VIN
BOOST Voltage..........................................–0.3V to 110V 36 35 32 31 30
RUN Voltage..............................................–0.3V to 110V
VFB, PGOOD Voltages................................. –0.3V to 16V 27 BOOST
FREQ
PLLIN/MODE
CLKOUT
PGOOD
SS
ICTRL
IMON
VPRG1
UHE36(26) PACKAGE
36-LEAD (5mm × 6mm) PLASTIC QFN
TJMAX = 150°C, θJA = 38°C/W, θJC = 5°C/W
EXPOSED PAD (PIN 37) IS PGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT7101EUHE#PBF LT7101EUHE#TRPBF 7101 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C
LT7101IUHE#PBF LT7101IUHE#TRPBF 7101 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C
LT7101HUHE#PBF LT7101HUHE#TRPBF 7101 36-Lead (5mm × 6mm) Plastic QFN –40°C to 150°C
LT7101MPUHE#PBF LT7101MPUHE#TRPBF 7101 36-Lead (5mm × 6mm) Plastic QFN –55°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Rev. 0
Rev. 0
Burst Mode Efficiency at 5VOUT Burst Mode Efficiency at 12VOUT Burst Mode Efficiency at 3.3VOUT
100 100 100
fSW = 300kHz fSW = 300kHz fSW = 300kHz
95 FIGURE 14 CIRCUIT 95 FIGURE 15 CIRCUIT 95 FIGURE 16 CIRCUIT
90 90 90
85 85 85
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
80 80 80
75 75 75
70 70 70
65 65 65
VIN = 12V VIN = 24V VIN = 12V
60 VIN = 24V 60 VIN = 48V 60 VIN = 24V
55 VIN = 48V 55 VIN = 72V 55 VIN = 48V
VIN = 72V VIN = 100V VIN = 72V
50 50 50
0.1 1 10 100 1000 0.1 1 10 100 1000 0.1 1 10 100 1000
LOAD CURRENT (mA) LOAD CURRENT (mA) LOAD CURRENT (mA)
7101 G01 7101 G02 7101 G03
80 80 80
EFFICIENCY (%)
EFFICIENCY (%)
70 70 EFFICIENCY (%) 70
60 60 60
50 50 50
VIN = 12V VIN = 24V VIN = 12V
VIN = 24V VIN = 48V VIN = 24V
40 40 40
VIN = 48V VIN = 72V VIN = 48V
VIN = 72V VIN = 100V VIN = 72V
30 30 30
10 100 1000 10 100 1000 10 100 1000
LOAD CURRENT (mA) LOAD CURRENT (mA) LOAD CURRENT (mA)
7101 G04 7101 G05 7101 G06
80 80 80
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
70 70 70
60 60 60
50 50 50
VIN = 12V VIN = 24V VIN = 12V
VIN = 24V VIN = 48V VIN = 24V
40 40 40
VIN = 48V VIN = 72V VIN = 48V
VIN = 72V VIN = 100V VIN = 72V
30 30 30
10 100 1000 10 100 1000 10 100 1000
LOAD CURRENT (mA) LOAD CURRENT (mA) LOAD CURRENT (mA)
7101 G07 7101 G08 7101 G09
Rev. 0
EFFICIENCY (%)
80 80 6
75 75
70 70 4
65 65
ILOAD = 1A VIN = 12V
60 60 2
ILOAD = 500mA VIN = 24V
55 ILOAD = 100mA 55 VIN = 48V
ILOAD = 10mA VIN = 72V
50 50 0
0 20 40 60 80 100 0.2 1 2 0 10 20 30 40 50 60 70 80 90 100
INPUT VOLTAGE (V) FREQUENCY (MHz) VIN VOLTAGE (V)
7101 G10 7101 G11 7101 G12
Regulated Feedback Voltage vs Average Output Current vs VIN, Average Output Current vs
Temperature ICTRL Temperature
1.005 1.4 1.4
VPRG1 = FLOAT FIGURE 14 CIRCUIT FIGURE 14 CIRCUIT
1.004 VPRG2 = FLOAT
REGULATED FEEDBACK VOLTAGE (V)
1.001
0.8 0.8
ICTRL = 0.94V
1.000
0.6 0.6
0.999
VICTRL = 0.76V
0.998 0.4 0.4
ICTRL = 0.58
0.997
0.2 0.2
0.996
0.995 0 0
–55 –25 5 35 65 95 125 155 0 20 40 60 80 100 –55 –25 5 35 65 95 125 155
TEMPERATURE (°C) VIN VOLTAGE (V) TEMPERATURE (°C)
7101 G13 7101 G14 7101 G15
Peak Current Limit vs Output Current Monitor vs Output Current Monitor Error vs
Temperature Average Output Current Average Output Current
1.80 1.4 2.0
VICTRL = 1V FIGURE 14 CIRCUIT FIGURE 14 CIRCUIT
1.75
1.2
IMON VOLTAGE ERROR (%)
1.0
PEAK CURRENT LIMIT (A)
1.70
IMON VOLTAGE (V)
1.0
1.65 0
0.8
1.60
–1.0
0.6 VIN = 24V VIN = 72V
1.55
VIN = 48V VIN = 48V
VIN = 72V VIN = 24V
1.50 0.4 –2.0
–55 –25 5 35 65 95 125 155 0 0.2 0.4 0.6 0.8 1.0 1.2 0 0.2 0.4 0.6 0.8 1.0 1.2
TEMPERATURE (°C) AVERAGE OUTPUT CURRENT (A) AVERAGE OUTPUT CURRENT (A)
7101 G16 7101 G17 7101 G18
Rev. 0
1200
45
1050
900 40
TOP SWITCH
750
600 35
BOTTOM SWITCH
450
30
300
150 25
–55 –25 5 35 65 95 125 155 –55 –25 5 35 65 95 125 155
TEMPERATURE (°C) TEMPERATURE (°C)
7101 G19 7101 G20
1
6.0
0
4.0
–1
FREQ = GND (300kHz) 2.0
–2 FREQ = 12.5k (200kHz)
FREQ = 57.5k (2MHz) SHUTDOWN
FREQ = INTVCC (1MHz)
–3 0.0
–55 –25 5 35 65 95 125 155 0 15 30 45 60 75 90 105
TEMPERATURE (°C) VIN VOLTAGE (V)
7101 G21 7101 G22
PULSE–SKIPPING
15 MODE
500mA/DIV
SLEEP
10 FORCED
CONTINUOUS
MODE
5 500mA/DIV
7101 G24
10µs/DIV
SHUTDOWN VIN = 48V
ILOAD = 200µA
0 FIGURE 14 CIRCUIT
–55 –25 5 35 65 95 125 155
TEMPERATURE (°C)
7101 G23
Rev. 0
IL IL IL
500mA/DIV 500mA/DIV 500mA/DIV
SW Node Waveform at Full Load Synchronization to External Clock Start-Up from Shutdown
VSW VOUT
20V/DIV 2V/DIV
IL
500mA/DIV
VSW EXTERNAL
10V/DIV CLOCK ON VRUN
PLLIN/MODE 5V/DIV
1V/DIV
7101 G28 7101 G29 7101 G30
50ns/DIV 15µs/DIV 200µs/DIV
VIN = 48V VIN = 48V VIN = 48V
ILOAD = 1A ILOAD = 500mA Burst Mode OPERATION
FIGURE 14 CIRCUIT FIGURE 14 CIRCUIT FIGURE 14 CIRCUIT
1.4
1.2
VICTRL
500mV/DIV
VOUT 1.0
2V/DIV BW = 93kHz
0.8
IL
IL 0.6
250mA/DIV VIN = 24V
500mA/DIV
VOUT = 4V
0.4 RICTRL = 40.2k
7101 G31 7101 G32 IOUT(AVG) = 500mA
100µs/DIV 40µs/DIV 0.2 fSW = 300kHz
VIN = 48V VICTRL = 0.76V TO 1.12V PULSE FIGURE 14 CIRCUIT
PULSE–SKIPPING MODE VIN = 48V, VOUT = 4V 0
FIGURE 14 CIRCUIT FIGURE 14 CIRCUIT 0.1 1 10 100 300
FREQUENCY (kHz)
7101 G33
Rev. 0
40
AMPLITUDE (dBµV/m)
30
20
10
CLASS 5 PEAK LIMIT
LT7101
0
0 100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
FIGURE 17 CIRCUIT 7101 G34
48VIN TO 5VOUT AT 1A
fSW = 400kHz
PIN FUNCTIONS
RUN (Pin 3): Run Control Input. Holding this pin below voltage mode is selected using the VPRG1 and VPRG2 pins.
1.1V shuts off the switching regulator. Holding this pin If VPRG1 and VPRG2 are both floating, then a resistor from
below 0.7V reduces the quiescent current to approxi- RIND to SGND must be used.
mately 0.7µA. Place a resistor divider between VIN and ITH (Pin 9): Error Amplifier Output and Switching Regulator
this pin to use as an undervoltage lockout. Tie this pin to Compensation Point. Place compensation components
VIN to always enable the LT7101. between the ITH pin and SGND. Tie this pin to INTVCC for
SGND (Pin 6): Signal Ground. fixed internal compensation.
OVLO (Pin 7): Overvoltage Shutdown Input. If the voltage VFB (Pin 10): Regulator Feedback Input. When set to
on this pin exceeds 1.21V, then the switching regulator adjustable mode, use an external resistor divider between
is shut down and the SS pin is internally grounded. Tie the regulator output voltage and the VFB pin. For fixed out-
this pin to SGND to allow operation with VIN up to 105V. put voltage mode, tie VFB directly to the regulator output.
RIND (Pin 8): Sets the current used to create an internal FREQ (Pin 11): The frequency control pin for the internal
ramp that replicates the inductor current up-slope for low VCO. Connect this pin to SGND for 300kHz operation or
duty cycle operation. This pin generates a voltage that to INTVCC for 1MHz operation. Place a resistor to SGND
varies with the switching frequency. Place a resistor to on this pin to set the operating frequency between 200kHz
SGND on this pin equal to 1/(3.3 • L) to set the internal and 2MHz. Minimize the capacitance on this pin if Burst
ramp current. This pin can be left floating if fixed output Mode operation is used. This pin sources 40µA.
Rev. 0
Rev. 0
+
ITH
3.1V –
10µA
VOSC
SHDN INTVCC
SS
2 • BG
SOFT-START
VSNS
+ ∫dt
+ INTERNAL ITH CHARGE BOOST
1V
+ SW
PUMP
VOUT – ITHMIN
ERROR
R1 AMP INTERNAL VFB (VFBI) + CBST
VDUTY
VFB
+
ISENSE
R2 + 0.9V
CCA
AVG CURR – RECONSTRUCTION
UV GM AMP
VOSC SW
PK CURR VSNS
RCA +
– COMP
SGND
PWM – VPK L
COMP
– 1.1V
OV –
VPRG1 R PWM VOUT
+ VRAMP OV Q INTVCC
VOUT + S
SELECT
VPRG2 BG
LOGIC COUT
SHDN PGND
PGOOD 40µA VCO
0.42V +
SLEEP
VOSC + VSNS
ITH – BURST
10µA COMPARATOR
PFD REVERSE – +
CURRENT
–
MODE
PRESET ITHMIN COMPARATOR
CONTROL
HI/LO SYNC
DET
FREQ PLLIN/MODE CLKOUT
7101 BD
Rev. 0
inductor current to decrease. The bottom switch stays Figure 1. Typical Current Loop Operating Waveforms
on until the beginning of the next clock cycle, unless the
reverse current limit is reached and the reverse current Voltage loop compensation can be set externally using
comparator trips. The reverse current limit is 0.4A for the ITH pin, taking advantage of OPTI-LOOP compensa-
forced continuous mode and 0A for burst and pulse- tion to optimize the loop response. The compensation of
skipping modes. the voltage loop is essentially the same as for peak cur-
In closed-loop operation, the average current amplifier rent mode control. Alternatively, the ITH pin can be tied
creates an average current loop that forces the average to INTVCC to select internal voltage loop compensation.
sensed current signal to be equal to the internal ITH volt- When internal voltage loop compensation is selected,
age. Note that the DC gain and compensation of this aver- the LT7101 automatically adjusts the internal compensa-
age current loop is automatically adjusted to maintain tion based on switching frequency to maintain a fast and
an optimum current-loop response. The error amplifier stable voltage loop.
adjusts the ITH voltage by comparing the divided-down
Power and Bias Supplies (VIN, SW, BOOST, INTVCC,
output voltage (VFBI) with a 1.0V reference voltage. If the
EXTVCC Pins)
load current changes, the error amplifier adjusts the aver-
age inductor current as needed to keep the output voltage The VIN pins on the LT7101 are used to supply voltage
in regulation. to the drain terminal of the internal high side N-channel
Rev. 0
Rev. 0
Rev. 0
Rev. 0
Rev. 0
Rev. 0
tance should be chosen according to: FIXED VOUT f = 300kHz f = 1MHz f = ADJ
1.2V 10μH 3.3µH L = 3.1/f
⎛ V OUT ⎞ ⎛ V OUT ⎞ 1.8V 15µH 4.7µH L = 4.6/f
L=⎜ ⎟ ⎜ 1–
⎝ f • ΔIL(MAX ) ⎠ ⎝ V IN(MAX ) ⎟⎠ 2.5V 22µH 6.8µH L = 6.7/f
3.3V 33µH 10µH L = 9.9/f
The LT7101 contains a fast, average current limit loop 3.6V 33µH 10µH L = 9.9/f
that limits the DC output current to a value determined by 5V 47µH 15µH L = 14.6/f
the voltage on the ICTRL pin. (See Average Output Current 12V 100µH 33µH L = 31.5/f
Limit and Monitor section for details.) However, some 15V 100µH 33µH L = 31.5/f
applications may experience inductor current transients
that are limited by the peak current limit comparator,
which tracks nominally 0.53A above the average current Inductor Core Selection
limit set point. To avoid saturation, choose an inductor Once the value for L is known, the type of inductor must be
with a saturation current ISAT such that: selected. Actual core loss is independent of core size for a
V – 0.4 fixed inductor value but is very dependent on the induc-
ISAT > ICTRL + 0.68A tance selected. As the inductance increases, core loss
0.77
decreases. Unfortunately, increased inductance requires
This enables the use of an inductor with a current rating more turns of wire leading to increased copper loss.
that fits the needs of a given application. If the average Ferrite designs exhibit very low core loss and are pre-
output current limit is set to the default value of 1.11A, ferred at high switching frequencies, so design goals can
then an inductor with ISAT > 1.9A is required. However, if concentrate on copper loss and preventing saturation.
the average current limit is set to 0.6A (VICTRL = 0.89V), Ferrite core materials saturate hard, meaning the induc-
then an inductor with ISAT > 1.4A may be used. Note that tance collapses abruptly when the peak design current is
if there is a varying voltage on the ICTRL pin, always use exceeded. This collapse will result in an abrupt increase
the highest value present on ICTRL when calculating the in inductor ripple current, so it is important to ensure the
required inductor saturation current. See Average Output core will not saturate.
Current Limit and Monitor section for details on setting
the average current limit.
Rev. 0
not leave the RIND pin floating when adjustable VOUT mode CD ZIN
CBULK CF
is selected. If the RIND pin is left floating and adjustable RD
VOUT mode selected (VPRG1 and VPRG2 are both floating),
the LT7101 will detect this as a fault condition and will OPTIONAL
7101 F04
not operate.
The allowable current range on the RIND pin is between Figure 4. Input Filter with Optional Damping Network
8μA and 220μA, which means that:
For high voltage applications, it can be costly to use bulk
2.5 ≤ f • L ≤ 67 capacitance that is rated to handle the required RMS input
In practice, the above constraint does not normally affect current. Moreover, when using a simple capacitor to filter
the choice of inductor value. the AC input current, it is difficult to determine exactly
where this AC current is flowing when a power supply is
CIN Selection placed into a larger system. To avoid these issues, an LC
filter can be used on the power supply input as shown in
The input capacitance, CIN, is needed to filter the trap-
Figure 4. This keeps the higher AC currents contained in
ezoidal current at the drain of the top power MOSFET. CIN
a relatively small and inexpensive capacitor (CF) whose
should be sized to do this without causing a large variation
RMS current rating is known to be adequate. Choose an
in input voltage. In addition, the input capacitor needs
LC filter such that:
to have a very low ESR and must be rated to handle the
worst-case RMS input current of: 1 f
<
5
I 2π L F C F
IRMS = OUT(MAX )
2 where f is the switching frequency. This will attenuate the
Note that capacitor manufacturers’ ripple current ratings RMS input current by a factor of approximately 5X, greatly
are often based on only 2000 hours of life. This makes alleviating the RMS input requirements of the larger bulk
it advisable to further derate the capacitor, or to choose capacitor CBULK. The filter inductor LF should have a satu-
a capacitor rated at a higher temperature than required. ration current of at least:
Several capacitors may be paralleled to meet size or height V I
requirements in the design. Due to the high operating ISAT(LF ) ≥ 1.3 • OUT OUT(MAX )
V IN(MIN)
frequency of the LT7101, ceramic capacitors can also be
Rev. 0
Rev. 0
Rev. 0
7101 F05
800k
INTVCC
VPRG1
Figure 5. Setting the Output Voltage VPRG2
7101 F06
Rev. 0
R3 ⎛ R5 ⎞
V IN(MAX ) • ⎜ < 6V
RUN ⎝ R3 + R4 + R5 ⎟⎠
LT7101
R4
OVLO If this equation cannot be satisfied in the application, con-
OPTIONAL
R5 4.7V 7101 F08 nect a 4.7V Zener diode between the OVLO pin and ground
to clamp the OVLO pin voltage as shown in Figure 8.
OPTIONAL
Note that in applications with VOUT > 6V, additional
Figure 8. Adjustable UV and OV Lockout constraints on the use of the RUN pin also apply. See
Operating at VOUT > 6V section for more information.
The current that flows through the R3-R4-R5 divider will
directly add to the shutdown, sleep, and active current Soft-Start and LDO Regulator Timeout
of the LT7101, and care should be taken to minimize the An internal soft-start ramp of 1.2ms will limit the ramp
impact of this current on the overall efficiency of the appli- rate of the output voltage to prevent excessive input cur-
cation circuit. Resistor values in the MΩ range may be rent during start-up. If a longer ramp time is desired,
required to keep the impact on quiescent shutdown and a capacitor can be placed from the SS pin to ground.
sleep currents low. To pick resistor values, the sum total The value of the soft-start capacitor needed to provide a
of R3 + R4 + R5 (RTOTAL) should be chosen first based on desired soft-start time (tSS) can be calculated by:
the allowable DC current that can be drawn from VIN. The
individual values of R3, R4 and R5 can then be calculated CSS = tSS • 10µA
from the following equations: Note that the value of CSS must be greater than 12nF to
provide a soft-start time that is greater than the internal
1.21V
R5 = R TOTAL • default of tSS(INT) = 1.2ms.
RISING V IN OVLO THRESHOLD
The LT7101 also includes an LDO regulator timeout
1.21V feature that is essential for limiting die temperature rise
R4 = R TOTAL • – R5
RISING V IN UVLO THRESHOLD due to power dissipation in the VIN LDO. This is useful
in high VIN applications, where EXTVCC is tied to VOUT,
R3 = R TOTAL – R5 – R4
and VOUT gets shorted to ground. When this occurs, the
For applications that do not need a precise external OVLO, VIN LDO will take over the INTVCC current, resulting in
the OVLO pin should be tied directly to ground. The RUN potentially high power dissipation (>1W) in the VIN LDO
pin in this type of application can be used as an external pass device. If this condition persists, an LDO timeout
UVLO using the previous equations with R5 = 0Ω. occurs, disabling the switching of the top and bottom
MOSFETs. Once switching is disabled, the INTVCC bias
Rev. 0
60
Operating at VOUT > 6V
50
The LT7101 contains circuitry to automatically charge the
boost supply for the topside MOSFET driver by activating 40
starting up or operating near dropout (VIN ≈ VOUT) and Figure 9. Maximum Allowable Duty Cycle vs Frequency
with VOUT > 6V, however, care must be taken to avoid the for VOUT > 6V and Option 2 Configuration
accumulation of negative inductor current that can arise
from the automatic boost charging circuitry. When selecting the resistors for the RUN pin divider to
There are two optional configurations allowable for appli- limit the minimum operating VIN voltage, use the RUN pin
cations with VOUT > 6V. falling threshold minimum value of 1.06V. This ensures
that the LT7101 will not operate below the minimum oper-
Option 1: 100% Duty Cycle Allowed. Use this option when ating input voltage requirement given in Option 2 above.
operation at or near 100% duty cycle is required or if RUN Referring to Figure 8, calculate the RUN pin divider resis-
pin control is not needed. For this option, the RUN pin tors as:
must be tied to the VIN pin directly and operation at higher
1.06V
switching frequencies is prohibited. The switching fre- R4 = R TOTAL •
quency set point must be limited to a maximum value of VIN,MIN
f ≤ 550kHz R3 = R TOTAL – R4 – R5
and the inductance value must be a minimum of The rising VIN voltage at which the LT7101 will begin
L ≥ 4.5µH • (VOUT – 3) – 10µH switching is determined by the rising RUN pin threshold
of 1.21V (1.26V maximum). The typical rising VIN turn-on
Option 2: High Switching Frequency Allowed. Use this voltage is therefore:
option when either high switching frequency or RUN pin
control is needed. In this case, operation near drop-out VIN(ON,TYP) = 1.14 • VIN,MIN
is prohibited and a RUN pin divider is required to set the Note that for direct RUN pin control in all applications
minimum operating input voltage to a value of: with VOUT > 6V, an open-drain pull-down must be used in
VOUT conjunction with a RUN pin divider as shown in Figure 8.
VIN,MIN ≥
1– f • 260ns Since Option 2 allows for higher switching frequency
and smaller size inductors, this option is preferred for
Rev. 0
ing the ITH pin to the INTVCC pin. Internal compensation 7101 F10
Rev. 0
Rev. 0
VIN VIN SW
L1
VOUT
The RDS(ON) for both the top and bottom MOSFETs
CIN1 VFB can be obtained from the Typical Performance
LT7101 EXTVCC COUT Characteristics curves. Thus to obtain I2R loss:
(MASTER) INTVCC
1µF
I2R Loss = IOUT2 • (RSW + RL)
SS CLKOUT ITH 2. The internal LDO supplies the power to the INTVCC
CC RC
rail. The total power loss here is the sum of the gate
CBYP drive losses and quiescent current losses from the
control circuitry. Each time a power MOSFET gate is
SS PLLIN/MODE ICTRL L2 switched from low to high to low again, a packet of
VIN SW charge, dQ, moves from VIN to ground. The resulting
CIN2 VPRG1 EXTV
VPRG2
LT7101 CC
(SLAVE) INTVCC
dQ/dt is a current out of INTVCC that is typically much
RIND VFB 1µF larger than the DC control bias current. In continuous
RIND ITH
current mode, IGATECHG = f(QT + QB), where QT and
10pF
7101 F11
QB are the gate charges of the internal top and bot-
tom power MOSFETs and f is the switching frequency.
Figure 11. Connections for 2-Phase Operation For estimation purposes, (QT + QB) on the LT7101 is
approximately 4nC, although it varies with VIN voltage.
To calculate the total power loss from the LDO load,
Efficiency Considerations simply add the gate charge current and quiescent cur-
The percent efficiency of a switching regulator is equal to rent and multiply by voltage:
the output power divided by the input power times 100%.
⎡ ⎛ V ⎞ ⎤
It is often useful to analyze individual losses to determine PLDO = ⎢3.5mA +1nC ⎜ 4+ IN ⎟ • f ⎥ • VX
what is limiting the efficiency and which change would ⎣ ⎝ 31 ⎠ ⎦
Rev. 0
Other hidden losses such as copper trace resistances, The LT7101 requires the exposed package backplane
and internal battery resistances can account for additional metal (PGND) to be well soldered to the PC board to pro-
efficiency degradations in the overall power system. Other vide both electrical and thermal contact. This gives the
losses, including diode conduction losses during dead QFN package exceptional thermal properties, compared
time and inductor core losses, generally account for less to other packages of similar size. In many applications,
than 2% total additional loss. the LT7101 does not generate much heat due to its high
efficiency and low thermal resistance package backplane.
Fault Conditions: Short-Circuit Protection However, in applications in which the LT7101 is running at
a high ambient temperature and high input voltage or high
The architecture of the LT7101 provides inherent protec- switching frequency, the generated heat may exceed the
tion against short-circuit conditions, without the need for maximum junction temperature of the part. If the junction
folding back either the output current or the oscillator fre- temperature reaches approximately 171°C, both power
quency. A given switching cycle is skipped only as needed switches will be turned off until temperature decreases
to satisfy the high-speed average current loop, resulting by approximately 16°C.
in a brick-wall style current limit without any foldback or
hiccups in the operation down to VOUT = 0V. Note, how- Thermal analysis should always be performed by the user
ever, that hiccup restart will occur due to the LDO timeout to ensure the LT7101 does not exceed the maximum junc-
feature unless EXTVCC > 3V, or this feature is disabled by tion temperature.
tying the SS pin to INTVCC through a 75k resistor. The temperature rise is given by:
While the average current loop is extremely fast, a failsafe TRISE = PD • θJA
peak current limit (IPK) comparator has also been incor-
porated to ensure that the inductor cannot exceed a safe where PD is the power dissipated in the chip and θJA is
level, even momentarily. In practice, the peak current limit the thermal resistance from the junction of the die to the
comparator is only needed when there is an abnormal ambient environment. Consider the example in which an
voltage on the average current amplifier output filter and LT7101 is operating with IOUT = 1A, VIN = 50V, f = 500kHz,
a short-circuit is applied. In this case, the peak current VOUT = EXTVCC = 5V, and an ambient temperature of 70°C.
limit comparator may be needed for a few cycles while From the Typical Performance Characteristics section the
the average current amplifier filter settles. RDS(ON) of the top switch at this temperature is found to
be nominally 760mΩ while that of the bottom switch is
Rev. 0
VIN
VIN BOOST
36V TO 72V
2.2M LT7101 0.1µF
7101 F12
Rev. 0
VOUT
VIN COUT
CIN2
CIN1 L1
R3
GND CBST
R4
R5
CVCC
R1 R2
RFREQ
7101 F13
VIAS TO GROUND PLANE
VIAS TO OUTPUT SUPPLY (VOUT)
VIAS TO INTVCC
OUTLINE OF GROUND PLANE
VIN
VIN BOOST
5V TO 100V
4.7µF 0.1µF
100V LT7101 47µH VOUT
X7R RUN SW 5V
1A
VPRG1 VFB
OVLO EXTVCC 47µF
6.3V
VPRG2 X5R
PLLIN/MODE ITH
FREQ INTVCC
SGND PGND 1µF
fsw = 300kHz
L: WURTH 7447714470
7101 F14
Figure 15. High Efficiency 12V to 100V Input to 12V/1A Output Step-Down Regulator
VIN
VIN BOOST
4.4V TO 100V
4.7µF 0.1µF
100V LT7101 33µH VOUT
X7R RUN SW 3.3V
1A
VPRG2 VFB
OVLO EXTVCC 100µF
6.3V
VPRG1
X5R
PLLIN/MODE ITH
FREQ INTVCC
SGND PGND 1µF
fsw = 300kHz
L: WURTH 7447714330
7101 F16
Figure 16. High Efficiency 4.4V to 100V Input to 3.3V/1A Output Step-Down Regulator
BEAD BEAD
FB1 FB2
VIN
5V TO 100V VIN BOOST
4.7µF 0.22µF 4.7µF 0.1µF
0.1µF 33µH, L2 VOUT
100V 100V 100V 100V LT7101
X7R X7R X7R X7R SW 5V
1A
RUN VFB
+ C1 4.7µF
EXTVCC 47µF
10µF 100V 6.3V
125V X7R VPRG1 RIND X6S
OVLO PLLIN/MODE
VPRG2 ITH
FREQ INTVCC 8.87k
fSW = 400kHz
C1: SUNCON 125HVH10M 17.8k SGND PGND 1µF
L2: COILCRAFT XAL6060-333ME
FB1, FB2: MURATA BLM31PG121SN1
7101 F17
Rev. 0
VIN
VIN BOOST
18V TO 72V 2.2µF 0.1µF
100V LT7101 47µH VBAT
X7R RUN SW 13.5V TO 14.3V
402k 1.1A
EXTVCC
OVLO 0.1% 10µF
VFB
25V
IMON IN– X7R
VPRG1
LTC1440 100k
VPRG2 INTVCC V+ 0.1%
RIND ITH IN+ 1.74M
100k 115k 10k
FREQ PLLIN/MODE REF OUT
R1
6.49k 20k SGND PGND 1µF HYST 40.2k
115k
V– GND 0.1%
7101 TA03
Rev. 0
0.70 ±0.05
5.50 ±0.05
2.60
±0.05
4.10 ±0.05
PACKAGE
3.00 REF 3.60 OUTLINE
±0.05
0.25 ±0.05
0.50 BSC
5.10 ±0.05
6.50 ±0.05
3.60 4
±0.10
24 5
6.00 ±0.10
23 6
22
2.60
21 ±0.10
20
19 10 0.8 REF
18 11
0.75 ±0.05 0.25 ±0.05 R = 0.125
0.50 BSC TYP
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
2. DRAWING NOT TO SCALE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
3. ALL DIMENSIONS ARE IN MILLIMETERS 5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For more by
is granted information www.analog.com
implication or otherwise under any patent or patent rights of Analog Devices. 37
LT7101
TYPICAL APPLICATION
4.4V to 32V Input to 3.3V/1A Output, 2MHz Automotive Radiated EMI Performance (CISPR25) Radiated
Supply with Overvoltage Lockout and 100V Input Tolerance Emission Test with Class 5 Peak Limits
50
BEAD BEAD VERTICAL POLARIZATION
VIN FB1 FB2
4.4V TO 32V VIN BOOST
40
(100V MAX) 4.7µF 4.7µF + 0.22µF 0.1µF
100V 100V 100V 4.7µH VOUT
AMPLITUDE (dBµV/m)
LT7101
X7R X7R X7R SW 3.3V
1A 30
RUN VFB
EXTVCC 10µF
4.7µF 0.1µF 1.74M 6.3V 20
100V 100V 2MHz CLK X5R
X7R X7R OVLO PLLIN/MODE OR GND
×3 VPRG2 RIND
60.4k 10
VPRG1 ITH CLASS 5 PEAK LIMIT
64.9k LT7101
FREQ INTVCC
0
57.6k SGND PGND 0 100 200 300 400 500 600 700 800 900 1000
1µF
FREQUENCY (MHz)
14VIN TO 3.3VOUT AT 1A 7101 TA04b
7101 TA04a
fSW = 2MHz
fSW = 2MHz
OVERVOLTAGE LOCKOUT AT 36V
L: COILCRAFT XFL4020-472ME
FB1, FB2: MURATA BLM31PG601SN1
C1: SUNCON 125HVH10M
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LTC4366-2
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Rev. 0
38
04/19
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For more information www.analog.com ANALOG DEVICES, INC. 2019