36 V, 18 MHz, Low Noise, Fast Settling

Single Supply, RRO, JFET Op Amp

Data Sheet ADA4625-1/ADA4625-2
FEATURES PIN CONFIGURATION
Wide gain bandwidth product: 18 MHz typical NC 1 ADA4625-1 8 NC
High slew rate: 48 V/µs typical
–IN 2 7 V+
Low voltage noise density: 3.3 nV/√Hz typical at 1 kHz
Low peak-to-peak noise: 0.15 µV p-p, 0.1 Hz to 10 Hz +IN 3 6 OUT
TOP VIEW
Low input bias current: ±15 pA typical at TA = 25°C V– 4 (Not to Scale) 5 NC
Low offset voltage: ±80 µV maximum at TA = 25°C NOTES
Offset voltage drift: ±1.2 µV/°C maximum at TA = −40°C to 85°C 1. NC = NO CONNECTION. DO NOT CONNECT TO THIS PIN.

15893-001
2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND,
Fast settling: 0.01% in 700 ns typical V+ OR V– PLANE, OR LEAVE IT FLOATING.

Wide range of operating voltages Figure 1.

Dual-supply operation: ±2.5 V to ±18 V The ADA4625-1/ADA4625-2 are unity-gain stable, and there is
Single-supply operation: 5 V to 36 V
no phase reversal when input range exceeds either supply rail by
Input voltage range includes V−
200 mV. The output is capable of driving loads up to 1000 pF
Rail-to-rail output
and/or 600 Ω loads.
High capacitive load drive capability
Output short-circuit current: ±46 mA The ADA4625-1/ADA4625-2 are specified for operation over
No phase reversal the extended industrial temperature range of −40°C to +125°C
Unity-gain stable and operates from +5 V to +36 V (±2.5 V to ±18 V) with specifi-
cations at +5 V and ±18 V. The devices are available in an 8-lead
APPLICATIONS SOIC package with an exposed pad (EPAD).
PLL filter amplifiers 100
VSY = 5V
Transimpedance amplifiers VSY = ±18V
Photodiode sensor interfaces
VOLTAGE NOISE DENSITY (nV/√Hz)

Low noise charge amplifiers

GENERAL DESCRIPTION
The ADA4625-1/ADA4625-2 build on Analog Devices, Inc., 10
high voltage, single-supply, rail-to-rail output (RRO), precision
junction field effect transistor (JFET) input op amps, taking that
product type to a level of speed and low noise that has not been
made available to the market previously.
The ADA4625-1/ADA4625-2 provide optimal performance in
1
high voltage, high gain, and low noise applications. The input

15893-157
1 10 100 1k 10k 100k
common-mode voltage range includes the negative supply, and FREQUENCY (Hz)
the output swings rail to rail. This enables the user to maximize Figure 2. Voltage Noise Density vs. Frequency
dynamic input range in low voltage, single supply applications
without the need for a separate negative voltage power supply Table 1. Related Precision JFET Operational Amplifiers
for ground sense. Single Dual Quad
Not applicable AD823A Not applicable
The combination of wide bandwidth, low noise, and low input
AD8510 AD8512 AD8513
bias current makes the ADA4625-1/ADA4625-2 especially
suitable for phase-locked loop (PLL), active filter amplifiers and AD8610 AD8620 Not applicable
for high tuning voltage (VTUNE), voltage controlled oscillators ADA4610-1 ADA4610-2 ADA4610-4
(VCOs) and preamplifiers where low level signals require an ADA4622-1 ADA4622-2 ADA4622-4
amplifier that provides both high amplification and wide ADA4627-1/ADA4637-1 Not applicable Not applicable
bandwidth.

Rev. A Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2017–2019 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
ADA4625-1/ADA4625-2
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Pin Configuration ............................................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—±18 V Operation ........................... 3
Electrical Characteristics—5 V Operation................................ 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 23
Input and Gain Stages ................................................................ 23
REVISION HISTORY
6/2019—Rev. 0 to Rev. A
Added ADA4625-2 ........................................................ Throughout
Changes to Table 2 ............................................................................ 3
Changes to Table 3 ............................................................................ 5
Added Figure 4 and Table 7; Renumbered Sequentially ............. 8
Changes to Table 6 ............................................................................ 8
Added Figure 16.............................................................................. 10
Added Figure 25 and Figure 28..................................................... 12
Added Figure 17, Figure 38, and Figure 40 ................................. 14
Added Figure 61 and Figure 64..................................................... 18
Added Figure 65 to Figure 70........................................................ 19
Added Figure 73 and Figure 76..................................................... 20
Rev. A | Page 2 of 35
Data Sheet
Output Stage................................................................................ 23
No Phase Inversion .................................................................... 24
Supply Current............................................................................ 24
Applications Information .............................................................. 25
Active Loop Filter for Phase-Locked Loops (PLLs) .............. 25
ADA4625-1 Advantages and Design Example ....................... 26
Transimpedance Amplifier ....................................................... 27
DAC Output Driver ................................................................... 31
Recommended Power Solution ................................................ 32
Input Overvoltage Protection ................................................... 32
Driving Capacitive Loads .......................................................... 32
Thermal Management ............................................................... 32
Typical Applications ................................................................... 33
Outline Dimensions ....................................................................... 35
Ordering Guide .......................................................................... 35
Added Figure 77 and Figure 80 .................................................... 21
Added Figure 84 ............................................................................. 22
Added DAC Output Driver Section, Figure 105, Figure 106, and
Figure 107 ........................................................................................ 31
Added Typical Applications Section, Figure 109, and
Figure 110 ......................................................................................... 33
Added Figure 111 and Figure 112 ................................................ 34
Updated Outline Dimensions ....................................................... 35
Changes to Ordering Guide .......................................................... 35
10/2017—Revision 0: Initial Version
Data Sheet ADA4625-1/ADA4625-2

SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—±18 V OPERATION
Supply voltage (VSY) = ±18 V, common-mode voltage (VCM) = output voltage (VOUT) = 0 V, TA = 25°C, unless otherwise noted.

Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS ADA4625-1 ±15 ±80 µV
ADA4625-2 ±100 µV
−40°C < TA < +125°C ±250 µV
Offset Voltage Drift TCVOS −40°C < TA < +85°C ±0.2 ±1.2 µV/°C
−40°C < TA < +125°C ±0.5 ±2.1 µV/°C
Input Bias Current IB ±15 ±75 pA
ADA4625-1, −40°C < TA < +125°C ±5.5 nA
ADA4625-2, −40°C < TA < +125°C ±7 nA
Input Offset Current IOS ±2 ±50 pA
ADA4625-1, −40°C < TA < +125°C ±0.4 nA
ADA4625-2, −40°C < TA < +125°C ±0.7 nA
Input Voltage Range IVR −18.2 +14.5 V
Common-Mode Rejection Ratio CMRR VCM = −18.2 V to +14.5 V 97 115 dB
−40°C < TA < +125°C 94 dB
VCM = −18.2 V to +12 V 115 130 dB
−40°C < TA < +125°C 110 dB
Large Signal Voltage Gain AVO Load resistance (RL) = 2 kΩ, VOUT = −17.5 V to 140 150 dB
+17.5 V
−40°C < TA < +125°C 135 dB
RL = 600 Ω, VOUT = −15 V to +15 V 130 135 dB
ADA4625-1, −40°C < TA < +125°C 115 dB
ADA4625-2, −40°C < TA < +125°C 100 dB
Input Capacitance
Differential Mode CDM ADA4625-1 8.6 pF
ADA4625-2 13.8 pF
Common Mode CCM ADA4625-1 11.3 pF
ADA4625-2 13.3 pF
Input Resistance RDM Differential mode 1012 Ω
RCM Common mode, VCM from −18 V to +12 V 1012 Ω
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 2 kΩ 17.65 17.72 V
−40°C < TA < +125°C 17.5 V
RL = 600 Ω 17.0 17.28 V
−40°C < TA < +125°C 16.75 V
Output Voltage Low VOL RL = 2 kΩ −17.74 −17.70 V
−40°C < TA < +125°C −17.5 V
RL = 600 Ω −17.4 −17.0 V
−40°C < TA < +125°C −16.85 V
Output Current IOUT Dropout voltage (VDROPOUT) < 1 V ±33 mA
Short-Circuit Current ISC ±46 mA
Closed-Loop Output Impedance ZOUT f = 1 MHz, closed-loop gain (AV) = +1 2 Ω
AV = +10 18 Ω
AV = +100 29 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = ±5 V to ±18 V 105 120 dB
−40°C < TA < +125°C 102 dB
Supply Current per Amplifier ISY VOUT = 0 V 4.0 4.5 mA
−40°C < TA < +125°C 5 mA

Rev. A | Page 3 of 35
ADA4625-1/ADA4625-2 Data Sheet
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
Slew Rate SR VOUT = ±10 V, RL = 2 kΩ, AV = −1 48 V/µs
VOUT = ±10 V, RL = 2 kΩ, AV = −5 44 V/µs
Gain Bandwidth Product GBP AV = 100 18 MHz
Unity-Gain Crossover UGC AV = 1 12.4 MHz
−3 dB Bandwidth −3 dB AV = 1 16 MHz
Phase Margin ΦΜ ADA4625-1 88 Degrees
ADA4625-2 75 Degrees
Channel Separation CS VIN = 15 V p-p, f = 1 kHz, RL = 2 kΩ, AV = 100 108 dB
VIN = 15 V p-p, f = 10 kHz, RL = 2 kΩ, AV = 100 88 dB
Settling Time tS
ADA4625-1 To 0.1%, input voltage (VIN) = 10 V step, RL = 500 ns
2 kΩ, load capacitance (CL) = 15 pF, AV = −1
To 0.01%, VIN = 10 V step, RL = 2 kΩ, CL = 15 pF, 700 ns
AV = −1
ADA4625-2 To 0.1%, VIN = 10 V step, RL = 2 kΩ, CL = 15 pF, 700 ns
AV = −1
To 0.01%, VIN = 10 V step, RL = 2 kΩ, 1200 ns
CL = 15 pF, AV = −1
ELECTROMAGNETIC INTERFERENCE (EMI) EMIRR
REJECTION RATIO
f = 1000 MHz ADA4625-1/ADA4625-2 56 dB
f = 2400 MHz ADA4625-1 93 dB
ADA4625-2 73 dB
NOISE PERFORMANCE
Peak-to-Peak Noise eN p-p 0.1 Hz to 10 Hz 0.15 µV p-p
Voltage Noise Density eN f = 10 Hz 5.5 nV/√Hz
f = 100 Hz 3.6 nV/√Hz
f = 1 kHz 3.3 nV/√Hz
Current Noise Density iN f = 1 kHz 4.5 fA/√Hz
Total Harmonic Distortion + Noise THD + N AV = 1, f = 10 Hz to 20 kHz, RL = 2 kΩ,
VIN = 6 VRMS at 1 kHz
Bandwidth = 80 kHz 0.0003 %
−109 dB
Bandwidth = 500 kHz 0.0007 %
−103 dB

Rev. A | Page 4 of 35
Data Sheet ADA4625-1/ADA4625-2
ELECTRICAL CHARACTERISTICS—5 V OPERATION
VSY = 5 V, VCM = 1.5 V, VOUT = VSY/2, TA = 25°C, unless otherwise noted.

Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS ±0.1 ±0.6 mV
−40°C < TA < +125°C ±1.0 mV
Offset Voltage Drift TCVOS ADA4625-1, −40°C < TA < +85°C ±0.4 ±2.6 µV/°C
ADA4625-2, −40°C < TA < +85°C ±4.5 µV/°C
ADA4625-1, −40°C < TA < +125°C ±0.7 ±3.6 µV/°C
ADA4625-2, −40°C < TA < +125°C ±4.5 µV/°C
Input Bias Current IB ±15 ±50 pA
ADA4625-1, −40°C < TA < +125°C ±3.5 nA
ADA4625-2, −40°C < TA < +125°C ±4 nA
Input Offset Current IOS ±2 ±50 pA
−40°C < TA < +125°C ±150 pA
Input Voltage Range IVR −0.2 +1.5 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 1.5 V 74 90 dB
−40°C < TA < +125°C 70 dB
Large Signal Voltage Gain AVO RL = 2 kΩ to V−, VOUT = 0.35 V to 4.65 V 130 145 dB
−40°C < TA < +125°C 120 dB
RL = 600 Ω to V−, VOUT = 0.5 V to 4.5 V 120 130 dB
−40°C < TA < +125°C 110 dB
Input Capacitance
Differential Mode CDM ADA4625-1 12.1 pF
ADA4625-2 12.7 pF
Common Mode CCM ADA4625-1 16.3 pF
ADA4625-2 18.4 pF
Input Resistance RDM Differential mode 1012 Ω
RCM Common mode, VCM from 0 V to 1.5 V 1012 Ω
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 2 kΩ to V− 4.75 4.82 V
−40°C < TA < +125°C 4.7 V
RL = 600 Ω to V− 4.65 4.74 V
−40°C < TA < +125°C 4.55 V
Output Voltage Low VOL RL = 2 kΩ to V+ 0.17 0.22 V
−40°C < TA < +125°C 0.3 V
RL = 600 Ω to V+ 0.25 0.3 V
−40°C < TA < +125°C 0.45 V
Output Current IOUT VDROPOUT < 1 V ±33 mA
Short-Circuit Current ISC ±46 mA
Closed-Loop Output Impedance ZOUT f = 1 MHz, AV = +1 2 Ω
AV = +10 18 Ω
AV = +100 29 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = 4.5 V to 10 V 80 97 dB
−40°C < TA < +125°C 75 dB
Supply Current per Amplifier ISY VOUT = 0 V 3.9 4.3 mA
−40°C < TA < +125°C 4.8 mA

Rev. A | Page 5 of 35
ADA4625-1/ADA4625-2 Data Sheet
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
Slew Rate SR VOUT = 0.5 V to 4.5 V, RL = 2 kΩ, AV = −1 32 V/μs
VOUT = 0.5 V to 4.5 V, RL = 2 kΩ, AV = −5 27 V/μs
Gain Bandwidth Product GBP AV = 100 16 MHz
Unity-Gain Crossover UGC AV = 1 11.2 MHz
−3 dB Bandwidth −3 dB AV = 1 16 MHz
Phase Margin ΦM ADA4625-1 86 Degrees
ADA4625-2 71 Degrees
Channel Separation CS VIN = 15 V p-p, f = 1 kHz, RL = 2 kΩ, AV = 100 108 dB
VIN = 15 V p-p, f = 100 kHz, RL = 2 kΩ, AV = 100 88 dB
Settling Time tS
ADA4625-1 To 0.1%, VIN = 4 V step, RL = 2 kΩ, CL = 15 pF, AV = −1 600 ns
To 0.01%, VIN = 4 V step, RL = 2 kΩ, CL = 15 pF, 950 ns
AV = −1
ADA4625-2 To 0.1%, VIN = 4 V step, RL = 2 kΩ, CL = 15 pF, AV = −1 1250 ns
To 0.01%, VIN = 4 V step, RL = 2 kΩ, CL = 15 pF, 1350 ns
AV = −1
EMI REJECTION RATIO EMIRR
f = 1000 MHz ADA4625-1/ADA4625-2 56 dB
f = 2400 MHz ADA4625-1 87 dB
ADA4625-2 79 dB
NOISE PERFORMANCE
Peak-to-Peak Noise eN p-p 0.1 Hz to 10 Hz 0.15 μV p-p
Voltage Noise Density eN f = 10 Hz 5.5 nV/√Hz
f = 100 Hz 3.6 nV/√Hz
f = 1 kHz 3.3 nV/√Hz
Current Noise Density iN f = 1 kHz 4.5 fA/√Hz
Total Harmonic Distortion + Noise THD + N AV = 1, f = 10 Hz to 20 kHz, RL = 2 kΩ,
VIN = 0.6 VRMS at 1 kHz
Bandwidth = 80 kHz ADA4625-1 0.0003 %
−109 dB
ADA4625-2 0.002 %
−93 dB
Bandwidth = 500 kHz ADA4625-1 0.0007 %
−103 dB
ADA4625-2 0.004 %
−89 dB

Rev. A | Page 6 of 35
Data Sheet ADA4625-1/ADA4625-2

ABSOLUTE MAXIMUM RATINGS

Table 4. THERMAL RESISTANCE
Parameter Rating Thermal performance is directly linked to printed circuit board
Supply Voltage 40 V (PCB) design and operating environment. Close attention to PCB
Input Voltage (V−) − 0.2 V to thermal design is required.
(V+ ) + 0.2 V
Differential Input Voltage (V−) − 0.2 V to Table 5. Thermal Resistance
(V+) + 0.2 V Package Type1, 2 θJA3 θJC Unit
1
Input Current ±20 mA RD-8-1 52.8 5.7 °C/W
Storage Temperature Range −65°C to +150°C 1
Values were obtained per JEDEC standard JESD-51.
Operating Temperature Range −40°C to +125°C 2
Although the exposed pad can be left floating, it must be connected to the
Junction Temperature Range −65°C to +150°C GND, or the V+ or V− plane for proper thermal management.
3
Board layout impacts thermal characteristics such as θJA. When proper thermal
Lead Temperature, Soldering (10 sec) 300°C management techniques are used, a better θJA can be achieved. Refer to the
Electrostatic Discharge (ESD) Thermal Management section for additional information.
Human Body Model (HBM)2
ADA4625-1 1.25 kV
ADA4625-2 1.5 kV ESD CAUTION
Field Induced Charge Device Model (FICDM)3
ADA4625-1 1.25 kV
ADA4625-2 1.25 kV
1
The input pins have clamp diodes connected to the power supply pins. Limit
the input current to 20 mA or less whenever input signals exceed the power
supply rail by 0.3 V.
2
ESDA/JEDEC JS-001-2011 applicable standard.
3
JESD22-C101 (ESD FICDM standard of JEDEC) applicable standard.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. A | Page 7 of 35
ADA4625-1/ADA4625-2 Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

NC 1 ADA4625-1 8 NC

–IN 2 7 V+

+IN 3 6 OUT
TOP VIEW
V– 4 (Not to Scale) 5 NC

NOTES
1. NC = NO CONNECTION. DO NOT CONNECT TO THIS PIN.

15893-002
2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND,
V+ OR V– PLANE, OR LEAVE IT FLOATING.

Figure 3. ADA4625-1 Pin Configuration

Table 6. Pin Function Descriptions, ADA4625-1

Pin No. Mnemonic Description
1, 5, 8 NC No Connection. Do not connect to these pins.
2 −IN Inverting Input Pin.
3 +IN Noninverting Input Pin.
4 V− Negative Supply Voltage Pin.
6 OUT Output Pin.
7 V+ Positive Supply Voltage Pin.
EPAD Exposed Pad. Connect the exposed pad to GND, V+ or V− plane, or leave it floating.

OUT A 1 ADA4625-2 8 V+

–IN A 2 7 OUT B

+IN A 3 6 –IN B
TOP VIEW
V– 4 (Not to Scale) 5 +IN B

NOTES
15893-101

1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND,

V+ OR V– PLANE, OR LEAVE IT FLOATING.

Figure 4. ADA4625-2 Pin Configuration

Table 7. Pin Function Descriptions, ADA4625-2

Pin No. Mnemonic Description
1 OUT A Output Pin for Channel A.
2 −IN A Inverting Input Pin for Channel A.
3 +IN A Noninverting Input Pin for Channel A.
4 V− Negative Supply Voltage Pin.
5 +IN B Noninverting Input Pin for Channel B.
6 −IN B Inverting Input Pin for Channel B.
7 OUT B Output Pin for Channel B.
8 V+ Positive Supply Voltage Pin.
EPAD Exposed Pad. Connect the exposed pad to GND, V+ or V− plane, or leave it floating.

Rev. A | Page 8 of 35
Data Sheet ADA4625-1/ADA4625-2

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VCM = 0 V, unless otherwise noted.
50 25
VSY = ±18V VSY = 5V
RL = ∞ VCM = 1.5V
RL = ∞
40 20
NUMBER OF AMPLIFIERS

NUMBER OF AMPLIFIERS
30 15

20 10

10 5

0 0

15893-003

15893-006
–100 –75 –50 –25 0 25 50 75 100 –400 –300 –200 –100 0 100 200 300 400
VOS (µV) VOS (µV)

Figure 5. Input Offset Voltage (VOS) Distribution, Supply Voltage (VSY) = ±18 V Figure 8. VOS Distribution, VSY = 5 V

70 45
VSY = ±18V VSY = 5V
VCM = 1.5V
40
60
35
NUMBER OF AMPLIFIERS

NUMBER OF AMPLIFIERS

50
30

40 25

30 20

15
20
10
10
5

0 0
15893-004

15893-007
–2.0 –1.5 –1.0 –0.5 0.0 0.5 1.0 1.5 2.0 –2.0 –1.5 –1.0 –0.5 0.0 0.5 1.0 1.5 2.0
TCVOS (µV/°C) TCVOS (µV/°C)

Figure 6. Input Offset Voltage Drift (TCVOS) Distribution (−40°C to +125°C ), Figure 9. TCVOS Distribution (−40°C to +125°C ), VSY = 5 V
VSY = ±18 V

1000
600 VSY = 5V
VSY = ±18V 800 90 AMPLIFIERS
90 AMPLIFIERS
600
400
400

200 200
VOS (µV)

0
VOS (µV)

0
–200

–400
–200
–600

–400 –800

–1000
15893-008

–600 –0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4
15893-005

–18.2 –13.2 –8.2 –3.2 1.8 6.8 11.8 16.8 VCM (V)
VCM (V)
Figure 10. VOS vs. VCM, VSY = 5 V
Figure 7. VOS vs. Common-Mode Voltage (VCM), VSY = ±18 V

Rev. A | Page 9 of 35
ADA4625-1/ADA4625-2 Data Sheet
120 120
VSY = ±18V VSY = 5V
RL = ∞ VCM = 1.5V
RL = ∞
100 100

NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS

80 80

60 60

40 40

20 20

0 0

15893-013
15893-010
–60 –50 –40 –30 –20 –10 0 10 –60 –50 –40 –30 –20 –10 0 10
IB (pA) IB (pA)

Figure 11. Input Bias Current (IB) Distribution, VSY = ±18 V Figure 14. IB Distribution, VSY = 5 V

90 90
VSY = ±18V VSY = 5V
RL = ∞ 80 VCM = 1.5V
80 RL = ∞

70 70

NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS

60 60

50 50

40 40

30 30

20 20

10 10

0
0

15893-014
–40 –30 –20 –10 0 10 20 30 40
15893-011

–40 –30 –20 –10 0 10 20 30 40

IOS (pA)
IOS (pA)

Figure 12. Input Offset Current (IOS) Distribution, VSY = ±18 V Figure 15. IOS Distribution, VSY = 5 V

200 500

0 0

–200 –500

–400 –1000

–600 –1500
IB (pA)
IB (pA)

–800 –2000

–1000 –2500

–1200 –3000

–1400 VSY = 5V, VCM = 1.5V –3500 VSY = 5V, VCM = 1.5V
VSY = ±18V VSY = ±18V
–1600 –4000
15893-102
15893-012

–40 –25 –10 5 20 35 50 65 80 95 110 125 –40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 13. ADA4625-1 IB vs. Temperature Figure 16. ADA4625-2 IB vs. Temperature

Rev. A | Page 10 of 35
Data Sheet ADA4625-1/ADA4625-2
100 300
VSY = ±18V VSY = 5V
80 250
200
60
150
40
100
20 50
IB (pA)

IB (pA)
0 0

–20 –50
–100
–40
–150
–60
–200
–80 –250
–100 –300

15893-015

15893-018
–18.2 –14.2 –10.2 –6.2 –2.2 1.8 5.8 9.8 13.8 17.8 –0.2 0.3 0.8 1.3 1.8 2.3 2.8 3.3 3.8
VCM (V) VCM (V)

Figure 17. IB vs. VCM, VSY = ±18 V Figure 20. IB vs. VCM, VSY = 5 V

10n 10n

TA = 125°C
TA = 125°C
ABSOLUTE VALUE OF IB (A)

ABSOLUTE VALUE OF IB (A)

1n 1n

TA = 85°C
TA = 85°C

100p 100p

10p 10p

TA = 25°C TA = 25°C

1p 1p
15893-016

15893-019
–18.2 –14.2 –10.2 –6.2 –2.2 1.8 5.8 9.8 13.8 17.8 –0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0
VCM (V) VCM (V)

Figure 18. Absolute Value of IB vs. VCM for Various Temperatures, VSY = ±18 V Figure 21. Absolute Value of IB vs. VCM for Various Temperature, VSY = 5 V

100 10
VSY = ±18V VSY = 5V
VCM = 1.5V

10
(V+) – VOUT (V)

(V+) – VOUT (V)

1
+125°C TA = +125°C
+85°C TA = +85°C
+25°C TA = +25°C
–40°C TA = –40°C

0.1 0.1
15893-017

15893-020

0.001 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100

IOUT SOURCE (mA) IOUT SOURCE (mA)

Figure 19. Dropout Voltage ((V+) − VOUT) vs. Output Current (IOUT) Source Figure 22. ((V+) − VOUT) vs. IOUT Source for Various Temperatures, VSY = 5 V
for Various Temperatures, VSY = ±18 V

Rev. A | Page 11 of 35
ADA4625-1/ADA4625-2 Data Sheet
100 10
VSY = ±18V VSY = 5V
VCM = 1.5V

10

VOUT – (V–) (V)

VOUT – (V–) (V)

1
TA = +125°C TA = +125°C
TA = +85°C TA = +85°C
TA = +25°C TA = +25°C
TA = –40°C TA = –40°C

0.1 0.1

15893-021

15893-024
0.001 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100
IOUT SINK (mA) IOUT SINK (mA)

Figure 23. Dropout Voltage (VOUT − (V−)) vs. IOUT Sink for Various Figure 26. (VOUT − (V−)) vs. IOUT Sink for Various Temperatures, VSY = 5 V
Temperatures, VSY = ±18 V

120 270 120 270

VSY = 5V
100 225 100 RL = 1kΩ 225
CL = 300pF
CL = 100pF
80 180 80 CL = 0pF 180

PHASE (Degrees)
PHASE (Degrees)

60 135 60 135
GAIN (dB)
GAIN (dB)

40 90 40 90

20 45 20 45

0 0 0 0
VSY = ±18V
RL = 1kΩ
–20 CL = 300pF –45 –20 –45
CL = 100pF
CL = 0pF
–40 –90 –40 –90

15893-025
15893-022

100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 24. ADA4625-1 Open-Loop Gain and Phase vs. Frequency, VSY = ±18 V Figure 27. ADA4625-1 Open-Loop Gain and Phase vs. Frequency, VSY = 5 V

120 270 120 270

100 225 100 225

80 180 80 180

PHASE (Degrees)
PHASE (Degrees)

60 135 60 135
GAIN (dB)
GAIN (dB)

40 90 40 90

20 45 20 45

0 0 0 0
VSY = ±18V VSY = 5V
RL = 1kΩ RL = 1kΩ
–20 CL = 300pF –45 –20 CL = 300pF –45
CL = 100pF CL = 100pF
CL = 0pF CL = 0pF
–40 –90 –40 –90
15893-104
15893-103

100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 25. ADA4625-2 Open-Loop Gain and Phase vs. Frequency, VSY = ±18 V Figure 28. ADA4625-2 Open-Loop Gain and Phase vs. Frequency, VSY = 5 V

Rev. A | Page 12 of 35
Data Sheet ADA4625-1/ADA4625-2
60 60
VSY = ±18V VSY = 5V

50 50
AV = 100 AV = 100
40 40

30 30
GAIN (dB)

GAIN (dB)
AV = 10 AV = 10
20 20

10 10
AV = 1 AV = 1
0 0

–10 –10

–20 –20

15893-023

15893-026
10 100 1k 10k 100k 1M 10M 100M 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 29. Gain vs. Frequency for Various Closed-Loop Gains, VSY = ±18 V Figure 32. Gain vs. Frequency for Various Closed-Loop Gains, VSY = 5 V

1000 1000
VSY = ±18V VSY = 5V

100 100
OUTPUT IMPEDANCE (Ω)

OUTPUT IMPEDANCE (Ω)

10 10
AV = 100 AV = 10 AV = 1
AV = 100 AV = 1
1 1 AV = 10

0.1 0.1

0.01 0.01

0.001 0.001
15893-027

15893-030
100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 30. Output Impedance (ZOUT) vs. Frequency, VSY = ±18 V Figure 33. ZOUT vs. Frequency, VSY = 5 V

100 100
VSY = ±18V VSY = 5V
VCM = 1.5V
–PSRR
80 +PSRR 80 –PSRR
+PSRR

60 60
PSRR (dB)

PSRR (dB)

40 40

20 20

0 0

–20 –20
15893-028

15893-031

10 100 1k 10k 100k 1M 10M 100M 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 31. Power Supply Rejection Ration (PSRR) vs. Frequency, VSY = ±18 V Figure 34. PSRR vs. Frequency, VSY = 5 V

Rev. A | Page 13 of 35
ADA4625-1/ADA4625-2 Data Sheet
140 140
VSY = 5V VSY = 5V
VSY = ±18V VSY = ±18V
120 120

100 100
EMIRR (dB)

EMIRR (dB)
80 80

60 60

40 40

20 20

15893-029

15893-105
10M 100M 1G 10G 10M 100M 1G 10G
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 35. ADA4625-1 EMI Rejection Ratio (EMIRR) vs. Frequency Figure 38. ADA4625-2 EMIRR vs. Frequency

45 40
VSY = ±18V VSY = 5V
40 RL = 2kΩ 35 VCM = 1.5V
VIN = 100mV p-p RL = 2kΩ
VIN = 100mV p-p
35
30
AV = +1
OS+ OS+
30 OS– AV = +1 OS–
OVERSHOOT (%)

OVERSHOOT (%)
25
25
20
20
AV = –1
15
15
10
10 AV = –1

5 5

0 0
15893-034

15893-037
1 10 100 1k 1 10 100 1k
LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF)

Figure 36. ADA4625-1 Small Signal Overshoot (OS±) vs. Load Capacitance, Figure 39. ADA4625-1 OS± vs. Load Capacitance, VSY = 5 V
VSY = ±18 V
45 45
VSY = ±18V VSY = 5V
40 RL = 2kΩ 40 RL = 2kΩ
VIN = 100mV p-p VIN = 100mV p-p
35 35
OS+ OS+
30 OS– AV = +1 30 OS– AV = +1
OVERSHOOT (%)

OVERSHOOT (%)

25 25

20 20

15 15

10 AV = –1 10 AV = –1

5 5

0 0
15893-106

15893-107

1 10 100 1k 1 10 100 1k
LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF)

Figure 37. ADA4625-2 OS± vs. Load Capacitance, VSY = ±18 V Figure 40. ADA4625-2 OS± vs. Load Capacitance, VSY = 5 V

Rev. A | Page 14 of 35
Data Sheet ADA4625-1/ADA4625-2
140 120
VSY = 5V
110 VSY = ±18V
130
100
120 90
80
110
70
CMRR (dB)

CMRR (dB)
100 60
50
90
40
80 30

VSY = ±18V, VCM = –18.2V TO +14.5V 20

70 VSY = ±18V, VCM = –18.2V TO +12.0V
10
VSY = 5V, VCM = 0V TO 1.5V
60 0

15893-036

15893-033
–40 –25 –10 5 20 35 50 65 80 95 110 125 10 100 1k 10k 100k 1M 10M 100M
TEMPERATURE (°C) FREQUENCY (Hz)

Figure 41. CMRR vs. Temperature Figure 44. CMRR vs. Frequency

20 4
VSY = 5V
VSY = ±18V RL = 2kΩ
15 RL = 2kΩ CL = 100pF
CL = 100pF 3
10

OUTPUT VOLTAGE (V)

2
5
VOLTAGE (V)

0 1

–5
0
–10

–1
–15

–20 –2
15893-035

15893-038
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
TIME (µs) TIME (µs)

Figure 42. Large Signal Transient Response, AV = +1, VSY = ±18 V Figure 45. Large Signal Transient Response, AV = +1, VSY = 5 V

20 5
VSY = ±18V VSY = 5V
15 RL = 2kΩ VCM = 1.5V
CL = 100pF RL = 2kΩ
4
CL = 100pF
10
OUTPUT VOLTAGE (V)

3
5
VOLTAGE (V)

0 2

–5
1
–10

0
–15

–20 –1
15893-039

15893-042

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
TIME (µs) TIME (µs)

Figure 43. Large Signal Transient Response, AV = −1, VSY = ±18 V Figure 46. Large Signal Transient Response, AV = −1, VSY = 5 V

Rev. A | Page 15 of 35
ADA4625-1/ADA4625-2 Data Sheet
0.10 1.60
VSY = ±18V VSY = 5V
RL = 2kΩ VCM = 1.5V
CL = 100pF RL = 2kΩ
VIN = 0.1V p-p CL = 100pF
0.05 1.55 VIN = 0.1V p-p

VOLTAGE (V)
VOLTAGE (V)

0 1.50

–0.05 1.45

–0.10 1.40

15893-043
15893-040
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
TIME (µs) TIME (µs)

Figure 47. Small Signal Transient Response, AV = 1, VSY = ±18 V Figure 50. Small Signal Transient Response, AV = 1, VSY = 5 V

0.10 1.60
VSY = ±18V VSY = 5V
RL = 2kΩ VCM = 1.5V
CL = 100pF RL = 2kΩ
VIN = 0.1V p-p CL = 100pF
0.05 1.55 VIN = 0.1V p-p
VOLTAGE (V)

VOLTAGE (V)

0 1.50

–0.05 1.45

–0.10 1.40
15893-041

15893-044
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
TIME (µs) TIME (µs)

Figure 48. Small Signal Transient Response, AV = −1, VSY = ±18 V Figure 51. Small Signal Transient Response, AV = −1, VSY = 5 V

10 20 1.0 2.5

5 15 0.5 2.0

0 10 0 1.5

OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

INPUT VOLTAGE (V)

INPUT VOLTAGE (V)

VIN (V+) = 3.5V, (V–) = –1.5V

–5 5 –0.5 VOUT VCM = 0V 1.0
VIN = 0.75V p-p
–10 0 –1.0 0.5

VSY = ±18V
–15 VIN = 5.4V p-p –5 –1.5 0

–20 VIN –10 –2.0 –0.5

VOUT
–25 –15 –2.5 –1.0

–30 –20 –3.0 –1.5

15893-048
15893-045

TIME (200ns/DIV) TIME (200ns/DIV)

Figure 49. Negative Overload Recovery, AV = −10, VSY = ±18 V Figure 52. Negative Overload Recovery, AV = −10, VSY = 5 V

Rev. A | Page 16 of 35
Data Sheet ADA4625-1/ADA4625-2
5 35 0.5 14

0 30 0 12

–5 VSY = ±18V 25 –0.5 10

VIN = 5.4V p-p

OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

INPUT VOLTAGE (V)

INPUT VOLTAGE (V)

VIN (V+) = 3.5V, (V–) = –1.5V
–10 20 –1.0 VOUT VCM = 0V 8
VIN = 0.75V p-p
VIN
–15 VOUT 15 –1.5 6

–20 10 –2.0 4

–25 5 –2.5 2

–30 0 –3.0 0

–35 –5 –3.5 –2

15893-046

15893-049
TIME (200ns/DIV) TIME (200ns/DIV)

Figure 53. Positive Overload Recovery, AV = −10, VSY = ±18 V Figure 56. Positive Overload Recovery, AV = −10, VSY = 5 V

10 5
VSY = ±18V VSY = 5V
5 RL = 2kΩ 3 VCM = 1.5V
CL = 100pF RL = 2kΩ
INPUT INPUT CL = 100pF
DUT AV = –1
0 1 DUT AV = –1
INPUT VOLTAGE (V)

INPUT VOLTAGE (V)

–5 –1

–10 –3
ERROR BAND ERROR BAND
POST GAIN = 20 POST GAIN = 20
–15 +100mV –5 +40mV
OUTPUT OUTPUT
–20 0V –7 0

–25 –100mV –9 –40mV

15893-047

15893-050
–30 –11
TIME (400ns/DIV) TIME (400ns/DIV)

Figure 54. ADA4625-1 Negative Settling Time to 0.1%, VSY = ±18 V Figure 57. ADA4625-1 Negative Settling Time to 0.1%, VSY = 5 V

10 4
INPUT VSY = ±18V VSY = 5V
5 RL = 2kΩ 2 VCM = 1.5V
CL = 100pF RL = 2kΩ
DUT AV = –1 CL = 100pF
0 0 DUT AV = –1
INPUT VOLTAGE (V)

INPUT VOLTAGE (V)

–5 –2
INPUT

–10 –4
ERROR BAND ERROR BAND
POST GAIN = 20 POST GAIN = 20
–15 –6 OUTPUT
+10mV
OUTPUT +4mV
–20 0V –8 0
–10mV –4mV
–25 –10
15893-051

15893-054

–30 –12
TIME (400ns/DIV) TIME (400ns/DIV)

Figure 55. ADA4625-1 Negative Settling Time to 0.01%, VSY = ±18 V Figure 58. AD4625-1 Negative Settling Time to 0.01%, VSY = 5 V

Rev. A | Page 17 of 35
ADA4625-1/ADA4625-2 Data Sheet
10 5

5 3 INPUT
INPUT VSY = ±18V
RL = 2kΩ
0 CL = 100pF 1 VSY = 5V
VCM = 1.5V
DUT AV = –1

INPUT VOLTAGE (V)

INPUT VOLTAGE (V)

RL = 2kΩ
–5 –1 CL = 100pF
DUT AV = –1
–10 –3
ERROR BAND ERROR BAND
POST GAIN = 20 POST GAIN = 20
–15 +100mV –5 +40mV
OUTPUT OUTPUT
–20 0V –7 0

–25 –100mV –9 –40mV

15893-052

15893-055
–30 –11
TIME (400ns/DIV) TIME (400ns/DIV)

Figure 59. ADA4625-1 Positive Settling Time to 0.1%, VSY = ±18 V Figure 62. ADA4625-1 Positive Settling Time to 0.1%, VSY = 5 V

10 4
INPUT
5 2
VSY = ±18V INPUT
RL = 2kΩ VSY = 5V
0 CL = 100pF 0
VCM = 1.5V
DUT AV = –1
INPUT VOLTAGE (V)
RL = 2kΩ
INPUT VOLTAGE (V)

–5 –2 CL = 100pF
DUT AV = –1

–10 –4
ERROR BAND ERROR BAND
OUTPUT POST GAIN = 20
POST GAIN = 20
–15 –6
+10mV +4mV
–20 0V –8 0
–10mV –4mV
–25 –10 OUTPUT

15893-056
15893-053

–30 –12
TIME (400ns/DIV) TIME (400ns/DIV)

Figure 60. ADA4625-1 Positive Settling Time to 0.01%, VSY = ±18 V Figure 63. ADA4625-1 Positive Settling Time to 0.01%, VSY = 5 V

10 4
VSY = ±18V VSY = 5V
VCM = 0V VCM = 1.5V
5 2
RL = 2kΩ RL = 2kΩ
INPUT CL = 100pF CL = 100pF
DUT AV = –1 0 DUT AV = –1
0
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)

–5 –2
INPUT

–10 –4
ERROR BAND ERROR BAND
POST GAIN = 20 POST GAIN = 20
–15 +100mV –6 +40mV

OUTPUT OUTPUT
–20 0V –8 0

–25 –100mV –10 –40mV

15893-109
15893-108

–30 –12
TIME (400ns/DIV) TIME (400ns/DIV)

Figure 61. ADA4625-2 Negative Settling Time to 0.1%, VSY = ±18 V Figure 64. ADA4625-2 Negative Settling Time to 0.1%, VSY = 5 V

Rev. A | Page 18 of 35
Data Sheet ADA4625-1/ADA4625-2
10 4
VSY = ±18V
INPUT VCM = 0V VSY = 5V
5 2 VCM = 1.5V
RL = 2kΩ RL = 2kΩ
CL = 100pF CL = 100pF
DUT AV = –1 DUT AV = –1
0 0
INPUT VOLTAGE (V)

INPUT VOLTAGE (V)

–5 –2
INPUT

–10 –4
ERROR BAND ERROR BAND
POST GAIN = 20 POST GAIN = 20
–15 –6
OUTPUT
+10mV
OUTPUT +10mV
–20 0V –8 0
–10mV –10mV
–25 –10

15893-110

15893-113
–30 –12
TIME (400ns/DIV) TIME (400ns/DIV)

Figure 65. ADA4625-2 Negative Settling Time to 0.01%, VSY = ±18 V Figure 68. AD4625-2 Negative Settling Time to 0.01%, VSY = 5 V

10 4
INPUT
5 2
INPUT
VSY = ±18V
0 VCM = 0V 0 VSY = 5V
RL = 2kΩ VCM = 1.5V

INPUT VOLTAGE (V)

RL = 2kΩ
INPUT VOLTAGE (V)

CL = 100pF
–5 DUT AV = –1 –2 CL = 100pF
DUT AV = –1
–10 –4
ERROR BAND ERROR BAND
POST GAIN = 20 POST GAIN = 20
–15 +100mV –6 +40mV
OUTPUT OUTPUT
–20 0V –8 0

–25 –100mV –10 –40mV

15893-114
15893-111

–30 –12
TIME (400ns/DIV) TIME (400ns/DIV)

Figure 66. ADA4625-2 Positive Settling Time to 0.1%, VSY = ±18 V Figure 69. ADA4625-2 Positive Settling Time to 0.1%, VSY = 5 V

10 4

INPUT
5 2
INPUT
VSY = ±18V
VCM = 0V 0 VSY = 5V
0
RL = 2kΩ VCM = 1.5V
INPUT VOLTAGE (V)

CL = 100pF
INPUT VOLTAGE (V)

RL = 2kΩ
–5 DUT AV = –1 –2 CL = 100pF
DUT AV = –1
–10 –4
ERROR BAND OUTPUT ERROR BAND
OUTPUT POST GAIN = 20
POST GAIN = 20
–15 –6
+10mV +10mV
–20 0V –8 0
–10mV
–10mV
–25 –10
15893-115
15893-112

–30 –12
TIME (400ns/DIV) TIME (400ns/DIV)

Figure 67. ADA4625-2 Positive Settling Time to 0.01%, VSY = ±18 V Figure 70. ADA4625-2 Positive Settling Time to 0.01%, VSY = 5 V

Rev. A | Page 19 of 35
ADA4625-1/ADA4625-2 Data Sheet
10 10
BW = 80kHz, AV = +1 BW = 80kHz, AV = +1
BW = 80kHz, AV = –1 BW = 80kHz, AV = –1
BW = 500kHz, AV = +1 BW = 500kHz, AV = +1
1 BW = 500kHz, AV = –1 1 BW = 500kHz, AV = –1

0.1 0.1
THD + N (%)

THD + N (%)
0.01 0.01

0.001 0.001
VSY = ±18V VSY = 5V
RL = 2kΩ RL = 2kΩ
FREQUENCY = 1kHz FREQUENCY = 1kHz
0.0001 0.0001

15893-058

15893-061
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1
AMPLITUDE (V rms) AMPLITUDE (V rms)
Figure 71. ADA4625-1 Total Harmonic Distortion + Noise (THD + N) vs. Figure 74. ADA4625-1 THD + N vs. Amplitude, VSY = 5 V
Amplitude, VSY = ±18 V (BW Means Bandwidth)
0.1 0.1
VSY = ±18V BW = 80kHz, AV = +1 BW = 80kHz, AV = +1
BW = 80kHz, AV = –1 VSY = 5V
RL = 2kΩ RL = 2kΩ BW = 80kHz, AV = –1
VIN = 6V rms BW = 500kHz, AV = +1 VIN = 0.6V rms BW = 500kHz, AV = +1
BW = 500kHz, AV = –1 BW = 500kHz, AV = –1

0.01 0.01
THD + N (%)

THD + N (%)

0.001 0.001

0.0001 0.0001
15893-059

20 200 2k 20k

15893-062
20 200 2k 20k
FREQUENCY (Hz) FREQUENCY (Hz)
Figure 72. ADA4625-1 THD + N vs. Frequency, VSY = ±18 V Figure 75. ADA4625-1 THD + N vs. Frequency, VSY = 5 V

10
10
BW = 80kHz, AV = +1
BW = 80kHz, AV = –1 BW = 80kHz, AV = +1
BW = 500kHz, AV = +1 BW = 80kHz, AV = –1
1 BW = 500kHz, AV = –1 BW = 500kHz, AV = +1
1 BW = 500kHz, AV = –1

0.1
THD + N (%)

0.1
THD + N (%)

0.01
0.01

0.001
VSY = ±18V 0.001
RL = 2kΩ VSY = 5V
FREQUENCY = 1kHz RL = 2kΩ
FREQUENCY = 1kHz
0.0001
15893-116

0.001 0.01 0.1 1 10 0.0001

15893-118

0.001 0.01 0.1 1

AMPLITUDE (V rms)
AMPLITUDE (V rms)
Figure 73. ADA4625-2 THD + N vs. Amplitude, VSY = ±18 V
Figure 76. ADA4625-2 THD + N vs. Amplitude, VSY = 5 V

Rev. A | Page 20 of 35
Data Sheet ADA4625-1/ADA4625-2
0.1 0.1
VSY = ±18V BW = 80kHz, AV = +1 VSY = 5V BW = 80kHz, AV = +1
RL = 2kΩ BW = 80kHz, AV = –1 RL = 2kΩ BW = 80kHz, AV = –1
VIN = 6V rms BW = 500kHz, AV = +1 VIN = 0.6V rms BW = 500kHz, AV = +1
BW = 500kHz, AV = –1 BW = 500kHz, AV = –1

0.01 0.01
THD + N (%)

THD + N (%)
0.001 0.001

0.0001 0.0001

15893-117

15893-119
20 200 2k 20k 20 200 2k 20k
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 77. ADA4625-2 THD + N vs. Frequency, VSY = ±18 V Figure 80. ADA4625-2 THD + N vs. Frequency, VSY = 5 V

100
VSY = 5V VSY = 5V
VSY = ±18V VSY = ±18V

VOLTAGE NOISE DENSITY (nV/√Hz)

50nV/DIV

10
15893-060

15893-057
TIME (1s/DIV) 1 10 100 1k 10k 100k
FREQUENCY (Hz)

Figure 78. 0.1 Hz to 10 Hz Noise Figure 81. Voltage Noise Density vs. Frequency

400 5.0
5 AMPLIFIERS TA = +125°C
TA = 25°C
4.5
300
TA = +85°C
4.0
200 TA = +25°C
3.5
TA = –40°C
100
3.0
VOS (µV)

ISY (mA)

0 2.5

2.0
–100
1.5
–200
VCM = VSY/2 1.0
VCM = VSY/2
–300
0.5

–400 0
15893-065

15893-063

4 8 12 16 20 24 28 32 36 0 4 8 12 16 20 24 28 32 36
VSY (V) VSY (V)

Figure 79. VOS vs. VSY Figure 82. Supply Current (ISY) vs. VSY for Various Temperatures

Rev. A | Page 21 of 35
ADA4625-1/ADA4625-2 Data Sheet
140 25
VSY = 5V, VCM = 1.5V
20 VSY = ±18V
130
15
120
10
110
5
PSRR (dB)

VOS (µV)
100 0

–5
90
–10
80
–15
70
VSY = ±5V TO ±18V –20
VSY = +4.5V TO +10V
60 –25

15893-032

15893-009
–40 –25 –10 5 20 35 50 65 80 95 110 125 –40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 83. PSRR vs. Temperature Figure 85. VOS vs. Temperature

0 40
AV = 10 VSY = ±18V
VIN = 1V p-p VSY = ±2.5V
–20 RL = 2kΩ 35 VSY = ±18V
VSY = ±2.5V
CHANNEL SEPARATION (dB)

30
OUTPUT VOLTAGE (V p-p)
–40
MAXIMUM
25 OUTPUT
–60 VOLTAGE
WITHOUT SID
20
–80
15

–100
10

–120 5

–140 0
15893-120

15893-064
10k 100k 1M 10M 100M 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 84. Channel Separation vs. Frequency Figure 86. Maximum Peak-to-Peak Output Voltage Without Slew Rate
Induced Distortion (SID) vs. Frequency

Rev. A | Page 22 of 35
Data Sheet ADA4625-1/ADA4625-2

THEORY OF OPERATION
Figure 87 shows the simplified circuit diagram for the
ADA4625-1/ADA4625-2. The JFET input stage architecture
offers the advantages of low input bias current, high bandwidth,
high gain, low noise, and no phase reversal when the applied
input signal exceeds the common-mode voltage range. The
output stage is rail to rail with high drive characteristics and low
dropout voltage for both sinking and sourcing currents.
INPUT AND GAIN STAGES
To achieve high input impedance, low noise, low offset, and low
offset drift, the ADA4625-1/AD4625-2A uses large input
N channel JFETs (M1 and M2). These JFETs operate with the
S source at about 1.2 V above the G gate. In the worst case, the
source is only 0.9 V above the gate. By design, the normal operation
of the input tail current (ITAIL) extends down to 0.6 V above V−,
which gives the ADA4625-1/ADA4625-2 an input common-mode
range down to 0.2 V below V− with margin. Resistive loads keep
the noise low. The BUFF1 buffer drives the top of the input load
resistors (R1 and R2), keeping the voltage drop across M1 and
M2 nearly constant, making a virtual cascode. The differences
of the input voltages of +IN and –IN steer ITAIL through M1 and
M2 to R1 and R2, generating a differential voltage. The first
voltage to current gain block (GM1) translates that differential
voltage into differential currents (I1 and I2) that drive the current
mirror (Q1 and Q2), which generates a differential voltage
between the reference node and gain node. JFET inputs of the
second voltage to current gain block (GM2) maximizes the gain
node impedance, giving the ADA4625-1/ADA4625-2 a high gain.
OUTPUT STAGE
The GM2 gain block generates two pairs of differential currents.
One pair drives the bottom current mirror (Q3 and Q4) and the
NPN output transistor (Q7), and the second pair drives the top
current mirror (Q5 and Q6) and the output PNP transistor (Q8).
The common emitter output transistors (Q7 and Q8) source and
sink current rail to rail. GM2 also senses the base voltages of Q7
and Q8 and adjusts the I4 and I6 currents; with no output load,
Q7 and Q8 collector currents are 0.6 mA. In addition, GM2
clamps the base voltages of Q7 and Q8 so neither completely
turns off.

V+

BUFF1 Q5 Q6
G D D G
+IN M4 M3 –IN OUTPUT
S S PNP
INPUT LOAD BIAS Q10 Q9 Q8
R1 RESISTORS R2
AND VOS TRIM
I5 I6
ITC1 ITC2 DIFFERENTIAL GM1
5V
LEVEL SHIFT TCVOS VOLTAGE V/I GAIN DIFFERENTIAL CCOMP1 OUT
TRIM CURRENTS

I1 I2 GAIN NODE
GM2
V/I GAIN AND
D JFET D OUTPUT
G INPUT PAIR M2 G REF NODE BIAS
–IN M1 OUTPUT
I4
S S CCOMP2 NPN
I3 Q7

+IN
ITAIL
Q1 Q2 Q3 Q4
INPUT
15893-066

TAIL CURRENT
V–

Figure 87. Simplified Circuit Diagram

Rev. A | Page 23 of 35
ADA4625-1/ADA4625-2 Data Sheet
NO PHASE INVERSION SUPPLY CURRENT
Rail-to-rail output (RRO) amplifiers without rail-to-rail input The supply current (ISY) is the quiescent current drawn by the
(RRI) are prone to phase inversion because the output can drive op amp with no load. Figure 89 and Figure 90 show that the
the input outside of the normal common-mode range, causing quiescent current varies with the common-mode input voltage.
the output to go in the wrong direction and latch up. To prevent The shape of ISY vs. VCM at higher VCM shows saturation of
phase inversion, the input must control the input at all times. BUFF1 and the ITAIL turn off.
Even though the RRO of the ADA4625-1/ADA4625-2 input 5.0
TA = +125°C
stage (M1, M2, R1, and R2) operates correctly down to 0.2 V
below V−, it does not operate correctly within 2.5 V of V+. The 4.5 TA = +85°C

ADA4625-1/ADA4625-2 guarantees no phase inversion by TA = +25°C

implementing an input pair (M3 and M4) to extend the 4.0

common-mode range to 0.2 V above V+, with reduced TA = –40°C

ISY (mA)
performance. M3 and M4 are not active in the normal 3.5

common-mode range. Figure 88 shows that the input voltage

exceeds both supplies by 200 mV with no phase inversion at the 3.0

output.
25 2.5
VSY = ±18V
INPUT VOLTAGE AND OUTPUT VOLTAGE (V)

20 VIN = 36.4V p-p

AV = 1 2.0

15893-068
15 –18.2 –12.2 –6.2 –0.2 5.8 11.8 17.8
VCM (V)
10
Figure 89. ISY vs. VCM, VSY = ±18 V
5
5.0
0
TA = +125°C
–5 4.5
TA = +85°C
–10 VOUT
4.0 TA = +25°C
–15
ISY (mA)

–20
VIN 3.5 TA = –40°C
15893-067

–25
TIME (200µs/DIV)
3.0
Figure 88. No Phase Reversal if the Input Range Exceeds the Power Supply
by 200 mV
2.5

2.0

15893-069
–0.2 0.7 1.6 2.5 3.4 4.3 5.2
VCM (V)

Figure 90. ISY vs. VCM, VSY = 5 V

Rev. A | Page 24 of 35
Data Sheet ADA4625-1/ADA4625-2

APPLICATIONS INFORMATION
ACTIVE LOOP FILTER FOR PHASE-LOCKED LOOPS Loop Filter
(PLLS) The loop filter, which smooths out the error signal, is a critical
PLL Basic part of the system. For applications that require low phase noise
A PLL is a feedback system that combines a phase detector and a wide tuning range, design the VCO with a low gain and a
(PD), a loop filter, and a voltage controlled oscillator (VCO) large input voltage range to satisfy these requirements. When the
that is so connected that the oscillator maintains a constant required VCO tuning voltage is higher than the maximum
frequency (or phase angle) relative to the reference signal. The voltage the charge pump can supply, implement an active loop
functional block diagram of a basic PLL is shown in Figure 91. filter comprising of an op amp with gain to accommodate the
higher tuning voltages. Figure 93 and Figure 94 illustrate the typical
PHASE CHARGE LOOP
fREF DETECTOR PUMP FILTER
VCO fOUT active loop filters in inverting and noninverting topologies,
respectively, with prefiltering.

15893-071
N DIVIDER

CHARGE
Figure 91. Basic PLL PUMP
OUTPUT VCO
INPUT
The phase detector detects the phase difference between the
input reference signal and the feedback signal. The resulting

15893-073
error signal is proportional to the relative phase of the input
and the feedback signals. The charge pump converts the PD Figure 93. Typical Active Loop Filter—Inverting Topology
error signal into current pulses. A loop filter circuit is typically
required to integrate and smooth the source and sink current CHARGE VCO
INPUT
pulses from the charge pump into a voltage, which in turn drives PUMP
OUTPUT
the VCO. The VCO outputs a range of frequencies depending
on the voltage level at its tuning port. By making the frequency

15893-074
N divider programmable, the VCO frequency can be tuned in
either integer steps or fractional amounts characterizing the PLL
as either an integer-N PLL or a fractional-N PLL. Because a PLL Figure 94. Typical Active Loop Filter—Noninverting Topology
is a negative feedback loop, the output of the VCO adjusts as The inverting topology has the advantage of biasing the charge
necessary until the frequency error signal is zero and the PLL is pump output at a fixed voltage, typically one-half the charge
in lock. The output frequency is given by fOUT = N × fREF. pump voltage (VP/2), which is optimal for spur performance.
Figure 92 shows the block diagram of the basic PLL model in When using the inverting topology, ensure that the PLL IC
the Laplace transform format, where fREF is the frequency of the allows the phase detector polarity to be inverted for the correct
input signal, and fOUT is the frequency of the VCO output signal. polarity voltage at the output of the op amp for driving the VCO.
Because the phase difference is the integral of the frequency
difference, there is a 1/s term in the PLL loop.
PHASE CHARGE LOOP
DETECTOR PUMP FILTER VCO

+ 1
fREF PD Kd Z(s) KV fOUT
s
–

N DIVIDER
15893-072

1
N

Figure 92. Basic PLL Model

Rev. A | Page 25 of 35
ADA4625-1/ADA4625-2
ADA4625-1 ADVANTAGES AND DESIGN EXAMPLE
The op amp choice for an active filter affects the key performance
parameters of the PLLs: frequency range, phase noise, spurious
frequencies, and lock time. The output of the filter directly
affects the generated frequency and phase. Low noise is
essential because any voltage noise applied to the tuning port
of the VCO is amplified by the VCO gain and translated into
phase noise. Low input bias current is also recommended
because the op amp bias current must be sourced from the PLL
phase detector/ charge pump, and any mismatch or leakage at
the output of the phase detector between the up and down
currents causes ripples and reference spurs.
With 18 MHz gain bandwidth product (GBP), low input bias
currents (±15 pA), low voltage noise density (3.3 nV/√Hz),
ultralow current noise density, and low 1/f corner frequency,
the ADA4625-1 is an ideal op amp for using in a PLL active
loop filter. The ADA4625-1 does not require a negative voltage
supply because of its ground sensing input. The rail-to-rail
Data Sheet
configuration. The VCO is set up to feedback the VCO/2 output
to the ADF4159. The loop filter has a 900 kHz loop bandwidth
(LBW) and a phase margin of 58° with 2.5 mA charge pump
current. Lowering the bandwidth further improves phase noise
at the expense of increased PLL lock time.
Figure 95 shows the PLL loop filter transfer function. Capacitor C1
and Resistor R1 change the phase detector current pulses into a
continuous time voltage waveform. At frequencies lower than
the R2C2 zero, the amplifier and R1C2 form an integrator.
Between the R2C2 zero and the R2C3 pole, the gain is constant
at the value set by R2/R1. Above the R2C3 pole, the amplifier is
an integrator until R1C3 becomes a feedforward noninverting
zero path around the amplifier. Resistor R3 and Capacitor C4
add an additional pole in the loop filter signal path. Setting the
R3C4 pole below the R2C3 pole reduces the effect of the R1C3
feedforward zero.
R3C4 POLE
R2C2 ZERO

GAIN (dB)
R2C3 POLE
output stage is beneficial in terms of increasing the flexibility
in biasing the op amp so that the output range of the PLL is
mapped efficiently onto the input range of the VCO. In
0dB
addition, the wide 5 V to 36 V operating supply range makes
R2/R1
the ADA4625-1 a versatile choice for the design of a wide AMP GAIN

15893-076
R1C1 POLE
variety of active loop filters. LOG FREQUENCY

Figure 96 shows the ADA4625-1 as the loop filter for the Figure 95. PLL Loop Filter Transfer Function
ADF4159, a 13 GHz fractional-N synthesizer. The phase
detector polarity of the ADF4159 is programmed to negative
because the ADA4625-1 is used in an inverting active loop filter

C3
3.3V 1.8V 3.3V
33pF
R2 C2

AVDD DVDD VP 1kΩ 3.3nF

15V
R1
ADF4159 100Ω R3
RFINx FRACTIONAL-N CP 365Ω
SYNTHESIZER C1 ADA4625-1
220pF 3.3V
100MHz REFIN C4
AGND DGND CPGND SDGND 47kΩ U4 100pF

47kΩ 1µF
100pF
5V

VCC
6dB PAD 11.4GHz TO 12.8GHz
VCO
6GHz RFOUT/2
5.7GHz TO 6.4GHz VTUNE
52pF
RFOUT
11.4GHz TO 12.8GHz GND
15893-075

12GHz OUTPUT

Figure 96. Block Diagram of ADA4625-1 Active Loop Filter for ADF4159

Rev. A | Page 26 of 35
Data Sheet ADA4625-1/ADA4625-2
PLLs in which the loop gain passes through 0 dB above the R2C2 TRANSIMPEDANCE AMPLIFIER
zero and below the R2C3 pole and R3C4 pole are stable. At low The ADA4625-1 is an excellent choice for low noise transimpe-
charge pump currents, the loop gain passes through zero above dance amplifier (TIA) applications. While its low voltage and
R2C2 zero. At high charge pump currents, the loop gain passes current noise maximize signal-to-noise ratio (SNR), its low
through zero below the R2C3 pole and R3C4 pole (see Figure 97). voltage offset and input bias current minimize the dc error at
the amplifier output. Having a true ground sense capability, the
0dB FULL LOOP GAIN
HIGH CURRENT ADA4625-1 is ideal for single-supply operation. In addition, its
0dB FULL LOOP GAIN
LOW CURRENT rail-to-rail output swing allows the detection and amplification
of a wide range of input current signals. Figure 99 shows the
ADA4625-1 as a current to voltage (I-V) converter with an
GAIN (dB)

0 electrical model of a photodiode.

CF

RF

LOG FREQUENCY –
LOOP WITHOUT FILTER, HIGH CURRENT LOOP FILTER GAIN CM
LOOP WITHOUT FILTER, LOW CURRENT ID CD CD VOUT
RSH = 1011Ω
LOOP FILTER CM
15893-077

FULL LOOP, HIGH CURRENT +

VB ADA4625-1

15893-081
FULL LOOP, LOW CURRENT

Figure 97. Gain vs. Frequency of PLL and Loop Filter

Figure 99. Equivalent TIA Circuit
Figure 98 shows the measured phase noise vs. frequency offset
from 12 GHz carrier for different charge pump currents (ICP). Photodiodes can operate in either photovoltaic mode (zero
Generally, most operations have a charge pump current of bias) or photoconductive mode (with an applied reverse-bias
2.5 mA and below. Refer to the UG-383 User Guide for details across the diode). Mode selection depends on the speed and
on running these tests and setting up the software required. dark current requirements of the application and the choice of
–60 photodiode. In photovoltaic mode, the dark current is at a
ICP = 4.7mA
minimum and is preferred for low frequency and/or low light
–80 level applications (that is, PN photodiodes). Photoconductive
ICP = 2.5mA
mode is better for applications that required faster and linear
PHASE NOISE (dBc/Hz)

–100 responses (that is, PIN photodiodes); however, the tradeoffs

include increases in dark and noise currents.
–120
The following transfer function describes the transimpedance
ICP = 0.31mA gain of Figure 99:
–140
I D RF
VOUT = (1)
–160
1 + sC F RF
where:
–180
VOUT is the desired output dc voltage of the op amp.
15893-078

1k 10k 100k 1M 10M 100M

FREQUENCY OFFSET FROM 12GHz CARRIER (Hz) ID is the output current of the photodiode.
Figure 98. Phase Noise vs. Frequency Offset from 12 GHz Carrier for Different RF and CF are the feedback resistor and capacitor. The parallel
Charge Pump Currents (ICP) combination of RF and CF sets the signal bandwidth.
s is the s plane.
The Analog Devices simulation tool, ADIsimPLL, allows the
design and simulation of PLL loop filter topologies and has a Set RF such that the maximum attainable output voltage
library of Analog Devices op amps built in. The simulation tool corresponds to the maximum diode output current. Because
accurately predicts PLL closed-loop phase noise and is able to signal levels increase directly with RF, while the noise due to RF
model the effect of op amp noise along with the noise of the increases with the square root of the resistor value, employing
other PLL loop components. For more information about the the full output swing maximizes the SNR.
ADIsimPLL design tools, refer to www.analog.com/ADIsimPLL.

Rev. A | Page 27 of 35
ADA4625-1/ADA4625-2 Data Sheet
It is important to distinguish between the signal gain and the Setting the pole at the fX frequency maximizes the signal bandwidth
noise gain (NG) because the noise gain characteristics with a 45° phase margin but is marginal for stability, as indicated by
determine the net circuit stability. The noise gain has the same the dashed line. Because fX is the geometric mean of fZ and the
transfer function as the noninverting signal gain, which follows: gain bandwidth product frequency (fGBP) of the amplifier,
calculate fX by
 R  1 + s (RF // RSH )(C IN + C F )
NG = 1 + F ×
 (2)
 RSH  1 + sR F C F f X = f Z f GBP (6)

where: Substituting Equation 4 and Equation 5 into Equation 6, the CF

RSH is the diode shunt resistance. value that produces fX is
CIN is the total input capacitance consisting of the sum of the
1 + 1 + 8πRF C IN f GBP
diode shunt capacitance (CD), the input capacitance of the CF = (7)
amplifier (CDM + CCM), and the external stray capacitance. 4 πRF f GBP
CIN and RF produce a zero in the noise gain transfer function If 8π × RF × CIN × fGBP >> 1, Equation 7 simplifies to
and the zero frequency (fZ) is as follows:
C IN
1 CF = (8)
fZ = (3) 2πRF f GBP
2π (RF // RSH )(C IN + C F )
Adding CF also sets the signal bandwidth at fP. Substitute
Because the photodiode shunt resistance RSH >> RF, the circuit
Equation 8 into Equation 5 and rearrange the equation for the
behavior is not impacted by the effect of the junction resistance,
signal bandwidth in terms of fGBP, RF, and CIN:
and fZ simplifies to
1 f GBP
fZ = (4) fP = (9)
2πRF (C IN + C F ) 2πRF C IN

Figure 100 shows the TIA noise gain superimposed upon the open Notice the attainable signal bandwidth is a function of the time
loop gain of the amplifier. For the system to be stable, the noise gain constant RFCIN and the fGBP of the amplifier. To maximize the
curve must intersect with the open loop response with a net slope signal bandwidth, choose an op amp with high bandwidth and
of less than 20 dB/decade. In Figure 100, the dotted line shows an low input capacitance, and operate the photodiode in reverse
uncompensated noise gain (CF = 0 pF) intersecting with the open bias to reduce its junction capacitance.
loop gain at the frequency (fX) with a slope of 20 dB/decade, Because the input current noise of the FET input op amp is
indicating an unstable condition. negligible, and the shot noise of the photodiode is negligible
due to the filtering effect of the shunt capacitance, the dominant
UNCOMPENSATED
sources of output noise in the wideband photodiode TIA circuit
(CF = 0pF)
are the input voltage noise of the amplifier eN and the thermal
OPEN LOOP GAIN noise generated by RF.
At low frequencies, the circuit noise gain is 1 + RF/RSH. At
COMPENSATED
GAIN

frequencies equal to or greater than fZ, the noise gain begins to

SIGNAL BANDWIDTH increase and plateau when the gain is 1 + CIN/CF (see Figure 100).
CIN
In addition, the noise bandwidth frequency, fN (where the
1+
CF compensated noise gain intersecting the open loop gain), can
R2 NOISE GAIN fGBP be estimated by
1+
R1
fZ fp fx fN CF
15893-082

fN = fGBP (10)
FREQUENCY (C IN + CF )
Figure 100. Generalized TIA Noise Gain and Transfer Function
The instability caused by CIN can be compensated by adding CF to
introduce a pole at a frequency equal to or lower than fX. The pole
frequency is as follows:
1
fP = (5)
2πRF C F

Rev. A | Page 28 of 35
Data Sheet ADA4625-1/ADA4625-2
100 1M
Design Example
As a design example, Figure 101 shows the ADA4625-1
80 100k
configured as a TIA amplifier in a photodiode preamp I-V GAIN

application. Assuming the photodiode has a CD of 5 pF and an ID

60 10k
of 200 µA, and the desired full-scale VOUT is 10 V, and using OPEN-LOOP

I-V GAIN (Ω)

GAIN

GAIN (dB)
Equation 1, RF is 50 kΩ.
40 1k
2.2pF

49.9kΩ 20 100

+15V NOISE GAIN

0 10

0.1µF
–20 1
VOUT 1k 10k 100k 1M 10M 100M 1G 10G

15893-085
ADA4625-1
FREQUENCY (Hz)
1kΩ
15893-083
Figure 103. Compensating the TIA, CF = 3.9 pF
150

CF = 2.2pF
Figure 101. Single-Supply TIA Circuit Using the ADA4625-1

The ADA4625-1 input capacitance (CCM + CDM) is 19.9 pF; 100

OUTPUT VOLTAGE (%)

therefore, the total input capacitance (CIN) is 24.9 pF. By
CF = 3.9pF
substituting CIN = 24.9 pF, RF = 50 kΩ, and fGBP = 18 MHz into
Equation 7 and Equation 9, the resulting feedback capacitor 50

value (CF) and the −3 dB signal bandwidth (fP) are 2.2 pF and
1.45 MHz, respectively.
0
Figure 102 and Figure 103 show the compensations of the TIA
circuit. The system has a bandwidth of 1.45 MHz when it is
maximized for a signal bandwidth with CF = 2.2 pF. Increasing CF

15893-086
–50
to 3.9 pF reduces the bandwidth to 0.82 MHz; however, it greatly TIME(1µS/DIV)
reduces the overshoot (see Figure 104). In practice, an optimum Figure 104. Pulse Response vs. CF
CF value is determined experimentally by varying it slightly to
optimize the output pulse response.
100 1M

80 100k
I-V GAIN

60 10k
OPEN-LOOP
I-V GAIN (Ω)

GAIN
GAIN (dB)

40 1k

20 100

NOISE GAIN
0 10

–20 1
1k 10k 100k 1M 10M 100M 1G 10G
15893-084

FREQUENCY (Hz)

Figure 102. Compensating the TIA, CF = 2.2pF

Rev. A | Page 29 of 35
ADA4625-1/ADA4625-2 Data Sheet
Table 8 shows the noise sources and estimated total output noise
for the photodiode amplifier with CF = 2.2 pF and CF =3.9 pF,
respectively.
Use the Analog Devices Analog Photodiode Wizard to design a
transimpedance amplifier circuit to interface with a photodiode.

Table 8. RMS Noise Contributions of the Photodiode Preamplifier

RMS Noise (µV) 1
Noise Contributor Expression CF = 2.2 pF CF = 3.9 pF
RF π 43.2 32.5
4kTRF  f P 
2 
where:
k is Boltzmann’s constant (1.38 × 10−23 J/K).
T is the temperature in Kelvin (K).
Current Noise, Vni, AMP π 0.34 0.25
iN RF fp
2
Voltage Noise, Vnv, AMP 61.6 47.7
 C π
eN 1 + IN  fGBP
2
 CF 
Total Noise Vnv , AMP 2 + Vnv , AMP 2 + VRF 2 75.2 57.7

1
RMS noise with RF = 49.9 kΩ, CIN = CCM + CDM = 19.9 pF, CD = 5 pF, iN = 4.5 fA/√Hz, and eN =3.3 nV/√Hz.

Rev. A | Page 30 of 35
Data Sheet ADA4625-1/ADA4625-2
DAC OUTPUT DRIVER
+15V
PRECISION R1 1/2
5V DC + AD8676B
SOURCE 1.5kΩ C1 +
10µF A1
– 1/2
+3.3V +15V AD8676B
−15V 10µF 10µF
+ –

+
R3 B1
+15V −15V
1kΩ
R2 0.1µF 0.1µF
1kΩ
10 9 5 4 3 20
RFB

IOVCC

VCC

VDD
+15V

VREFPF

VREFPS
7 CLR

8 LDAC –
INV 1
–10V TO +10V
11 SDO C1 OUTPUT
SPI INTERFACE VOLTAGE
AND DIGITAL 14 SYNC VOUT 2 +
AD5791B ADA4625-1
CONTROL
13 SCLK
−15V

VREFNF

VREFNS
12 SDIN

AGND
DGND

VSS
6 RESET
15 18 16 17 19
0.1µF

R5 B2
2kΩ + –
+

10µF
R4 1/2
1kΩ AD8676B
– –15V
A2

15893-121
+
1/2
AD8676B
Figure 105. 20-Bit Accurate, ±10 V Voltage Source (Simplified Schematic: All Connections and Decoupling Not Shown)

ADA4625-1 can be used as an output buffer for 20-bit accurate, Figure 106 and Figure 107 show the INL response with the
±10 V voltage source with the AD5791 and the LTC6655. The EVAL-AD5791SDZ and the step response of the ADA4625-1 in
low voltage noise, low drift output drive capability of the comparison to the AD8675, respectively.
ADA4625-1, as well as dynamic parameters such as fast settling
time and slew rate make the device an ideal DAC output buffer.
It is recommended to provide supplies of ±15 V to obtain the
full potential of the ADA4625-1 in this application due to the ADA4625-1
VOLTAGE (200mV/DIV)

AD8675
input VCM range of the device.
2.0

1.5

1.0

0.5 TA = 25°C
EVAL-AD5791SDZ
INL (LSB)

1V STEP FROM DAC

0
15893-123

OUTPUT READ AT VO_BUF

TIME (500ns/DIV)
–0.5
Figure 107. Step Response with ADA4625-1 and AD8675 Output Buffers
–1.0 LTC6655 REFERENCE
ADA4625-1 OUTPUT BUFFER
ON-BOARD SUPPLIES FROM ADP7118 AND ADP7182
–1.5 3458A DMM, NPLC = 10
STEP SIZE = 1024
TA = 25°C
–2.0
15893-122

0 200000 400000 600000 800000 1000000 1200000

DAC CODES

Figure 106. AD5791 with LTC6655 and ADA4625-1 as Output Buffer INL
Performance

Rev. A | Page 31 of 35
ADA4625-1/ADA4625-2
RECOMMENDED POWER SOLUTION
Analog Devices has a wide range of power management
products to meet the requirements of most high performance
signal chains.
For a dual-supply application, the ADA4625-1 typically needs a
±15 V supply. Low dropout (LDO) linear regulators such as the
ADP7118 or the ADP7142 for the positive supply and the
ADP7182 for the negative supply help improve the PSRR at
high frequency and generate a low noise power rail. In addition,
if a negative supply is not available, the ADP5070 can generate
the negative supply from a positive supply. Figure 108 shows an
example of this power solution configuration for the ADA4625-1.
+16V
ADP7118 +15V
+12V ADP5070
15893-070
–16V
ADP7182 –15V
Figure 108. Power Solution Configuration for the ADA4625-1
Table 9. Recommended Power Management Devices
Product Description
ADP5070 DC-to-dc switching regulator with independent
positive and negative outputs
ADP7118 20 V, 200 mA, low noise, CMOS LDO linear regulator
ADP7142 40 V, 200 mA, low noise, CMOS LDO linear regulator
ADP7182 −28 V, −200 mA, low noise, linear regulator
It is recommended to use a low ESR, 0.1 μF bypass capacitor close
to each power supply pins of the ADA4625-1 and ground to
reduce errors coupling in from the power supplies. For noisy
power supplies, place an additional 10 μF capacitor in parallel
with the 0.1 μF for better performance.
INPUT OVERVOLTAGE PROTECTION
The ADA4625-1 has internal protective circuitry that allows
voltages as high as 0.2 V beyond the supplies to be applied at the
input of either terminal without causing damage. For higher
input voltages, a series resistor is necessary to limit the input
current. Determine the resistor value by
(VIN − VS)/RS ≤ 20 mA
where:
VIN is the input voltage.
VS is the voltage of either V+ or V−.
RS is the series resistor.
With a very low bias current of <5.5 nA up to 125°C, higher
resistor values can be used in series with the inputs. A 500 Ω
resistor protects the inputs from voltages as high as 10 V beyond
the supplies and adds less than 2.75 µV to the offset. However,
note that the added series resistor (RS) may increase the overall
noise and lower the bandwidth due to the addition of a pole
introduced by RS and the input capacitor of the amplifier.
DRIVING CAPACITIVE LOADS
The inherent output resistance of the op amp combined with a
capacitive load forms an additional pole in the transfer function
of the amplifier. Adding capacitance to the output of any op amp
Rev. A | Page 32 of 35
Data Sheet
results in additional phase lag. This lag reduces stability and
leads to overshoot or oscillation, which is a common situation
when an amplifier is used to drive the input of switched
capacitor analog-to-digital converters (ADCs).
The ADA4625-1 has a high phase margin and low output
impedance and is capable of directly driving a capacitive load
up to 1 nF with no external compensation at unity-gain without
oscillation.
For other considerations and various circuit solutions, see the
Ask the Applications Engineer-25, Op Amps Driving Capacitive
Loads Analog Dialogue article.
THERMAL MANAGEMENT
The ADA4625-1 can operate with up to a 36 V supply voltage
with a typical 4 mA quiescent current. Heavy loads increase
power dissipation and raise the chip junction temperature.
The maximum safe power dissipation for the ADA4625-1 is
limited by the associated rise in junction temperature (TJ) on
the die. Two conditions affect TJ: power dissipation (PD) of the
device and ambient temperature (TA) surrounding the package.
This relationship is shown in Equation 11.
TJ = PD × θJA + TA (11)
where θJA is the thermal resistance between the die and the
ambient environment. The total power dissipation in the
amplifier is the sum of the power dissipated in the output stage
plus the quiescent power. Power dissipation for the sourcing
current is shown in Equation 12, where VSY is the total supply
voltage (V+) – (V−).
PD = VSY × ISY + ((V+) − VOUT)IOUT (12)
Replace ((V+) − VOUT) in Equation 12 with ((V−) − VOUT) when
sinking current.
For symmetrical supplies with a ground referenced load, use the
following equation to calculate the average power for the amplifier
processing sine signal.
PAVG, SINE =
    (13)
(VSY × I SY ) +  2 × (V +) × VPEAK  −  VPEAK
2

π RL   2 ×RL 
where VPEAK is the peak value of a sine wave output voltage.
The specified thermal resistance θJA of the ADA4625-1/ADA4625-2
is 52.8°C/W. A good PCB layout and an external heat sink can
improve thermal performance by reducing junction to ambient
temperature.
The ADA4625-1/ADA4625-2 features an exposed pad that
floats internally to provide the maximum flexibility and ease of
use. Solder the exposed pad to the PCB board GND, or the V+
or V− plane for best thermal transfer. Where thermal heating is not
an issue, the exposed pad can be left floating.
Incorporate the use of thermal vias or heat pipes into the design
of the mounting pad for the exposed pad to lower the overall θJA.
Data Sheet ADA4625-1/ADA4625-2
TYPICAL APPLICATIONS
R3
3.9kΩ

+18V
R11 8
100MΩ 2
1 OUTPUT
R2 3 1/2
200Ω C11
4 ADA4625-2
–18V
C2
0.47µF
CT R4
R8 R6 6 1MΩ
HYDRO- 100MΩ
PHONE 100kΩ 7 R5
5 1MΩ
1/2
R7
1MΩ ADA4625-2

1OPTIONAL

DC OUTPUT ≤ 750µV FOR TA < 125°C.

15893-124
OUTPUT VOLTAGE NOISE = 128nV/√Hz AT 1kHz (GAIN = 20).
C1 ≈ CT ≈ 100pF TO 5000pF; R4 × C2 > R8 × CT.

Figure 109. Low Noise Hydrophone Amplifier with DC Servo

C1
1250pF

R1 R2
100MΩ 18kΩ

R3 C2
2kΩ 2µF
R4
6 20MΩ
7 R5
5 20MΩ
1/2
ADA4625-2 C3
2µF
+18V
8
ACELEROMETER 2
B & K MODEL 4381 OUTPUT
OR EQUIVALENT 1
3
1/2
4 ADA4625-2
–18V

R4 × C2 = R5 × C3 > R1 (1 + R2/R3) C1.

OUTPUT = 0.8mV/pC = 80mV/g.
15893-125

DC OUTPUT ≤ 1mV FOR TA < 25°C.

OUTPUT NOISE = 6.6nV/√Hz AT 1kHz.

Figure 110. Accelerometer Amplifier with DC Servo

Rev. A | Page 33 of 35
ADA4625-1/ADA4625-2 Data Sheet
PREAMP
LOW
DC SUPPLY
10pF

3.9MΩ 470kΩ
100kΩ 100pF
6
7
0.022µF
5
T 1/2
0.47pF ADA4625-2
PREAMP
390pF OUT
R 1MΩ 1.5kΩ 560kΩ

AC SUPPLY

2
470kΩ 4.7kΩ 3 1

500kΩ

10pF
2
1
3

15893-126
1/2
ADA4625-2
Figure 111. Guitar Preamplifier

R2
237kΩ

R5
154kΩ
C1
+18V 33nF
R1 R3 8
237kΩ 249kΩ 2 R4 R6
VIN C3
1 154kΩ 249kΩ 6 10nF
C2
100nF 3 7
1/2 VOUT
4 ADA4625-2 C4 5
1/2
330nF ADA4625-2
–18V

TYPICAL OFFSET ≈ 30µV.

1% TOLERANCES
VIN = 10V p-p, VOUT = –110dB AT f > 300Hz 15893-127

VOUT = –6dB AT f = 16Hz

THE LOW INPUT BIAS CURRENTS ALLOW THE USE OF HIGH RESISTOR VALUES.

Figure 112. 10 Hz Fourth-Order Chebyshev Low-Pass Filter (0.01 dB Ripple)

Rev. A | Page 34 of 35
Data Sheet ADA4625-1/ADA4625-2

OUTLINE DIMENSIONS
5.00
4.90 2.29
4.80 0.356

8 5 6.20
4.00 6.00
3.90 5.80 2.29
3.80 0.457
1 4

FOR PROPER CONNECTION OF

1.27 BSC BOTTOM VIEW THE EXPOSED PAD, REFER TO
3.81 REF THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
TOP VIEW SECTION OF THIS DATA SHEET.
1.75 1.65 0.50 45°
1.35 1.25 0.25
0.25
0.17
0.10 MAX
SEATING
PLANE 0.51 0.05 NOM 8°
1.04 REF
COPLANARITY 0° 1.27
0.31 0.10 0.40

06-02-2011-B
COMPLIANT TO JEDEC STANDARDS MS-012-A A

Figure 113. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP]
Narrow Body
(RD-8-1)
Dimensions shown in millimeters

ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADA4625-1ARDZ −40°C to +125°C 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] RD-8-1
ADA4625-1ARDZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] RD-8-1
ADA4625-1ARDZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] RD-8-1
ADA4625-2ARDZ −40°C to +125°C 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] RD-8-1
ADA4625-2ARDZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] RD-8-1
ADA4625-2ARDZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] RD-8-1
EVAL-ADA4625-1ARDZ Evaluation Board
EVAL-ADA4625-2ARDZ Evaluation Board
1
Z = RoHS Compliant Part.

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registered trademarks are the property of their respective owners.
D15893-0-6/19(A)

Rev. A | Page 35 of 35