BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, Pilani

Pilani Campus
Instruction Division

Course Handout (Part – II)

Course No : EEE/INSTR/CS F241

Course Title : CS/EEE/INSTR F241 Microprocessor Programming & Interfacing
Instructor-in- Charge : Dr. Nitin Chaturvedi
Instructor : Prof. J P Mishra, Dr. Vinay Chamola, Dr. G S Sesha Chalapathi,
Dr. Aditya Raw Gautam, Dr. Shishir Maheshwari, Mr. Devesh Samaiya
email : nitin80@pilani.bits-pilani.ac.in

1. Scope and Objective :

This course is a basic introduction to processor ISA, Assembly programming, Computer &
Embedded Architecture. Intel 80x86 is used as a platform through the course. 8086 - 80486
Programmers model of processor, processor architecture; Instruction set, modular assembly
programming using subroutines, macros etc.; Timing diagrams; Concept of interrupts: hardware
& software interrupts, Interrupt handling techniques, Interrupt controllers. Types of Memory &
memory interfacing. Programmable Peripheral devices and I/O Interfacing, DMA controller and
its interfacing. Design of processor based system.

2. Text Book:

Barry B Brey, The Intel Microprocessors .Pearson, Eight Ed. 2009.

3. Reference Books:

Douglas V Hall, Microprocessor and Interfacing, TMH, Second Edition.

4. Course Plan :

Lect.No. Learning Objectives Topics to be covered Reference to Text

1 Introduction to Compute Architecture, Memory & I/O Chapter 1

Microprocessor and organization, CISC/RISC processors
Microcomputers

2-3 Microprocessor & its Programmer's Model Chapter 2

architecture

4-6 Assembly Programming Addressing Modes Chapter 3

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 BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, Pilani
Pilani Campus
Instruction Division

7-16 Assembly Programming Instruction Set & ALP Chapter 4-6, 8

17-19 8086/8088 Hardware Pin Out, Modes of operation, Clocking, Chapter 9

Specifications Buses

20-23 Memory Interface Memory Devices, Address Decoding- Chapter -10

Memory Interface 8086- 80386

24 I/O Interfacing Basic I/O interfacing (I/O mapped I/O Chapter 11.1, 11.2
and Memory mapped I/O) I/O port
address decoding

25-27 Programmable Peripheral 8255 Chapter 11.3

Devices

28-29 Interrupts Types of interrupts, Vector tables, Chapter 12.1, 12.2,

Priority Schemes

30-31 Interrupt Controller 8259 Chapter 12.4

32-34 Programmable Timer 8253/8254 Chapter 11.4

35-36 Converters ADC, DAC Chapter 11.6

37-39 DMA controller Basic Operation, 8237, Shared Bus, Disk Chapter -13
Memory Systems, Video Displays

40-41 System Design Processor based system design Chapter 15

5. Evaluation Scheme :

SL. No Component & Nature Duration Weightage Date Nature

1 Quizzes ---- 40 (13.3%) Continuous Continuous

2 Lab Quiz/Assignments ---- 30 (10%) Continuous Continuous
3 Mid-Semester Test 90 min. 90 (~30%) OB/CB
4 Design Assignment -- 20 (~7%) As per AUGSD

5 Comprehensive Exam 3 hours 120 (40%) 14/05/2020 OB/CB

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 BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, Pilani
Pilani Campus
Instruction Division

6. Chamber Consultation Hour: To be announced in the class

7. Make-up Policy: Make up will be allowed for genuine cases. Prior application should be sent for
seeking the same. No make up for Quiz, Lab.
8. Course Notice: Will be displayed on Nalanda Notice board

Note: A student who scores less than 10% marks(30 marks) will be awarded NC.

Instructor-in-Charge