PROFORMA FOR SUBMITTING

PROPOSAL UNDER
SPECIAL MAN POWER DEVELOPMENT PROGRAM F O R CHIPS TO
SYSTEM DESIGN

1. Institute
a) Name : National Institute of Technology, Nagaland
b) Address : Chumukedima,Dimapur,Nagaland-797103
c) Legal status : Autonomous Institute under Ministry of HRD GoI (Established under NIT Act
2007)

2. Details (including Name, Designation, Department , email, contact no.) of

a) Chief Investigator
Name : Mr. J. Arul Valan
Designation : Assistant Professor
Department : CSE Department, NIT Nagaland
Contact : Telephone: +91-9443109434 (M)
Email : valanmspt@yahoo.co.in

b) Co- Chief Investigator

Name : Dr. Jay Chandra Dhar
Designation : Assistant Professor
Department : ECE Department, NIT Nagaland
Contact : Telephone: +91-9774738567 (M)
Email : jaydhar@gmail.com

3. Broad Objective of the Proposal

(a) Developmental Work - Project

(i) By Participating Institutions (Category- III i.e. Participating Institutions who did not
participated in Special Manpower Development Program Phase-II, excluding New IITs)

We have been assigned with two design activities by Resource Centre which is a part of the
clustered project “Building a prototype of air quality monitoring system based on FPGA/ASIC platform”.
In this regard we have been allotted with the following design activities:
 Design of sensor interfacing circuitry
 Design of DMA Controller for processor

Along with the above mentioned design activities we also have anticipated one individual FPGA
based design project (not part of the clustered project).We propose to build a prototype of a wearable
healthcare monitoring system based on FPGA platform which will be able to measure the heartbeat,
electrodermal activity and along with the temperature and humidity of the human body. A bracelet with
all the required sensors, called Measuring Unit, is placed around the arm of the human body and the
gathered information from sensors is sent to the Base Station, with the help of radio transceivers, where
it will be analyzed, displayed and can be interpreted.

(b) Capacity Building

Table I
Year 1st 2nd 3rd 4th 5th Total
Type IV 30 30 60 60 60 240
Type III ---- 15 15 15 15 60
Type II ---- 15 15 15 15 60
Type I ---- ---- 1 1 1 3

Type I PhD; Type-II M Tech-VLSI; Type-III ME/M Tech with courses in VI SI; Type-IV B E/B Tech
with courses in VLSI
(Note: Both the activities (a) Developmental Work- Project and (b) Capacity Build up are
mandatory for all institutions)
 Developmental Work – Project

4. Title of the Project (Clustered Project): An FPGA/ASIC based Sensor Platform for Monitoring Air Pollutants
Design Activities:
 Design of sensor interfacing circuitry
 Design of DMA Controller for processor

5. Project Details
 Design Activity I : Design of sensor interfacing circuitry
a) Aim and Objective:
The aim of the design activity is to develop a low power technique to interface the sensor data from
the output of ADC to FPGA.

b) Detailed description:
The design activity deals with the development of sensor interfacing module through I2C
communication protocol. In this regard an I2C compatible ADC module will be utilized for serving
the purpose. The interfacing module will be developed to communicate the ADC module to the
FPGA board through I2C which will be able to configure up to 4 conversion channels at 12 bits of
resolution.
An I2C master core will be implemented in FPGA through which output data of the ADC
will be transferred serially to be processed and stored in a memory core and to the LCD display.
The sensor data will also be transferred to a host computer through UART controller core. And for
the proper timing and control of the system a controller core will be implemented.

Fig 1: Basic building block of the proposed design activity Sensor interfacing circuitry

I2C (Inter-Integrated Circuit) is a Bidirectional, Synchronous, Serial, Master Slave bus

protocol. It is typically used for interfacing lower-speed peripheral ICs to processors or
microcontrollers in a short-distance, (intra-board communication). Since, I2C is synchronous
protocol the data is clocked along with the clock signal and the clock signal itself is use to control
the change in data and when the data should be read or write to a particular peripheral device.
Here are some of the features of the I2C-bus:
 Two bus lines are required - serial data line (SDA) and serial clock line (SCL)
 Each device connected to the I2C bus is addressable by a unique address and simple master/slave
relationships exist at all times
 It is a multi-master bus including collision detection and arbitration to prevent data corruption if
two or more masters simultaneously initiate data transfer.
 Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 Kbit/s in the Standard-
mode, up to 400 Kbit/s in the Fast-mode, up to 1 Mbit/s in Fast-mode Plus, or up to 3.4 Mbit/s in
the High-speed mode.
 On-chip filtering rejects spikes on the bus data line to preserve data integrity
In context to our design activity Sensor Interfacing circuitry the I2C bus structure suits perfectly
our objective of low power consumption and data transfer rate requirement. We propose to implement an
I2C master core in Xilinx Artix 7 series FPGA which will communicate with the I2C slave present in the
ADC and the digitalized sensor data will be transferred to the processor.
 Design Activity II : Design of DMA Controller for Processor
a) Aim and Objective:
The aim of the design activity is to develop a programmable Direct Memory Access (DMA)
Controller for the Processor.
b) Detailed description:
The design activity deals with the development of a programmable DMA Controller.
DMA is an I/O technique used for high speed data transfer between and memory and
peripherals. Other I/O techniques like polling based I/O and interrupt driven I/O, data transfer is
relatively slow because each instruction is to be fetched and executed. In DMA technique, the
processor releases the control of the buses to a device called DMA controller. Then, the
controller manages data transfer between the memory and the peripheral under its control by
bypassing the processor.
DMA introduces to important signals HOLD and HLDA
 HOLD - Requesting the use of the address and data buses
 HLDA (Hold Acknowledge) - This indicates the processor is relinquishing control of
the buses.
The DMA controller uses these signals like a peripheral requesting the processor for
control of the buses. The processor communicates with the controller by using the buses and the
control signals. The moment the controller has gained control it acts as processor for data
transfer.
The DMA controller core will then we implemented in Xilinx Artix 7 Series FPGA along
with Micro Blaze processor core for evaluation of its functionalities. An External Memory
module will be interfaced along with an I/O device to the FPGA board for data transfer through
the DMA controller.

Fig 2: Basic building block of the proposed design activity DMA controller
c) Specifications:
Specifications of subsystem/system (as applicable):
1. Sensors Specification
Table II
Temperature and
Parameters CO CO2 NO2
Humidity
NTC (Temp.)
Sensor layer/type Resistive NDIR Resistive
Resistive(Humidity)

Temp: 0-50°C
0.88 – 29.7 350-5000 0.022-0.213
Range Humidity:20-
ppm ppm ppm
90%RH

Supply Voltage 5V 5V 5V 5V

5.5 mW(Avg)
About 400
Power consumption < 28 mW 50 mW 13.75mW (Max.)
mW

Higher Higher Higher Higher

sensitivity is sensitivity is sensitivity is sensitivity is
Sensitivity
preferred (5 preferred preferred preferred
mV/ppm)

Lesser
Lesser is Lesser is
response time Temp:6-30 s
Response time preferred better
is preferred Humidity:6-15 s
(<10 s) (< 30 s)
(near 100 s)

Operating
-2 to -40 °C -2 to 40 °C -2 to -40 °C -2 to -40 °C
Temperature
Humidity 50-80% 50-80% 50-80% 50-80%
Interface Analog Analog Analog Serial Digital
Compatible
Standard Standard Standard Standard
Programmable
MCUs/FPGA MCUs/FPGA MCU/FPGA MCU/FPGA
Boards (CPB)

2. ADC Specifications
Table III
Parameters Specification
Supply Voltage, Vdd 2.7V to 5.5V
Number of Bits 12 ADC with fast conversion time: 1 μs
typical
Channels 4 analog input channels/3 analog input
channels with reference input
Interface I2Ccompatible serial interface supports
standard, fast, and High-speed modes
Power consumption 1.38mW(Fully operational)
Positive reference voltage, Vref+ 2.5V
Type SAR
Clock frequency 3.4 MHz
Operating temperature −40°C to 125°C
3. Processor Design Specification
Table IV
Parameters Specifications
I-V ratings (Voltage/Current)
FPGA Board-5V(External)
FPGA I/O,USB
Ports,Clocks,Flash,PMODS-3.3V,
2A/0.1 to 1.5A
FPGA Core-1.0V,
2A/0.2 to 1.3A
FPGA Auxiliary and Ram-1.8V,
300mA/ 0.05 to 0.15A
Architecture 33,280 Logic Cells
5,200 Slices CLBs
400 Distributed RAM
90 DSP Slices
5 CMT(each with 1MMCM and 1PLL)
1 XADC
5 I/O Banks
250 Max user I/O
Frequency 100 MHz
Internal clock speeds exceeding 450MHz
Memory 100(18kb)Block RAM
50 (36kb)Block RAM
1,800 Max(Kb)
Physical Dimensions 49 x 75.2 mm
I/O Pins 1 XADC
5 I/O Banks
250 Max user I/O

4. External Memory Specifications

Table V
Parameters Specification
Supply Voltage 3.3V
Size 32Mbit non-volatile serial Flash device
(on board)
16Mbit of non-volatile serial Flash memory
(Pmod)
Interface Quad Mode SPI Interface
Speed Normal READ (Serial): 40 MHz clock rate
Quad I/O FAST_READ: 80 MHz clock rate
Or 40 MB/s effective data rate

5. Display Specifications

Table VI
Parameters Specification
Supply Voltage 3.3V
Type and Interface 16×2 character LCD with parallel interface
192 predefined characters including 93
Number of character ASCII characters
Up to 8 user-definable characters
Power Consumption Low power operation
Title of the Project (Individual Project): Development of FPGA based Wearable Healthcare
monitoring system.

Project Details
a) Aim and Objective:
Knowing the limits of a human body can help improve performance and avoid extortion
scenarios. The proposed project aims at developing a low cost prototype of a Wearable
Healthcare Monitoring System. The project will be built to monitor Electrodermal activity and
Heartbeat rate of the human body.
The motivation behind of choosing this project is to facilitate the patients in the remote
locations of northeast regions in getting healthcare services which might not be possible
otherwise due to very low doctor-to-patient ratio.
b) Detailed description:
By examining the electrodermal activity and the hearth beat rate the system will be able to
inform about the wellness of the human body, the data generated from the system can be
utilized to scrutinize various parameters such as anxiety, stress, illness, and ingestion of drugs.
A bracelet with Galvanic Skin Response, Heartbeat Rate along with temperature and
humidity sensors attached to controller called Measuring Unit, is placed around the arm of the
subject. The gathered information from sensors is sent to the Base Station, with the help of radio
transceivers, where in the processing system it will be analysed, displayed and can be
interpreted. A warning system will be built to set an alert signal under any abnormality
circumstances.

Fig. 3 Basic buildings blocks of the proposed Wearable Healthcare Monitoring System. (Measuring Unit)

Fig. 4 Basic buildings blocks of the proposed Wearable Healthcare Monitoring System. (Base Station)

The system is composed of two modules one is named as Base station placed at a secured
location and another as Measuring Unit which is wired with the patient. The Measuring Unit is
equipped with a processor and a high precision ADC which samples the analog data of skin
impedance, heart rate, temperature and humidity of the subject’s body. Then, the digitalized
data will be transmitted via RF module wirelessly for being further processed and analysis.
The Base Station comprises of the processing unit where it will be interfaced with a
memory, display module and along with a computer interface for storage, display and
investigation of the data.
The proposed project has abundant potential for enhancements like adding new
parameters to be measured ECG, Blood pressure, Pulse and Oxygen in blood, EMG etc. The
system can also be extended to have many nodes, this mean it has possibility to monitor a big
number of persons. And also connection to a database to accumulate patients data to see their
variation and person’s evolution for a long time period.
Following are the goals of this project:
In the First Phase we will be designing a prototype in a Microcontroller based environment will all
the proposed functionalities after the successful operation of the system we will be advancing for FPGA
level implantation of the WHMS.
Phase I: Microcontroller level implementation WHMS
Phase II: FPGA level implementation of WHMS

c) Specifications:
Specifications of subsystem/system (as applicable)
1. Sensors Specification
Table VII
Temperature and
Parameters Skin Heart beat
Humidity

Sensor type Impedance Resistive Capacitive

30 – 240
Range 0 to 65279 ohm 0-100%
bpm

Supply Voltage 3.3 V 5V 3.3V

Power Low power Low power Low power

consumption
920nm
(Wavelength )
Sensitivity 1100nm Higher sensitivity is Higher sensitivity is
(Spectral preferred preferred
sensitivity)

Response time 0.1 to 0.5 sec 8-10 sec 8 sec

Operating
40 to 80°C -40 to 80°C -40 to125°C
Temperature
Humidity 50-80% 50-80% 100%
Interface Analog Analog Analog
Compatible
Standard Standard Standard
Programmable
MCUs/FPGA MCUs/FPGA MCU/FPGA
Boards (CPB)

2. ADC Specification
Table VIII
Parameters Specification
Supply Voltage, Vdd 3V to 5.25V
Number of Bits 24-bit
4 differential or 8 pseudo differential input
Channels
channels
Interface 3-wire serial SPI, QSPI
Power consumption 13.95mW(Fully operational)
Positive reference voltage, Vref+ 2.5V
Type sigma-delta (Σ-Δ)
Clock frequency 4.92 MHz
Operating temperature −40°C to +150°C
3. Processor Design Specification
Table IX
Parameters Specifications
I-V ratings (Voltage/Current)
FPGA Board-12V(External)
FPGA I/O,USB
Ports,Clocks,Flash,PMODS-3.3V,2A/0.1
to 1.5A
FPGA Core-1.0V,
2A/0.2 to 1.3A
FPGA Auxiliary and Ram-1.8V,
300mA/ 0.05 to 0.15A
Architecture 215,360 Logic Cells
33,650 Slices CLBs
2,888 Distributed RAM
740 DSP Slices
10 CMT(each with 1MMCM and 1PLL)
1 XADC
10 I/O Banks
500 Max user I/O
Frequency 33.333MHz (PS)
100 MHz (PL)
Memory 18Kb(730) Block RAM
36Kb(365)Block RAM
13,140 Max(Kb)
Physical Dimensions 15 x 15 mm
I/O Pins 1 XADC
7 I/O Banks
7 Max user I/O

4. RF Module Specification
Table X
Parameters Specification
Supply voltage 3.3V
Frequency 2.4GHz
Network Standard Supports Zigbee and MiWi protocols
Date rate Up to 650kbps
Interface 4-wire SPI
Modulation For low power density
Transmitting Power 60mW
Receiver Sensitivity To have good noise rejection property
Distance 90 meter
Antenna Type Whip antenna

5. External Peripheral SD card Slot Specification

Table XI
Parameters Specification
Supply Voltage 3.3V
Number of pins 12
Interface SPI Interface
6. External SD Card Memory Module
Table XII
Parameters Specification
Supply Voltage 2.7V to 3.6V
Size 1GB / 2GB
Interface SPI mode
Speed Default Mode: Variable clock rate 0-
25MHz, up to 12.5MB/sec
High Speed Mode : Variable clock rate 0-
50MHz, up to 25MB/sec

7. Display Specifications
Table XIII
Parameters Specification
Supply Voltage 3.3V
Type and Interface 16×2 character LCD with parallel interface
192 predefined characters including 93
Number of character ASCII characters
Up to 8 user-definable characters
Power Consumption Low power operation
d. Duration: Five Years
e. Deliverables and Outcomes in physical terms (i.e. development of Working Prototype of Systems
/Sub-Systems I SoC/ASIC/FPGA based board design, I Ps, Publications etc. This should be in line
with the MoU signed by the institute)
 Accomplishment of the design activities allocated by RC under the clustered project AQMS.
 Visible contributions to clustered project AQMS with the support from all PI’s and RC.
 Accomplishment of the FPGA based board level design project WHMS committed by the PI.
 Practically testing and collection of data from patients.
 Enabling a wide research area on the field of wearable electronics and IoT.
 Training of students leading towards M. Tech. & Ph.D.
 Engineers and technicians will be trained in the latest technologies in many fields like sensor data
acquisition calibration & testing, FPGA/ASIC design using EDA tools etc.
 Visible contribution to a national project at various research centers – CEERI Pilani, CGCRI Kolkata,
CDAC-Bangalore, IISc Bangalore, SCL Chandigarh with due assistance from MeitY.
 Knowledge and expertise transfer due to close interaction/visit with international scientists at research
centers, industries and reputed educational institutes.

f. Details & justification of the h/w & s/w proposed to be procured (ONLY for and
specific to Development of System/System on Chip etc.)

Table XIV: Hardware resources

Sl. No. Item Description Quantity

1. Gas sensor modules 6
2. Healthcare sensor modules 4
3. Temp & humidity sensor 2
module
4. Pmod AD2 2
5. Pmod AD5 2
6. Arduino UNO Board 1
7. Arduino NANO Board 1
8. NI myRIO 1
9. Basys 3 boards + accessories 10
10. Pmod KYPD 10
11. Pmod CLP 10
12. Analog Discover kit 3
13. Nexys 4 board 4
14. Zed board 2
15. Pmod RF2 2
16. XBee Module 2
17 XBee Sheild 2
18. PmodSD(Full Size SDcard Slot) 1
19. PmodSF(External ROM) 1
20. Power Supplies 2
 Table XV: Software installation status

Sl. No. Software Status

1. Cadence Installation complete
2. Mentor Graphics Installation in process
3. Synopsys Installation complete
4. Xilinx VIVADO Installation in process
5. Xilinx SDK Installation in process

g. Infrastructure and other facilities, including equipment, available at the institute for
undertaking this project:
i. List of major equipment along with model numbers, specifications etc.
We will be utilizing the FPGA boards and EDA tools available at NIT Nagaland
ii. Existing manpower and other personnel with names available for the project on full-time basis.
Nil

h. Facilities available elsewhere which could be made use of for the project:
IIT Guwahati

i. Nature of Documents for Transfer of Technology (ToT)

i. Project report
ii. Journal/Conference papers
iii. Any other technical document as per request

j. Summary of similar work being done elsewhere in the country

The clustered project work AQMS is initiated by the RC (IIT Guwahati) along with all the PI’s with specific
design task undertaken. In addition to that by the initiative of RC, resources from institutes like CGCRI Kolkata,
CEERI Pilani, IISc Bangalore, BARC and SCL Chandigarh is sought for the project.
And in context to the FPGA board level project WHMS is proposed individual project by the PI, with the
assistance RC it will also sought for Research Institutes and Industries where similar work is going on.

k. Impact Assessment on industry/students/research community/subject area and other

stakeholders. What will happen if this project activity is not undertaken?
There are many start-up companies coming up in India in the field of sensor networks and IoT.
Circuits/Algorithms/Architectures that will be developed in this project are very useful for these startup
companies. Since environmental monitoring and health monitoring is a multi-disciplinary research, often
research communities from non-electrical/computer-science background find it difficult to build the complete
environmental and health monitoring system. Outcome of the current project is very useful for research
communities as it are the most updated and latest technology and has potential of abundant research
opportunity.

l. How does the proposal help in value addition and gives recognition to your
Department/Institute?
Both the project has a significant social importance. It helps in improving the quality of life in the North-
eastern region of India and there by increases the reputation of NIT Nagaland as an Institute of National
Importance.

m. SWOT analysis for the proposed project which you intend to undertake? What are the
strengths on which this project is proposed?
Strengths:
NIT Nagaland is been included as a part of SMDP-C2SD program and it is gaining a valuable experience in
all areas of VLSI including circuit simulations using the CAD tools, working with FPGA boards. We will also
be taking the assistance of many post-graduate students in the proposed project. We have a good resource of
hardware and EDA tools available presently in our institute.
 Weaknesses:
The present projects committed in cluster and individually targets a system design and chip tape-out. This
research and development could lead to a product. However, in order to develop a compact product which can
be readily employed for environmental and health monitoring requires many other relevant considerations. For
example, integration of additional building blocks like network controllers and sensors will be one aspect.
Mechanical design aspects of the product and marketing feasibility studies etc. are other important issues to be
considered to bring the product to the market.
Opportunities:
We are working on a topical issue which is of national importance. The Ministry of Environment and
Forests, Government of India and state governments along with health departments will be interested in this
project as these projects directly links to the environmental and health issues. Opportunities have increased due
to the public awareness and many initiatives from the environmental groups, NGO’s and healthcare services.
Current project targets the development of integrated circuits and systems in the specified area and therefore
provides enormous opportunities.
Threats:
In India, environmental health is perceived merely as a bureaucratic requirement limited to the selection of
the project or pollution control technology to be adopted at the time of starting an industry. Lack of good quality
environmental data and improper implementation of the environmental health projects are further hampering the
research in this field. As of now, we are not aware of any complete Indigenous prototype being implemented.
Lack of standards related to the environmental monitoring systems is another issue. In the absence of a standard,
industries will not come forward to build a product, fearing the marketability.
In healthcare sector India has a reasonable amount of healthcare services and facilities in terms of treatment
but it is restricted only to the developed cities and towns. Healthcare monitoring and prevention is still in
developing phase and in case of the remote locations its poorest cause of its expensiveness and lack of
knowledge among the population.

n. Expected manpower to be generated with expertise in System / SoC Development (ONLY for and
specific to Development of System/System on Chip etc)
As mentioned in Table I.

o. Name of other organizations jointly participating in the project (includin g foreign collaboration):
IIT Guwahati
NIT Agartala
NIT Arunachal
NIT Meghalaya
NIT Mizoram
NIT Manipur

p. Name of experts whom the Chief Investigator would invite to join the project team as full
time/part time consultant (foreign collaboration / industry experts)
Dr. Roy P. Paily, Professor, Department of Electronics and Electrical Engineering, IIT Guwahati

q. Agency with which link up is established/proposed(Details may be given as a pplicable)

N/A

r. Likely End User(s) (Letter of interest / broad specifications to be obtained from end users -
ONLY for and specific to Development of System / System on Chip etc.)
 Air quality monitoring in residential complex and offices
 Air quality monitoring in townships near to industrial zone.
 Pollution monitoring in cities
 Pollution monitoring in high traffic junctions.
 A low cost Wearable healthcare monitoring system which can be used in remote village areas
 Self-analysis and continuous assessment of health for elderly
 Automated suggestion/preventions healthcare
 Researchers from other areas of engineering, who are working in the area of environmental monitoring.
 Start-up companies in the field of wireless sensor area networks and Embedded Systems
s. Year-wise break-up of physical achievements with specific intermediate milestones (in terms of
aims and objectives)/PERT Chart. BAR Chart (Separate Sheet)
 The infrastructure and manpower development will be first activity. The existing hardware and software
infrastructure and skills of UG and PG students available at NIT Nagaland will be made use for the project
 Preliminary Specification of sensors and system sub block for both projects individual an clustered.
 Finalization of Specification
 Subsystem level Simulation
 Design of individual circuit blocks and integration of these blocks will be the major activity.
 The processing and controlling of sensor data will be carried out in FPGA. The computer will be replaced by
the FPGA board.
 System level Integration
 The test infrastructure development and testing of the prototype will be carried out at the final stage.
 Milestones (Sub-block simulations, sub-block PCB/FPGA, Prototype test)
 The final technical report would be provided to MeitY. The work would be presented in relevant conferences
and published in reputed journals.
 TABLE XVI: Detailed PERT Chart (AQMS Clustered Project) 1st year activities:
Schedule of Consultancy: (Budgeted under HRD Collaboration Meeting) Post-1st year activities:
Sl. No. Task Months after starting
6 12 18 24 30 36 42 48 54 60
1. Development of working prototype:
a. Design Activity allotted (Clustered project)
2. Networked PhD Program (will go up to 9 years)

3. Knowledge Exchange Program

a. Virtual conferences based meetings Once every half-yearly
b. RC members trip to PIs for assessment of
work (in person) For activities (a) to (c)
c. Visit to R & D institutes like CEERI Pilani,
CGCRI Kolkata, IISc Bangalore, CDAC Pune,
SCL Chandigarh
d. Instruction Enhance Programs for faculty of Once yearly
Participating Institutions
e. Work shop / symposium For activities (d) & (e)
f. Mentoring PhDs of both RC and PIs
g. Mentoring work progress of PIs
h. Publications of papers in Journals / For activities (f) to (h)
conferences
i. Patenting the Innovative / Research
j. Bi-lateral Collaborative Development
k. Development of Model Syllabus in SoC
/System Development
l. Adoption of Model Syllabus in SoC/System
Development
4. Establishment / up gradation of VLSI
Design Laboratory
a. Procurement of Hardware / Software / EDA
Tools / Teleconferencing equipment /
Equipment for Prototype & Test facility/
Equipment for Design
Repository
b. Installation of the procured tools
c. Specialized Manpower generation
d. Web-site development & maintenance
 TABLE XVII: Detailed PERT Chart(Individual FPGA Board level Project )
Schedule of Consultancy: (Budgeted under HRD Collaboration Meeting)

Sl. No. Task Months after starting

6 12 18 24 30 36 42 48 54 60
1. Development of working prototype:
a. FPGA board level implementation (Individual
project).
2. Networked PhD Program (will go up to 9 years)

3. Knowledge Exchange Program

a. Virtual conferences based meetings Once every half-yearly
b. RC members trip to PIs for assessment of
work (in person) For activities (a) to (c)
c. Visit to R & D institutes like CEERI Pilani,
CGCRI Kolkata, IISc Bangalore, CDAC Pune,
SCL Chandigarh
d. Instruction Enhance Programs for faculty of Once yearly
Participating Institutions
e. Work shop / symposium For activities (d) & (e)
f. Mentoring PhDs of both RC and PIs
g. Mentoring work progress of PIs
h. Publications of papers in Journals / For activities (f) to (h)
conferences
i. Patenting the Innovative / Research
j. Bi-lateral Collaborative Development
k. Development of Model Syllabus in SoC
/System Development
l. Adoption of Model Syllabus in SoC/System
Development
4. Establishment / up gradation of VLSI
Design Laboratory
a. Procurement of Hardware / Software / EDA
Tools / Teleconferencing equipment /
Equipment for Prototype & Test facility/
Equipment for Design
Repository
b. Installation of the procured tools
c. Specialized Manpower generation
d. Web-site development & maintenance
 t. Budget Outlay, Manpower Requirement, Details of H/w & S/w proposed to be procured (only for and specific
to Development of System / System on Chip etc.):
Table XVIII: Budget Outlay
Budget Budget
Budget Budget Budget
Fourth fifth Total
Equipment/Activity First Year Second Year Third Year
Year Year (in lacs)
(in lacs) (in lacs) (in lacs)
(in lacs) (in lacs)
1 Capital Equipment 45.00 0.000 0.00 0.00 0.00 45.0
2 Manpower 11.28 12.40 13.60 14.86 16.20 68.36
3 Consumables/Chip 1.20 1.20 1.20 1.20 1.20 6.00
4 Travel and Training 1.00 1.00 1.00 1.00 1.00 5.00
5 Contingency 1.00 1.000 1.000 1.00 1.00 5.000
6 IEP 0 6 0 0 0 6.00
7 Institute Overhead (15%) 2.10 3.14 2.45 2.67 2.92 13.28
TOTAL 61.58 24.74 19.25 20.73 22.32 148.64

(i) Contribution of Project Implementing/& other Organization in Total Budget Outlay

G rand Total : Rs. 148.64 Lacs
(ii) MeitY Contribution: Rs. 148,64,000/-

Table-XIX: Manpower Details (ONLY for and specific to Development of System I System on Chip etc)
Sl. No. Designation Monthly Budget First Budget Budget Budget Budget
(No. of position) Emoluments Year Second Third Year Fourth fifth Year
Year Year

1 Project Assistant 20,000/- 2,40,000 2,64,000 2,90,400 3,19,440 3,51,384

(1) +10%
increment
2 Lab Engineer 34,000/- 4,08,000 4,48,800 4,93,680 5,43,050 5,97,350
(1) +10%
increment

3 Guest/Temporary 40,000/- 4,80,000 5,28,000 5,76,000 6,24,000 6,72,000

Lecturer +10%
(1) increment

TOTAL 68,36,104

1. Scientifi c/Technical Nil

2. Grade lower than ( I ) Nil
3. Skilled workers Nil
4. Unskilled workers Nil

Total: 68, 36,104