MOS1 Example Report

MOS1 EXAMPLE 1:
Id/Vgs and Threshold Voltage

Extraction:
The above example simulating an Id/Vgs curve and extracting threshold voltage and other
SPICE parameters. This example shows the following demonstrations:
 Process simulation of a MOS transistor in Athena

 Process parameter extraction (eg. oxide thicknesses)
 Autointerface between Athena and Atlas
 Id/Vgs curve generation with Vds=0.1V
 Parameter extraction for Vt, linear gain (beta) and mobility rolloff (theta)
The process simulation in SSuprem 4 follows a standard LDD MOS process. The polysilicon
gate is formed by a simple geometrical etch. Before this point the simulation is essentially one
dimensional and hence is run in Athena's 1D mode.
Electrodes are defined at the end of the process simulation. Metal is deposited and patterned.
The extract statement at the end of the file is used to calculate the oxide thickness at that point.
The value returned here may be used as an optimization target for calibration. For the use of the
Optimizer function refer to the instruction manual. This value will be added to a file in the
current working directory called results.final.
The grid used in this example is defined quite tightly. However the statement init ...
spac.mult=3 relaxes the mesh in X and Y directions by a factor of three.
A more typical mesh for MOS simulation can be obtained by setting spac.mult=1.
The contact statement is used to define the workfunction of the gate electrodes, while the
interface statement defines the fixed charge at the silicon/oxide interface.
CVT statement sets a general purpose mobility model including concentration, temperature,
parallel field and transverse field dependence.
The statement solve init is used to solve the thermal equilibrium case. After this the voltages can
be ramped.
The statement method trap enables Atlas to cut user-defined voltage steps in half if convergence
is not obtained. This is a highly recommended option and is turned on by default.
The sequence of solve statements is set to ramp the gate bias with the drain voltage at 0.1V.
Solutions are obtained at 0.25V intervals up to 3.0V. All terminal characteristics are saved to the
file mos1ex02_1.log as specified in the log statement.
The name parameter specifies only a user-defined label. The routines are not hard-coded to these
names.
The second extract statement measures the gain (or Beta). This is defined as the value of the
steepest slope to the Id/Vgs curve divided by the drain voltage. The final extraction is for the
SPICE level 3 mobility roll-off parameter (or Theta). This syntax shows the use of the syntax:
$"nvt" and $"nbeta" . This tells DeckBuild to substitute the previously extracted values of
threshold and beta into this places in the equation.
To load and run this example, select the Loadbutton in DeckBuild > Examples. This will copy
the input file and any support files to your current working directory. Select the Run button in
DeckBuild to execute the example.
MOS1 EXAMPLE 2:
Family of Id/Vds Curve:
This example demonstrates the following characteristics:

 Id/Vds curve generation with Vgs=1.1, 2.2 and 3.3V
 IV Curve parameter extraction for Idmax and saturation slope
The same steps are used for this example as the steps used in the first example. The maximum
drive current and saturation slope are extracted. To demonstrate simple functionality as depicted
in the first example no advanced features are used. The process simulation, process
parameter extraction and electrode definition for this example are the same as the first
example.
A more advanced sequence of solve statements is used for this example. Three Id/Vds curves are
required at different gate voltages. The first part of the solve sequence sets up the initial point of
the three curves. For each of the the three gate voltages a solution with Vds=0.0 is simulated and
the results saved to a solution file.
Then each of these three solution files is loaded in turn into Atlas. A log file is opened and the
ramp of Vds is set. When a file is loaded the voltages in Atlas are reset to the values in the file.
The extract function is used to measure the peak current and the saturation slope. From the
shape of the Id/Vds curves the saturation slope is clearly the minimum value of the gradient
along the curve. Finally the three Id/Vds curves are overlaid in TonyPlot.
MOS1 EXAMPLE 3:
Sub-Threshold Slope Extraction:
This is an example simulating an Id/Vgs curve and extracting sub-threshold slope. This example
demonstrates the following characteristics:

 Simple Id/Vgs curve generation with Vds=0.1V
 Parameter extraction for Sub-Threshold Slope
The process simulation, process parameter extraction and electrode definition for this example
are exactly as described in the first example in this section. The only difference is that the gate
voltage is ramped from zero to 1.0V only in 0.1V steps.
The extract statement used in this example measures the sub-threshold slope of the MOSFET.
The operators log10(), slope() and curve() are used by the extract statement to specify the
reciprocal of the steepest slope to the curve of Vgs vs. log(Id).
The operator log() specifies the function for natural logarithm.

MOS1 EXAMPLE 4:
DIBL Extraction:
This example simulates two Id/Vgs curves at different drain biases and extracting the DIBL
parameter. This example demonstrates the following characteristics:

 Ramp of drain voltage
 Parameter extraction for the DIBL parameter (Drain Induced Barrier Lowering)
The same procedure is used in this example as used in the first example. The only difference is
the use of the syntax compl=1.1e-7 cname=drain . This sets a compliance limit on the drain
current.
All results from the first Id/Vgs curve are saved to the file specified by the first log statement. In
Atlas, the only way to stop the IV points being saved is either to specify another LOG statement
or to use log off or exit the simulator. Here, log off is used to stop the output from the drain
voltage ramp being saved to the Id/Vgs logfile specified previously.
The second 'solve init' statement resets all applied voltages to zero. Then the drain is ramped to
3.0V and the gate ramp with compliance is repeated.
After each gate ramp the threshold voltage was extracted using a different syntax than the
NMOS threshold voltage example described earlier in this section. In this example the threshold
is determined by looking for the voltage where the drain current reaches a user-defined value.
The syntax x.val from curve (x,y) where y.val=<number> is used. At large drain biases this
method is preferred for threshold extraction over the steepest slope approach. The search value
of 0.1uA/um of current is typical for channel lengths around 1um. These thresholds are stored as
values nvt1 and nvt2 in DeckBuild. The final extract statement is used to obtain the DIBL
parameter. It is the difference in threshold voltage divided by the difference in the drain bias.
MOS1 EXAMPLE 5:
Body Effect Extraction:
This is a basic MOS Athena to Atlas interface example simulating two Id/Vgs curves at different
substrate biases and extracting the body effect (gamma) parameter. This example demonstrates
the following characteristics:

 Simple Id/Vgs curve generation with Vbs=0.0V
 Simple Id/Vgs curve generation with Vbs=-1.0V
 Parameter extraction for body effect
are exactly as described in the first example in this section.
The two threshold voltages that are measured by using extract function in example 4 derived
earlier are used to derive the body effect parameter taking the value of fi as 0.6V.The whole
example is very similar in syntax to the DIBL parameter extraction example described
previously in this section. The difference is that different substrate biases are used instead of
different drain biases.
MOS1 EXAMPLE 6:
Substrate and Gate Current
This example demonstrates:

 Autointerface between Athena and DevEdit
 Remeshing using DevEdit
 Autointerface between DevEdit and Atlas
 Solution for a Vgs ramp with Vds=3.3V
 Parameter extraction for maximum gate and substrate currents
The grid requirements for Atlas simulation of impact ionization effects are more stringent than
for the low electric field cases described earlier. DevEdit is used to remesh the Athena structure
before proceeding to Atlas.
The imp.refine commands specify regrids on impurities. Here a regrid on net doping is
performed. The constr.mesh command defines the base mesh. The refine commands specify
mesh refinements inside boxes specified by the coordinates in each statement.
The solution of the energy balance equations for electrons is specified by the parameter hcte.el
The parameter hei specifies the hot carrier injection model, which gives the gate current.
The equivalent hcte.ho and hhi exist for holes but is not required in NMOS simulation.
MOS1 EXAMPLE 7:
Breakdown Voltage Extraction:
This is an Athena/DevEdit/Atlas interface example simulating the breakdown voltage of an
NMOS transistor. This example demonstrates:

 Solution for a Vds ramp with Vgs=0.0V to get breakdown
The same DevEdit is used to remesh the Athena structure before proceeding to Atlas. The
remeshing commands are described in the previous example in this section. The parameter
setting method climit=1e-4 is also recommended in cases where the mesh is not as tight as the
one used here.
The sequence of SOLVE statements shows a ramp in drain voltage. Small steps are taken at first,
but the main simulation is done in 0.5V steps. A compliance limit of 5.0e 8A/um is set on the
drain. Compliance limits are useful in breakdown simulations to stop the simulation once the
breakdown point is reached.
The extract syntax used to measure the breakdown voltage is of the current search type. This is
preferred over the simple max(v."drain") syntax that could be used as it gives more consistent
results.
MOS1 EXAMPLE 8:
Id/Vgs and Threshold Voltage
Extraction:
This is a basic MOS Athena to Atlas interface example simulating an Id/Vgs curve and
extracting threshold voltage and other SPICE parameters.
The unique feature of this example is the IV data simulated and the extraction syntax used. The
model, interface and contact statements in Atlas are also as in the previous example.
The name parameter specifies a user-defined label. The routines are not hard-coded to these
names.
The sequence of SOLVE statements is set to ramp the gate bias with the drain voltage at -0.1V.
Solutions are obtained at -0.25V intervals up to -3.0V. All terminal characteristics are saved to
the file mos1ex02_1.log as specified in the LOG statement.
The extract statement at the end of the file are used to measure the threshold voltage and other
SPICE parameters.
MOS1 EXAMPLE 9:
Family of Id/Vds Curves:
This example demonstrates:

 Id/Vds curve generation with Vgs=-1.1, -2.2 and -3.3V
 IV Curve parameter extraction for Idmax and saturation slope
are exactly as described in the first PMOS example in this section. The maximum drive current
and saturation slope are extracted.
A more advanced sequence of solve statements is used for this example. Three Id/Vds curves are
required at different gate voltages.
The first part of the solve sequence sets up the initial point of the three curves. For each of the
three gate voltages a solution with Vds=0.0 is simulated.
At the end of the simulation, extract is used to measure the peak current and the saturation slope.
From the shape of the Id/Vds curves the saturation slope is clearly the minimum value of the
gradient along the curve as long as the absolute values of current and voltage are taken. Finally
the three Id/Vds curves are overlaid in TonyPlot.
MOS1 EXAMPLE 10:
Sub-Threshold Slope Extraction
In Atlas the same sequence of statements is used as in the first example in this section. The only
difference is that the gate voltage is ramped from zero to -1.0V only in -0.1V steps.
The extract statement used in this example measures the sub-threshold slope of the MOSFET.
The syntax uses the operators log10(), slope() and curve() to specify the reciprocal of the steepest
slope to the curve of Vgs vs. log(Id). Note that the operator log10() is needed here. The operator
log() specifies the function for the natural logarithm. It is obviously necessary to take the
absolute value of Id before the log10() operator is used.
MOS1 EXAMPLE 11:
This is a basic MOS Athena to Atlas interface example simulating two Id/Vgs curves at different
drain biases and extracting the drain-induced barrier lowering (DIBL) parameter. This example
demonstrates:

 Simple Id/Vgs curve generation with Vds=-0.1V
 Simple Id/Vgs curve generation with Vds=-3.0V
 Parameter extraction for the DIBL parameter
In Atlas, the models, interface and contact statements are also the same as in the first example.
The extraction of the first Id/Vgs curve is very similar to the previous threshold voltage
extraction example.
One difference is the use of the syntax compl=1.1e-7 cname=drain . This sets a compliance
limit on the drain current. Although the SOLVE statement calls for a ramp in gate voltage from
zero to -1.5V, once the trigger current specified by compl is exceeded on the electrode specified
by cname then the gate voltage ramp will step and Atlas will execute the next line of syntax.
Note that the compliance value does not need to be signed. A current more negative than -1.1e-7
will also trigger the compliance limit. Compliances are more commonly used in breakdown
simulations but can be used in this way to stop voltage ramps once the area of interest is passed.
The second 'solve init' statement resets all applied voltages to zero. Then the drain is ramped to -
3.0V and the gate ramp with compliance is repeated.
After each gate ramp, the threshold voltage was extracted using a different syntax than the
PMOS threshold voltage example described earlier in this section. In this example the threshold
is determined by looking for the voltage where the drain current reaches a user-defined value.
The syntax x.val from curve (x,y) where y.val=<number> is used. At large drain biases this
method is preferred for threshold extraction over the steepest slope approach. The search value
of 0.1uA/um of current is typical for channel lengths around 1um. These thresholds are stored as
values pvt1 and pvt2 in DeckBuild. The final extract statement is used to obtain the DIBL
parameter. It is the difference in threshold voltage divided by the difference in the drain bias.
MOS1 EXAMPLE 12:
In Atlas the whole example is very similar in syntax to the DIBL parameter extraction example
described previously in this section. The difference is that different substrate biases are used
instead of different drain biases.
Two threshold voltages are measured using the extract syntax described in the DIBL extraction
example. The body effect parameter is derived from the threshold voltages using the standard
formula assuming 0.6V for phi.
MOS1 EXAMPLE 13:
EXPLANATION:
This is a MOS Athena/DevEdit/Atlas interface example simulating substrate and gate current
versus gate bias using energy balance and impact ionization models. This example demonstrates:

 Solution for a Vgs ramp with Vds=-3.3V
 Parameter extraction for maximum gate and substrate currents
The grid requirements for Atlas simulation of impact ionization effects are more stringent than
for the low electric field cases described earlier. DevEdit is used to remesh the Athena structure
before proceeding to Atlas. DevEdit has two modes. The graphical mode allows users to draw
and interactively edit regions and impurities. The batch mode used here executes structure and
mesh commands similar to these. The syntax used by DevEdit is described in the DevEdit
manual. It can be constructed from the DeckBuild Command menu or most commonly mesh
edits made during a graphical session can be saved as a 'command file' from the SAVE menu of
DevEdit.
The imp.refine commands specify regrids on impurities. Here a regrid on net doping is
performed. The constr.mesh command defines the base mesh. The refine commands specify
mesh refinements inside boxes specified by the coordinates in each statement.
The Atlas simulation contains similar syntax to the simple examples described earlier in this
section. The solution of the energy balance equations for holes is specified by the parameter
hcte.ho . The parameter hhi specifies the hot carrier injection model, which gives the gate
current. The equivalent hcte.el and hei exist for electrons but are not required in PMOS
simulation.
The impact ionization model is selected on the impact statement. The parameter lrel.ho sets the
relaxation time for holes in this model. Although the hhi model is directly responsible for the
gate current, there is no 'special' model required to simulate substrate current. Running this
sweep of gate voltage with a high drain bias and including impact ionization and energy balance
supplies all the necessary physics. The substrate current can simply be plotted from the log file in
a similar manner to drain current. No special extraction of substrate current is needed.
The extract statements used in this run extract the peak value and position of the substrate and
gate currents. The value of the peak current is measured first. This result is then used in a current
search to find the gate voltage where this current is measured.
MOS1 EXAMPLE 14:
Breakdown Voltage Extraction:
This is an Athena/DevEdit/Atlas interface example simulating the breakdown voltage of a PMOS
transistor. This example demonstrates:

 Solution for a Vds ramp with Vgs=0.0V to get breakdown
MOS1 EXAMPLE 15:
Gate Length Scaling:
This is an Athena/Atlas interface example similar to the first example in this section. It
demonstrates the setting of gate length through parameter substitution.
In this example an NMOS transistors length is defined with a set statement around the poly etch
stage in the simulation. The set statement defines a variable used in a subsequent stretch
statement to define the half length of the transistor.
Importantly, the variable $cd is also used to place the name of the drain electrode in the
subsequent electrode statement. This simplifies the position definition of the drain electrode.
The use of the right statement in the stretch command makes sure that the coordinate system of
the stretched device remains unchanged from the original making sure that the left hand side of
the structure is in the same place as before. Both right|left flags are available.
ADITYA RANJAN NAYAK
REGD NO.-1541016238
BRANCH-ECE
SECTION-E

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MOS1 EXAMPLE 1:

Id/Vgs and Threshold Voltage

 Process simulation of a MOS transistor in Athena

 Process simulation of a MOS transistor in Athena

 Process simulation of a MOS transistor in Athena

The operator log() specifies the function for natural logarithm.

 Process simulation of a MOS transistor in Athena

 Process simulation of a MOS transistor in Athena

 Process simulation of a MOS transistor in Athena

 Process simulation of a MOS transistor in Athena

 Process simulation of a MOS transistor in Athena

 Process simulation of a MOS transistor in Athena

 Process simulation of a MOS transistor in Athena

 Process simulation of a MOS transistor in Athena

ADITYA RANJAN NAYAK

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