EC6202D

Analog Integrated Circuit Design

Course Project
Operational Transconductance Amplifier

29th November 2019

1 Aim
To design a single ended output operational amplifier/ operational transconductance amplifier
with a supply voltage of 1.8V to drive a load capacitance of 10pF. The amplifier should meet
the following specifications:
Parameters Specifications
UGB > 100M Hz
Slew Rate > 20V /µs
Phase Margin > 60◦
Also, to characterize the op-amp parameters such as DC gain, CMRR, PSRR, power consump-
tion, input offset voltage, expected chip area, harmonic distortion etc. In addition, simulate the
opamp in unity-gain feedback and observe the frequency domain and transient responses.

2 Introduction
Operational amplifiers are the heart and soul of analog circuits. Operational amplifiers have
very high open loop gain, therefore when applied in feedback, the closed loop gain is independent
of gain of op-amp. Unbuffered operational amplifiers are better described as trans-conductance
amplifiers. The striking feature about op-amp is the fact that when operated in negative
feedback, the operation of the op-amp is almost independent its internal circuitry. Hence in
most cases, the op-amp is designed to be used with external feedback, where the feedback
circuitry is generally made of capacitors and resistors. In short op-amp is a high gain amplifier
with differential input and usually single ended output.

2.1 Two Stage CMOS Op-amp

Two stage op-amp ia a very popular CMOS op-amp architecture for its simplicity yet robust
implementation. It can provide high gain and high output swing. This classical architecture also
helps to understand many important design concepts which can be directly used in other high
level designs. Two stage CMOS op-amps usually consists of an NMOS differential input stage
and PMOS current mirror as load. The output from this stage is given as input to common
source amplifier which acts as the second stage. Since there are multiple poles in the system,

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 VDD VDD VDD

M3 M4
M5
CC
IS
RZ
CL
V IN- M1 M2 VIN+

M8 M6
M0

Figure 1: Two stage CMOS op-amp architecture

this architecture has a tendency for oscillation. Hence proper compensation techniques need to
be used. A compensation capacitance and nulling resistor are used to increase the the overall
stability of this op-amp.

3 Op-amp parameters
3.1 DC Gain
Theoretically, the DC gain of an op-amp is the exceedingly high gain which is obtained when
the op-amp is not connected in a feedback mode. Ideally the open loop gain of an op-amp is
infinity while in practice, the maximal open loop gain is around 105 . The open loop gain at a
fixed frequency is given by the equation.
Vout
AOL = (1)
V −V− +

where AOL is the open loop gain of the op-amp, Vout is the output voltage and V + − V − is the
input voltage difference that is applied.

3.1.1 Effect on closed loop gain

The gain in a configuration where the op-amp is connected in feedback mode is referred as
closed loop gain. The independence of the closed loop gain on the internal circuitry of op-amp
is directly proportional to the open loop gain, that is, the higher the open loop gain, lesser is
the dependence of the closed loop gain on the internal circuitry of the op-amp.
For example, let R1 and R2 be the input impedance and the impedance in feedback of an
inverting amplifier. The closed loop gain (say ACL ) of such an op-amp when open loop gain is
not considered is given by
−R2
ACL = (2)
R1
However, with the use of open-loop gain, the equation (2) becomes:

R2
R1
ACL = 1 R2
(3)
1+ AOL (1 + R1 )

It can be observed from (3) that, the higher the value of open loop gain, the better (3) can be
approximated to (2). Thus, when operating in feedback mode, a high open loop gain is essential
for an op-amp for it’s characteristics to be independent of the internal circuitry of op-amp.

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3.2 Frequency Response
Frequency response is the spectral response obtained for the output of a system with respect
to input which act as stimulus to the system. Normally, the output to input ac gain (in dB)
and output to input phase (in degrees) of a system is plotted with respect to frequency. If a
sine wave is applied as stimulus to a LTI system, the system will process the signal and eject
an output with the same frequency with a certain magnitude and with a phase difference with
the input stimulus. In simple terms, this is the frequency response.

3.3 Unity gain Bandwidth (UGB)

Normally for an op-amp, the gain is constant till a certain frequency beyond which gain starts
decreasing. The unity gain bandwidth (which is often abbreviated as UGB) is the maximum
frequency up-to which the op-amp can produce a gain greater than 1. The unity gain bandwidth
is also known as transition frequency because it is at this frequency that the gain changes to
< 1 from a gain > 1. In other words, the unity gain bandwidth of an op-amp is the maximum
frequency at which an op-amp will not attenuate the input signal.

3.4 Phase Margin

Phase margin is a measure of stability of the system. It’s the amount of phase which can be
tolerated before which the system oscillates. Mathematically it’s measured as the difference
between 180◦ and the absolute value of lagging phase, calculated at the frequency where gain
of system is unity. A lower phase margin indicates that the system has higher tendency to
oscillates and hence instability. A phase margin greater than 60◦ is good while larger phase
margins lead to sluggish responses.

3.5 Slew Rate

Slew rate of an electronic circuit is defined as the maximum rate of change of the output. It is
usually defined in V/µs. Mathematically it’s defined as

|dvout|
SR = max (4)
|dt|
For a two stage op-amp, slew rate is defined as
It
SR = (5)
Cc
where It is the tail current and Cc is the compensation capacitance. Slewing is a large signal
phenomenon and in two stage op-amps connected in buffer configuration,
√ it can be observed
when the input voltage exceeds the fed back noise by more than 2 VOV .

3.6 Common Mode Rejection Ratio (CMRR)

Two signals are said to be common mode signals if they have the same amplitude and phase.
The common mode rejection ratio is a parameter to quantify the ability of a differential circuit
to reject the effect of these signals at the output if these signals are given as inputs. Consider a
differential op-amp with inputs V+ and V− . Let ADM be the differential mode gain and ACM
be the common mode gain. Under such condition, the output of the op-amp is given by

Vout = ADM (V+ − V− ) + 0.5ACM (V+ + V− ) (6)

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Referring to (6) CMRR is the ability of the circuit to reject the term 0.5ACM (V+ + V− ).
CMRR is defined as
ADM
CM RR = 20log( )dB (7)
ACM

3.7 Power Supply Rejection Ratio (PSRR)

Power Supply Rejection Ratio is the ability of a circuit to reject the variations in power supply,
so higher the PSRR, more faithful the operation of circuit. An ideal op-amp has infinite PSRR.
Mathematically, the PSRR of an opamp is defined as
ADM (vdd = 0)
P SRR = (8)
AV DD (vid = 0)
where ADM (vdd=0 ) is the differential gain of the op-amp when there are no ac fluctuations in
the supply voltage while ADD (vid=0 ) is the ac gain from supply voltage to the output voltage
when the ac differential input is 0. AV DD is defined as vout
vdd .

3.8 Input offset voltage

An op-amp mainly amplifies the differential input voltage. Hence, if the differential input is
zero, the output voltage is also expected to be 0. However if the mosfets of the differential input
are not matched (due to manufacturing process), a non zero output voltage is observed even
with zero differential input voltage. Therefore the output voltage is zero at a non zero value of
differential input, called the input offset voltage.

3.9 Total Harmonic Distortion (THD)

Harmonics or harmonic frequencies of a periodic voltage or current are frequency components in
the signal that are at integer multiples of the fundamental frequency. A voltage or current that is
purely sinusoidal has no harmonic distortion because it consists of a single frequency. A voltage
or current that is periodic but not purely sinusoidal will have higher frequency components in
it contributing to the harmonic distortion of the signal. In general, the less that a periodic
signal looks like a sine wave, the stronger the harmonic components are and the more harmonic
distortion it will have. Total harmonic distortion (THD) is defined as the ratio of the equivalent
root mean square (RMS) voltage of all the harmonic frequencies (from the 2nd harmonic) over
the RMS voltage of the fundamental frequency.
pP∞
2
n=2 V nrms
T HD = (9)
Vf rms

3.10 Corner Analysis

Though a circuit is designed for nominal operating conditions and typical device parameters,
the actual operating temperature and other conditions might vary over a large range and the
device parameters after the fabrication may deviate from the nominal values. Process corners
represent the extremes of the parameter variations. If the circuit functions well at these process
corners, the proper functionality of the circuit is ensured over wide range of conditions.
Two letter designators are used to represet corners where the first letter refers to the NMOST
corner and the second letter corresponds to the PMOST corner. Three corners exist: fast, slow
and typical based on the carrier mobilities. There are 5 possible corners FF (fast NMOS fast
PMOS), SS (slow NMOS slow PMOS), TT (typical-typical), FNSP (fast NMOS slow PMOS),
SNFP (slow NMOS fast PMOS).

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4 Design
A rough design was made using hand calculations based on the given specifications and a few
assumptions. The first level design is as follows:
For a phase margin of 60◦ and a second pole a greater than the UGB, the value of compensation
capacitor should be

Cc > 0.22 × CL (10)

CL = 10pF
Cc = 3pF
For a slew rate of 20V/µs,
Ibias
= SR (11)
Cc
Ibias = 60µA
For a unity gain bandwidth of 100MHz,
gm1,2
= U GB × 2π (12)
Cc
gm1,2 = 1885µA/V
(W/L)1,2 is found from Ibias and gm1,2 as

W (gm )
( )1,2 = (13)
L µn Cox Ibias
W
(
)1,2 = 200
L
Width of M1,2= 36µm if length = 180nm.
For further calculations, input common mode range (ICMR) is taken from 0.8V to 1.6V.
(W/L)3,4 are found from the bias current and upper limit of ICMR using the (14)
W Ibias
( )3,4 = (14)
L µn Cox (VDD − Vin(max) − VT 3(max) + VT 1(min) )2

W
( )3,4 = 25
L
Width of M3,4= 4.5µm if length = 180nm.

Saturation voltage of M0 is found using bias current and lower limit of ICMR using
s
Ibias
VDSS = Vin(min) − VSS − VT 1(max) − (15)
µn Cox ( W
L )1,2

(W/L)0 is found from the bias current and VDSS .

W 2Ibias
( )0 = (16)
L µn Cox Von
W
( )0 = 2
L

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The length of transistors M0 and M8 are taken as 500nm. As length increases, the channel
length modulation effects decrease and rout increases.
Width of MOSFET M0= 1µm if length = 500nm.

The first stage transistors are assembled and parameters tweaked to obtain all the transistors
in saturation region.

The width of M5 was adjusted to get the second pole outside the UGB and value of nulling
resistor was adjusted to obtain the zero at infinite frequency.
The width of M6 is adjusted according to (17) to avoid systematic offset.

(W/L)5 (W/L)6
=2× (17)
(W/L)3,4 (W/L)0

Table 1. shows the final (W/L) ratios and dimensions of transistors.

MOS (W/L) W (µm) L (nm)

M0 16 8 500
M1 200 36 180
M2 200 36 180
M3 25 4.5 180
M4 25 4.5 180
M5 100 18 180
M6 32 16 500
M8 2 1 500

Table 1: Transistor sizes

Cz 2.2 pF
Rz 2 KΩ

Table 2: Final value of compensation capacitor and nulling resistor

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5 Simulation Results
5.1 Frequency Response

Figure 2: Frequency response of differential gain of unbuffered op-amp

5.1.1 Observations
• The unbuffered op-amp has a DC gain of 41 dB (100V/V).
• The unity gain bandwidth of the unbuffered op-amp is around 166 MHz, for capacitance
load of 10pF.
• The unbuffered op-amp has around 86◦ , for capacitance load of 10pF.
• THe -3dB frequency of the op-amp is at around 1MHz.
• Only a single pole occurs inside the UGB, all the other poles and zeros lie outside the
UGB, hence this op-amp can be approximated as a single pole system.

5.2 Slew Rate

The op-amp is connected in unity gain feedback and a square wave of high frequency (50 MHz)
is applied, so that the rate of increase of the output wave is a constant. Slew rate is calculated
as the mean of slope of the rising and falling edges.

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 Figure 3: Input square wave

Figure 4: Slew rate limited output wave

5.2.1 Observations
• The slope of the rising edge is 108/µs and the slope of the falling edge is 75V /µs. Slew
rate is the mean of the two values = 91.5V /µs.
• The slew rate is high because of the high first stage bias current and low compensation
capacitance value.
• The rate of change is different for rising and falling edges because the current paths
are different, and hence different capacitances come into picture during charging and
discharging phases.
• If the output wave looks like a triangular wave, the rate of increase of output is slew
rate limited. If the output increases exponentially, the rate of increase is limited by the
bandwidth of the op-amp.

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5.3 Input Common Mode Range (ICMR)
Input common mode range was found by applying different input common mode voltage and
checking the region of operation of the transistors.

5.3.1 Observations
• All the transistors remain in saturation region for an input voltage in the range of 1V to
1.35V.
• The Von of M5 is approx 467 mV and the VT of M1,2 is 519mV , theoretically 0.986V is the
minimum voltage upto which the input can go without affected the region of operation of
M0.
• The upper limit of the ICMR also match the theoretical values neccessary to keep M1,
M2 and M4 in saturation.

5.4 Offset Voltage

The op-amp was connected in buffer configuration with small signal input as 0V. The output
voltage across the capacitor was measured and divided by gain (=1) to refer to input. Offset
voltage arise mainly due to mismatch between transistors, but there is no mismatch between
transistors at schematic level.

Figure 5: Input and output voltage for offset calculation

5.4.1 Observation
The difference between the input and output voltage is 25mV. But this difference is due gain
error (finite open loop DC gain).

5.5 Common Mode Rejection Ratio (CMRR)

The two input terminals of the op-amp were shorted and a small signal voltage along with
the bias voltage were applied and the gain at output terminal was measured. CMRR(dB) is
obtained as the difference between the differential mode gain in dB and the common mode gain
in dB.

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 Figure 6: Frequency response of common mode gain

5.5.1 Observations
• The low frequency common mode gain is -8dB.
• The low frequency CMRR is 48 dB.
• The -3 dB frequency of the common gain is around 15 MHz. This means that the CMRR
starts falling from around 15 MHz. Common mode rejection performance is not good
enough in the remaining frequency band of the op-amp.

5.6 Power Supply Rejection Ratio (PSRR)

A small signal variation (vdd= 10mV) is applied to the power supply VDD and its effect on
the output is observed, with no input small signal voltage applied. PSRR(dB) is obtained as
the difference between the differential mode gain in dB and the gain of power supply variation
in dB.

5.6.1 Observation

Figure 7: Frequency response of gain of supply voltage to output voltage

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 • Small signal variations in vDD gets transferred to output by a gain of -2dB.
• Power supply rejection ratio of op-amp equals to 42 dB.

5.7 Total Harmonic Distortion

An input sine wave of 50 KHz frequency and -2 dBm amplitude is applied and the percentage
of total harmonic distortion in the output are observed.

Figure 8: Percentage of Total Harmonic Distortion

5.7.1 Observations
• A THD of 300 percent is observed.

5.8 Buffer Configuration of Op-amp

The op-amp was connected in unity gain feedback and its frequency and transient responses
were observed.

VDD VDD VDD

M3 M4
M5
CC
IS
VOUT
RZ
CL
M1 M2 VIN+

M8 M6
M0

Figure 9: Op-amp connected in buffer configuration

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5.8.1 Frequency Response

Figure 10: Frequency response of op-amp in buffer configuration

5.8.2 Observation
• Bandwidth of op-amp in unity gain configuration is equal to its open loop dc gain × open
loop bandwidth, as the op-amp can be approximated as a single pole system.
• Buffer has a DC gain 0f 0.2 dB.

5.8.3 Transient Response

Figure 11: Transient response of op-amp in buffer configuration

5.8.4 Observation
• The buffer has a gain of 0.975V/V = 0.2dB.
• There is an offset difference between the input and output sine wave.

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5.9 Power Dissipation
The total current drawn from VDD = 1.5mA and VDD is 1.8V. So the power dissipation is 2.7
mW.

5.10 Corner Analysis

Unity gain bandwidth, phase margin and slew rate of the op-amp were evaluated in the 4 process
corners.

5.10.1 Frequency Response

Figure 12: Frequency response of op-amp in FF corner

Figure 13: Frequency response of op-amp in SS corner

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Figure 14: Frequency response of op-amp in FNSP corner

Figure 15: Frequency response of op-amp in SNFP corner

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5.10.2 Slew rate

Figure 16: Slew rate of op-amp in FF corner

Figure 17: Slew rate of op-amp in SS corner

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 Figure 18: Slew rate of op-amp in FNSP corner

Figure 19: Slew rate of op-amp in SNFP corner

Corner Gain(V/V) UGB (MHz) PM (deg) SR(Rise) SR (Fall) SR (Mean) (V /µs)

ss 39 142.43 86.5 105.6 78.96 92.3
snfp 41.5 190.3 84.716 123.15 78.36 100.756
tt 40 166 86 75 107.86 91.5
fnsp 38 139 87.8 104.577 72.73 88.6535
ff 40 186 86.2 111.11 73.46 92.285

Table 3: Specifications of op-amp in various process corners.

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5.10.3 Observations
• The design meets the UGB, PM and slew rate specifications in the process corners.

5.11 Area Estimation

The designed circuit has four components, NMOS, PMOS, capacitor and resistance. The area
of the circuit is calculated by summing the individual areas.

L+1.4 L+2

W+0.8 NMOS W W+1 PMOS W

L L
Figure 20: Area Estimation using approximate layout dimensions (All dimensions are in µm)

5.11.1 Area estimation of NMOS

To estimate the area of NMOS, the area estimation technique described in Fig. 20 is used. The
dimensions of various transistors can be seen in TABLE I. The total area required for all NMOS
is calculated as

A1 = (1+0.8)(0.5+1.4)+(8+0.8)(0.5+1.4)+2×(36+0.8)(0.8+1.4)+(16+0.8)(0.5+1.4) = 168.048µm2
(18)

5.11.2 Area estimation of PMOS

To estimate the area of PMOS, the area estimation technique described in Fig. 20 is used.
The dimensions of the various transistors can be seen in Table I. The total area required for all
PMOS is calculated as

A2 = 2 × (4.5 + 1)(0.18 + 2) + (18 + 1)(0.18 + 2) = 65.4µm2 . (19)

5.11.3 Area of resistor

Resistor is realized using the RNPPO MM cell in UMC 180nm CMOS technology technology.
For a resistance of 2kΩ a width of 250 nm and a length of 600 nm is required. Therefore resistor
consumes an area of 0.15µm2 . Assuming a boundary are of 2 µm2 , the total area occupied by
the resistor is approximately 2.15 µm2 . Let it be denoted as A3

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5.11.4 Area of capacitance
Capacitance is realized using MIMCAPS MM in UMC 180nm CMOS technology. 1pF capacitor
consumes an area of of 92.22×10µm2 = 922.2 µm2 . Assuming some area will be consumed for
boundary, let’s assume that the 1 pF capacitance will consume a total area of 1000 µm2 .
Therefore a 2.2 pF capacitor consumes an area of 2200 µm2 . Let it be denoted as A 4.
Therefore total are consumed is

T otalArea = A1 + A2 + A3 + A4 = 2435.598µm2 (20)

It can be noted that most of the area is consumed by compensation capacitance.

6 Conclusion
A two stage architecture was used to design an operational trans-conductance amplifier with
the following specifications at 300K:

Parameter Value
DC gain 41dB
Unity Gain Bandwidth 166 MHz
Phase margin 86◦
Slew Rate 91.5 V /µs
ICMR 0.98 to 1.35V
CMRR 48dB
PSRR 42dB
Power Consumption 2.7mW
Estimated area 2, 435.598µm2

Table 4: Parameters of the op-amp

The designed op-amp meets the given specifications at all process corners.
A higher DC GAIN, CMRR and PSRR can be obtained by an increase in transistor sizes
but since the bottle neck was to meet the given specifications with minimum area and power
consumption we have traded off DC gain, CMRR and PSRR for a lower power consumption
and chip area.

References
[1] Phillip E Allen & Douglas R. Holsberg, ”CMOS Analog Circuit Design”, Oxford University
Press, 2002
[2] Behzad Razavi, ”Design of Analog CMOS Integrated Circuits”, 2nd Edition Mc Graw Hill
India, 2017

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