Academic Year 2019/20

ENG632d1 Electronics

Assignment – Coursework 1

Deadline For Submission: 13th January 2020 – 23:00 UK time

Submission Instructions Submitted to Turnitin boxes in the Moodle’s module website.

Instructions for completing the Answer all questions.

assessment: The report should be edited electronically using a word processor.
Tables and diagrams can be handwritten and inserted in the document
file as images. The uploaded file should be in PDF format.

Examiners: Dr A Benkrid

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1. Consider a logic function with the standard minterm canonical form:

f(A,B,C,D)= ∑𝑚𝑚(0,2,3,8,10,11,15)

(i) Write the logical expression of the function f.

[1 mark]
(ii) Write the function in the standard maxterm canonical form.
[1 mark]
(iii) Implement the function f using one 16-1 multiplexer.
[2 marks]

(iv) Implement the function f using one 4-16 decoder having appropriate number of inputs, and one
logic gate.
[2 marks]

(v) Using Boolean algebra rules, give the most simplified logical expression of the function f. Show the
details of your work.
[3 marks]

(vi) Using Karnaugh map, give the most simplified logical expression of the function f. Show the details
of your work.
[3 marks]

(vii) Using the most simplified logical expression of the function f, draw the resulting circuit of the
function using only NAND gates (even to generate the inverse of an input).
[3 marks]

(viii) Write a VHDL entity to model the function f.

[3 marks]

2. A sequence detector has a single binary input and a single binary output. The output of the detector
should turn immediately to logic 1 when the pattern 0110 is received in the input stream without
overlap patterns. Here is an example of input-output sequence:

Input : 1110110110110
Output : 0000001000001

Give a Finite State Machine (FSM) transition diagram of the above system.

[4 marks]

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3. Figure 3.1 gives the diagram of a Finite State Machine (FSM) used in a process control system. The
FSM has one input, one output and three states.

reset

S0

0/1

S1

S2

Figure 3.1: FSM diagram

(i) Name the model of the above FSM. Explain your answer.
[1 mark]

(ii) Design an efficient digital circuit of this FSM using D-type flip-flops. In your answer, you should
include the following:

(a) State transition table

[2 marks]

(b) Karnaugh maps to get simplified logical expressions of the D flip-flops inputs and the FSM
output.
[7 marks]

(iii) Verify in Logisim software the correctness of your designed digital circuit. Discuss the results of
your simulation. (The Logisim design circuit and simulation log file should be both submitted.)

[5 marks]

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4. Consider a loadable n-bit counter (GenCount) with an input control select signal (Sel), an input
load value (Load), a counter output value (Counter), and an output 1-bit signal P (see Figure 4.1).

Sel [0:1] P

Counter[0: n-1]
GenCount (n)
Load [0: n-1]
Reset Clk

Figure 4.1: Loadable n-bit Counter (GenCount)

The counter has the following characteristics:

• It is clocked on the falling edge clock (Clk) with an asynchronous active high reset (Reset) signal
input.
• When the integer value of Sel equals,
o 0, the counter is loaded with the value of Load
o 1, the counter increments by one
o 2, the counter decrements by one
o 3, the counter does not change its value
• P is set to ‘1’ when the counter value equals 4.

(i) Write a VHDL code to model GenCount unit.

[11 marks]

(ii) An instance of GenCount with n equal to 8 is used to implement the sequential system
CompCount shown in Figure 4.2. Assume that the VHDL code of Comp is already available in
which the input and output ports are named as shown in the figure.

Sel [0:1] Sel [0:1] P Ref[0:7]

Less
Counter[0:7]

GenCount
Counter [0:7]
Load [0:7]

Load [0:7]
n=8 Comp
Equ
Reset Clk Reset Clk
Reset
Clk

Figure 4.2: Structure of CompCount system

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 Using VHDL structural modelling (design by hierarchy), write the VHDL entity to model the
system CompCount.
[9 marks]

What to submit:

• All your Model VHDL source files. The code should be properly commented.
• Report (up to 150 words) which should record:
 Model: description with justification of your design. The VHDL constructs used to code the
design should be identified and argued with reference to the relevant lines of code.
• A penalty of 3 marks will be induced if the required report cited above is not submitted

5. A company aims to build a machine to grade, sort and pack eggs. Your task is to design in VHDL the
control unit, which allows to sort eggs so they get routed to the correct packing machine. Eggs are sorted
into four different packing sizes as shown in Table 5.1, which also gives the required number of eggs in
each Pack.
Table 5.1: Egg details
Egg Size Packing Point Number in Pack
0,1,2 A (Small) 12
3,4 B (Medium) 12
5,6 C (Large) 6
7 D (Extra Large) 6

Specification:

Figure 5.1 gives the interface ports of the Control unit. The egg grading part of the machine sends the eggs
for sorting and packing one at a time, not necessarily in a uniform rate. It feeds the Egg_Size input of the
Control Unit with values between 0 and 7, and signals the availability of an egg with an"Egg Available"
strobe/pulse signal.

As shown in Figure 5.1, the control unit counts and outputs the number of eggs of each size, e.g.
Pack_A_Count. When the required number of eggs in a pack is reached, a corresponding "Pack Full" pulse is
generated, e.g. Pack_A_Full_Pulse. This causes the pack to leave the machine, and a new empty pack to be
loaded; the count for the corresponding pack size is reset to zero.

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 Reset Pack_A_Count

Pack_B_Count

Pack_C_Count
Egg Size
Eggs Grader
Pack_D_Count
Control Unit
Pack_A_FULL_pulse
Pack_B_FULL_pulse
Egg Available
Strobe Pack_C_FULL_pulse

Pack_D_FULL_pulse

Figure 5.1: Interface Ports of the Control Unit of the machine

The pack full pulse should last for 5 ms. Assume that you have an oscillator of 1 KHz available for use.

Testing your design:

To test the control unit a series of "Egg size" together with an "Egg available" strobe to clock the latest egg
size value into the Control Unit should be generated in the VHDL testbench file using a rand() function.

What to submit:

• All your Model and Test bench VHDL source files. The code should be properly commented.
• Report (up to 450 words) which should record:
 Model: description with justification of your design. The VHDL constructs used to code the
design should be identified and argued with reference to the relevant lines of code.
 Test bench and simulation:
• Brief description of the test vectors used
• Description how the random data is generated in the testbench.
• Annotated simulation waveforms highlighting sections where your modelling to the system
is correct / incorrect.

Mark Breakdown:
• VHDL Models (12 marks): package and entity: 3 marks; Pack_X_Count signals: 4 marks; Pack_X_Full
signals: 5 marks
• Test Benches and Simulation Discussion (10 marks): 4 marks for the test bench and 6 marks for
the explanation

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6. To ensure data reliability, error detection and correction codes are used in special computer data
storages to detect and correct most of internal data corruption, as well as in telecommunication. In fact,
many communication channels are subject to channel noise, and thus errors may be introduced during
transmission from the source to a receiver (a 0 bit may change to 1 or vice versa).

The modern development of error-correcting codes is due to Richard W. Hamming who developed in
1947 a special data encoding, named after himself, to detect and correct errors. Hamming codes can detect
and correct single-bit errors or can detect (but not correct) up to two simultaneous bit errors.

Requirements:

This task aims to design in VHDL the structure shown in Figure 6.1. The structure implements the single error
correction double error detection (SEC-DED) Hamming (8,4) coding on an 8-bit input. Your design should
give a solution to,

• Encode an 8-bit input sequence into a SEC-DED Hamming (8,4) code

• Model data corruption (noise) in the simulation testbench, where up to 3-bit error can be injected at
a random byte bit position into the Hamming(8,4) code

Noise

8-bit input 4-bit nibbles 8-bit output

Hamming (8,4)
Word Splitter
coder +

Figure 6.1: Hamming(8,4) based coder

What to submit:

• All your Model and Test bench VHDL source files. The code should be properly commented.
• Report (up to 600 words) which should record:
 Model: description with justification of your design. The VHDL constructs used to code the
design should be identified and argued with reference to the relevant lines of code.
 Test bench and simulation:
• Brief description of the test vectors used
• Description how the random data is generated in the testbench.

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 • Annotated simulation waveforms highlighting sections where your modelling to the system
is correct / incorrect.

Mark Breakdown:
• VHDL Models (8 marks): package and entity: 2 marks; Word Splitter: 3 marks; Hamming (8,4) code
3 marks
• Test Benches and Simulation Discussion (13 marks): 6 marks for the test bench and 7 marks for the
explanation