Project

MULTIPLIER
MULTIPLICATION ACCLERATION THROUGH BOOTH’S

AND MODIFIED BOOTH’S MULTIPLIER
A project report submitted to Jawaharlal Nehru Technological University Kakinada,
Kakinada in Partial fulfilment for the award of degree of
BACHELOR OF TECHNOLOGY
IN
ELECTRONICS & COMMUNICATION ENGINEERING

Submitted by
G.HIMASAILA (17495A0410)
G.RENUKA (17495A0409)
P.SRAVANI (17495A0412)
G.ANUSHA (16491A04I7)
Under the Guidance of
Mr. T.SRIRAM MURTY M.Tech,(ph.D)

Associate Professor
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
QIS COLLEGE OF ENGINEERING & TECHNOLOGY

(Autonomous)
(Approved by AICTE, New Delhi & Affiliated to JNTUK, Kakinada)
(An ISO 9001:2008 Certified, NBA Accredited, Recognized by UGC & NAAC
With ‘A’ Grade Institution)
VENGAMUKKAPALEM, PONDUR ROAD, ONGOLE-523272, A.P.

2016-2020
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QIS COLLEGEOF ENGINEERING AND TECHNOLOGY

(AUTONOMOUS)
(AnISO9001-2008Certified&NBAAccreditedInstitution)
(Affiliated to Jawaharlal Nehru Technological University, Kakinada)
VENGAMUKKAPALEM, ONGOLE-523272, A.P
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
BONAFIDECERTIFICATE
This is to certify that the project entitled “MULTIPLICATION
ACCELERATION THROUGH BOOTH’S AND MODIFIED BOOTH’S
MULTIPLIER” is a Bonfide work of
G.HIMASAILA (17495A0410)
G.RENUKA (17495A0409)
In the partial fulfilment of the requirement for the award of the degree of Bachelor of
Technology in ELECTRONICS &COMMUNICATION ENGINEERING and for the academic
year 2019-2020. This work is done under my supervision and guidance.
Signature of the Guide Signature of the HOD

Mr. T.SRIRAM MUTHY, M.Tech,(ph.D) Dr. CH.HIMA BINDU, M.Tech, Ph.D
Assistant Professor Professor and HOD
Signature of the External Examiner
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ACKNOWLEDGEMENT
“Task successful “makes everyone happy. But the happiness will be gold without glitter if
we didn’t state the persons who have supported us to make it a success.
We would like to place on record the deep sense of gratitude to the Honourable
Secretary& Correspondent Sri .N.SURYA KALYAN CHAKRAVARTHY, QIS Group
of Institutions, Ongole for providing necessary facilities to carry the project work.
We express our gratitude to the Honourable chairman Sri .N. NAGESWARARAO

GARU, QIS Group of Institutions, Ongole for his valuable suggestions and advices in
the B. Tech Course.
We express our gratitude to Dr.D.VENKATARAO, Ph.D., Principal of QIS College of

Engineering and Technology, Ongole for his valuable suggestions and advices in the B.
Tech course.
We express our gratitude to the Head of the Department of ECE, Dr.CH.HIMA

BINDU, M.Tech, Ph.D., QIS College of Engineering & Technology, Ongole for her
constant supervision, guidance and co-operation throughout the project.
We would like to express our thankfulness to our project guide Mr.T.SRIRAM
MURTHY, M.Tech,(ph.D). QIS College of Engineering & Technology, Ongole for
his constant motivation and valuable help throughout the project work.
Finally, we would like to thank our Parents, Family and friends for their co-operation to
complete this project.
Submitted by
G.HIMA SAILA (17495A0410)

G.RENUKA (17495A0409)
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MULTIPLIER
MULTIPLICATION
ACCELERATION THROUGH
BOOTH’S AND MODIFIED
BOOTH’S MULTIPLIER
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CONTENTS
 List of tables…………………………………………………………....vii
 List of figures………………………………………………………….vii
 Abstract……………………………………………………………......viii
Chapter 1
1.1 Introduction………………………………………………………........01
1.2 Purpose of the project……………………………………………….....02
1.3 Aim of the project…………………………………………………..….02
1.4 Scope of the project………………………………………………..….02
Chapter 2
 Existing approach……………………………………………………...03
2.1 2*2 multiplier……………………………………………………...03
2.2 4*4 multiplier………………………………………………………05
2.3 8*8 multiplier………………………………………………………06
Chapter 3
 Proposed method………………………………………………………10
3.1 booth’s multiplier………………………………………………….10
3.2 modified booth’s multiplier………………………………………..12
Chapter 4
 Results…………………………………………………………………..14
4.1 4*4 multiplier………………………………………………………14
4.2 8*8 multiplier………………………………………………………14
4.3 booth multiplier……………………………………………………15
4.4 modified booth multiplier………………………………………….15
Chapter 5
5.1.1 Disadvantages ………………………………………………………16
5.1.2 Advantages………………………………………………………….17
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5.2.1 Future scope ……………………………………………………….…..18
5.2.2 Conclusion………………………………………………………………18
5.2.3 Comparison…………………………………………………………….18
Appendix a
 Source codes
4*4 multiplier…………………………………………………………...19
8*8 multiplier…………………………………………………………..20
Booth multiplier………………………………………………………..23
Modified booth multiplier………………………………………………24
Bibliography……………………………………………………………….….27
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LIST OF TABLES:
Table 3.1.1booth multiplier …………………………………………...…….19
Table 3.2.1modified booth encoding table…….……………………..….…..20
Table 5.2.3.1comparision table……………………………………….….….26
LIST OF FIGURES:
Figure2.1.1Logicdiagram of 2bit multiplier………………………….….….10
Figure2.1.2 Circuit diagram of 2bit multiplier………………….……....…...11
Figure2.2.1Logic diagram of 4 bit multiplier………………….………...….12
Figure2.3.1logic diagram of 8bit multiplier.……………………………..…13
Figure3.2.1Structure of modified booth multiplier……………….………. ..18
Figure4.1.1output waveform of 4bit multiplier………………….……….....21
Figure4.2.1output waveform of 8bit multiplier………………….…...…......21
Figure4.3.1output waveform of booth multiplier……………………….…..22
Figure4.4.1output waveform of modified booth multiplier………...…….....22
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ABSTRACT
A binary multiplier is a combinational logic circuit used in digital systems to
perform the multiplication of two binary numbers. These are most commonly
used in various applications especially in the field of digital signal processing to
perform the various algorithms. Commercial applications like computers,
mobiles, high speed calculators and some general purpose processors require
binary multipliers. Compared with addition and subtraction, multiplication is a
complex process. In multiplication process, the number which is to be
multiplied by the other number is called as multiplicand and the number
multiplied is called as multiplier. Similar to the multiplication of decimal
numbers, binary multiplication follows the same process for producing a
product result of the two binary numbers. The binary multiplication is much
easier as it contains only 0s and 1s.
As much it is easy that much it is also confuse us. A small fault while doing
binary multiplication makes a very big change. There are various methods to
perform binary multiplication in an accurate way. Some of the methods are
going to be discussed in this project.
This technique can reduce the power dissipation by adapting a multiplier.The

total time taken in order to give the proper result is also very less compared to
manual multipliers i.e., 4 bit and 8 bit multipliers.
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Chapter 1
1.1 INTRODUCTION:
As in decimal system, the multiplication of binary numbers is carried out by multiplying the
multiplicand by one bit of the multiplier at a time and the result of the partial product for each
bit is placed in such a manner that the LSB is under the corresponding multiplier bit.
Finally the partial products are added to get the complete product. The placement of the
binary point in the product of two binary numbers having fractional representation is
determined in the same way as in the product of decimal numbers with fractional
representation. The total number of places after the binary point in the multiplicand and the
multiplier is counted.
The binary point in the product is then placed before this total number of places counted from
right. It should be noted that a multiplication by zero makes all the bits of the partial product
zero and may thus be ignored in intermediate steps.
Also, a multiplication by 1 leaves the bits of multiplicand unchanged but shifts it towards the
left by one bit position. The multiplication of binary numbers becomes more convenient by
carrying out intermediate sums of partial products.
In the case of binary multiplication there are certain advantages. The multiplication is
actually the addition of multiplicand with itself after some suitable shift depending upon the
multiplier. Thus multiplication is actually a process of shifting and adding. This process is to
be continued until the shifting due to MSB of the multiplier is done and final addition is
made.
This scheme has several drawbacks:
i) The total area of the multipliers would increase, since several multiplier units are used.
ii) The use of several multipliers increases the fan out of the signals that drive the inputs of
the multipliers .Higher fan out means longer delays and/or higher power dissipation.
iii) There would be a need for multiplexers that connect the active multiplier to the
Result route.
These disadvantages can be overcome by using booths and modified booths algorithm.
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1.2 Purpose of the project:
The main purpose of the project is how to improve the speed and how to reduce the
power dispassion by using MODIFIED BOOTHS technique and the previous algorithms to
applying a twin precession technique some of the draw backs are there those are
1. For lower radix multipliers this booth algorithm yields correct results but, if we go for
higher radix this algorithm yields wrong output.So we go for modified booth algorithm.
2. For un-signed higher radix multipliers this modified booth algorithm works properly. But
we go for higher radix signed multipliers this modified boot algorithm does not work
properly
1.3 Aim of the project:
The main aim of the project is to developing a code for BOOTH’S

AND MODIFIED BOOTH ALGORITHM technique. This technique can reduce the power
dissipation by adapting a multiplier to the bit width of the operands being computed. The
technique also enables an increased computational throughput, by allowing several narrow-
width operations to be computed in parallel. It is shown that the modified booths technique
delay penalty is small (5%―10%) and that a significant reduction in power dissipation (40%-
70%) can be achieved, when operating on narrow-width operands. In an application case
study, we show that by extending the multiplier of a general-purpose processor with the twin-
precision scheme, the execution time of a Fast Fourier Transform is reduced with 15 % at a
14 % reduction in data path energy dissipation.
1.4 Scope of the project:
In this project having
1. Generalmultipliers for Signed and unsigned multipliers
2. Booth multiplier for Signed and unsigned multipliers
3. Modified booth multiplier for Signed and unsigned multipliers
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Chapter 2
Existing approach:
In binary multipliers there are many types those are:
 2x2 multiplier
 4x4 multiplier
 8x8 multipliers
These are most commonly used multipliers among remaining all multipliers.
2.1 2x2 multiplier:
Figure 2.1.1:2 bit multiplier logic diagram
Structure:
The two numbers A1A0 and B1B0 are multiplied together to produce a 4-bit output
P3P2P1P0.
A1 A0
X B1 B0
-------------------------------------------------------------------
B0A1 B0A0
B1A1 B1A0
-------------------------------------------------------------------
P3 P2 P1 P0
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Thus, we get the partial products as:

P0 = A0*B0
P1 = A0*B1 xor A1 * B0
P2 = A1*B1 xor (A0*B1) * (A1*B0)
Example:
2x3=6
10
X 11
__________________________
10
1 0
______________________________
1 1 0
Figure2.1.2 circuit diagram of 2bit multiplier
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2.2 4x4 multiplier:

This multiplier carries out the multiplication in two steps.
First is four 2 by 2 bit multiplications carried out, creating four partial 4-bit products. The
four 4-bit partial products are added together to create the final 8-bit product. With this
method is the hardware cost kept low to implement the multiplier. Also the work to
implement the multiplier can be kept low, since only three different types of non-complex
blocks are needed to be used to build up the entire multiplier.
Figure2.2.1 structure of 4bit multiplier
Structure:
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Example:
2.3 8X8 MULTIPLIER:

An 8X8 multiplier is to be designed using Verilog. The multiplier accepts two 8-bit
numbers; multiplicand and multiplier and results in 16-bit multiplication. The design is to be
optimised for speed.
Wallace tree multiplier is made up of mainly two components, namely, half-adder and full-
adder. So firstly, a half-adder and a full-adder are designed. For constructing an 8X8
multiplier, we need 8 half-adders and 48 full-adders i.e. a total of 56 adders. Hence, the half
adder and the full adder is instantiated for each computation as per the requirement by
passing the appropriate parameters. The final result is obtained from the sum and carry bits of
the adders.
2.3.1 Logic diagram of 8bit multiplier
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STRUCTURE:
Multiplier is multiplied with multiplicand, produces product. For that, first production of
partial products takes place. After generating partial products either directly or using smaller
multipliers accumulate these to obtain final product a fast multi-operand adder
X=multiplicand.
Y=multiplier.
Each bit of the multiplier is multiplied with multiplicand and produces partial products, after
accumulation of all those partial products we can get final result as product.
Example:
let us consider 2 numbers
15 ------ 00001111
13 ------ 00001101
2‘s complement of 13---- 11110011
Then normal multiplication operation can be performed as:
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0 0 0 1 1 1 1 X 1 1 1 1 0 0 1 1
-------------------------------------------------------------
0 0 0 0 1 1 1 1
0 0 0 01 1 1 1
------------------------------------------------------------------------
0 0 0 1 0 1 1 0 1
0 0 0 0 0 0 0 0
------------------------------------------------------------------------------
0 0 0 0 1 0 1 1 0 1
0 0 0 0 0 0 0 0
-----------------------------------------------------------------------------------------------
0 0 0 0 0 1 0 1 1 0 1
0 0 0 0 0 1 1 1
---------------------------------------------------------------------------------------------------
0 0 0 1 0 0 0 1 1 1 0 1
0 0 0 0 1 1 1 1
---------------------------------------------------------------------------------------------------------------
0 0 0 1 0 1 1 1 1 1 1 0 1
0 0 0 0 1 1 1 1
-----------------------------------------------------------------------------------------------------------------------
0 0 0 1 1 0 1 0 1 1 1 1 0 1
0 0 0 1 1 1 1
0 0 0 1 1 1 0 0 0 1 1 1 1 0 1
1 1 1 0 0 0 0 1 1 answer= 195
Msb 1-magnitude 27 26 21 20
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Chapter 3
Proposed methods:
In order to overcome the disadvantages in normal multiplier there are two methods are
proposed those are….
1.Booth algorithm
2.Modified booth algorithm
3.1. Booth Multiplication Algorithm:
Booth's multiplication algorithm is a multiplication algorithm that multiplies two

signed binary numbers in two's complement notation.
Procedure:
Booth's algorithm involves repeatedly adding one of two predetermined

values A and S to a product P, then performing a rightward arithmetic shift on P.
Let m and r be the multiplicand and multiplier, respectively; and let x and y represent the
number of bits in m and r.
Determine the values of A and S, and the initial value of P. All of these numbers
should have a length equal to (x + y + 1).
A: Fill the most significant (leftmost) bits with the value of m. Fill the remaining (y + 1) bits
with zeros.
S: Fill the most significant bits with the value of (−m) in two's complement notation. Fill the
remaining (y + 1) bits with zeros.
P: Fill the most significant x bits with zeros. To the right of this, append the value of r. Fill
the least significant (rightmost) bit with a zero.
Example:
Determine the two least significant (rightmost) bits of P.
If they are 01, find the value of P + A. Ignore any overflow.
If they are 10, find the value of P + S. Ignore any overflow.
If they are 00, do nothing. Use P directly in the next step.
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If they are 11, do nothing. Use P directly in the next step.
Arithmetically shift the value obtained in the 2nd step by a single place to the right.
Let P now equal this new value.Repeat steps 2 and 3 until they have been done y times. Drop
the least significant (rightmost) bit from P. This is the product of m and r.
Example 1:
Let us consider an example with two unsigned numbers 11*13
11---------- 00001011(m) subtraction => a<=a-m (if 10)
13---------- 00001101(q) addition=> a<=a+m (if 01)
No of Operations done Accumulator content(a) Multiplier(q)

steps 00000000 00001101
1 subtraction 11110101 00001101
Right shift 11111010 10000110
2 addition 00000101 10000110
Right shift 00000010 11000011
3 sub 11110111 11000011
Right shift 11111011 11100001
4 No operation 11111101 11110000
11111101 11110000
5 addition 00001000 11110000
Right shift 00000100 01111000
6 No operation 00000010 00111100
00000010 00111100
7 No operation 00000001 00011110
00000001 00011110
8 No operation 00000000 10001111
00000000 10001111
Table 3.1.1: booth’s multiplication table
0000000010001111 = 27 x 2 3 x22 x21 =143 (11*13=143)
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3.2. Modified Booth Algorithm:
For requirements of smaller area occupation and faster operation, Modified Booth’s
algorithm is practically used .This encoding algorithm is suitable for 2’s complementary and
signed number multiplication. Multiplication by modified booth algorithm reduces the
number of partial products to half when compared to general multiplication.
Bits xi and xi-1 recoded into yi and yi-1 - xi-2 serves as reference bit
Separately - xi-2 and xi-3 recoded into yi-2 and yi-3 - xi-4 serves as reference bit
Groups of 3 bits each overlap - rightmost being x1 x0 (x-1), next x3 x2 (x1), and so on
Figure3.2.1: structure of modified booth algorithm

For requirements of smaller area occupation and faster operation, MODIFIED
Booth’s algorithm is practically used .This encoding algorithm is suitable for 2’s
complementary and signed number multiplication.
In this modified booth algorithm we will take three bits of multiplier at a time as
shown in above figure, and depend upon the three bit pattern the corresponding operation is
done according to the below given table. The selection of three bits is, one pattern bit is
overlapped with the other pattern as shown in above figure
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Procedure:
Pad the LSB with one zero.
Pad the MSB with 2 zeros if n is even and 1 zero if n is odd.
Divide the multiplier into overlapping groups of 3-bits.
Determine partial product scale factor from modified booth encoding table.
Compute the Multiplicand Multiples.
Sum the Partial Products obtained.
EXAMPLE:
A = 11 // 00001011
B = 13 // 00001101
A+2’s complement = 11110100
----------------------------------------------
1111 0 10 1
-----------------------------------------------
To find out the bit pair recorded multiplier
0 0 0 - 0
0 0 1 - + 1
1 1 0 - -1
0 1 0 - + 1
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0 0 0 0 1 0 1 1
0 +1 -1 +1
------------------------------------------------------------------------------------------------
0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1
1 1 1 1 1 1 1 1 1 1 1 1 0 1
0 0 0 0 0 0 0 0 1 0 1 1
0 0 0 0 0 0 0 0 0 0
----------------------------------------------------------------------------------------------------------
10 1 1 1 1 0 0 1 0 0 0 1 1 1 1
----------------------------------------------------------------------------------------------------------
1 1 1 1 1 1 0 0 --- magnitude
1 0 0 0 1 1 1 1
27 26 25 24 23 22 21 20
-------------------------------------------------
128 + 0 + 0 + 0 + 8 + 4 + 2 + 1 = 143
Answer = 143
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Chapter 4
RESULTS:
4.1:4*4 multiplier:
Figure4.1.1: output waveform of 4bit multiplier
4.2:8*8 multiplier:
Figure4.2.1: output waveform of 8bit multiplier
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4.3:Booth multiplier:
Figure4.3.1: output waveform of booth multiplier
4.4:Modified booth multiplier:

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Figure4.4.1: output waveform of modified booth multiplier
15
Chapter 5
5.1.1 Disadvantsges :
 4*4 multiplier:
 High power consumption
 More digital gates are required so complexity is more.
 Not suitable for the higher radix that is more than 4
 It doesn’t performs the signed multiplication
 8*8 multiplier:
 It doesn’t performs the signed multiplication by direct method
 It doesn’t suitable for the radix more than 8
 Booth multiplier:
 Due to general booth algorithm hard multipliers are generated.
 For lower radix multipliers this booth algorithm yields correct
results but, if we go for higher radix this algorithm yields
wrong output.
 So we go for modified booth algorithm\
 Modified booth multiplier:
 For un-signed higher radix multipliers this modified booth
algorithm works properly. But we go for higher radix signed
multipliers this modified boot algorithm does not work properly
and produces hard multiples.

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16
5.1.2 Advantages:
 4*4 multiplier:
 Minimum complexity
 Easy to place and route
 Easily scalable
 8*8 multiplier:
 Can perform multiplication up to radix8
 Overcome the disadvantages occur due to 4bit multiplier
 Less power consumption compared to 4bit multiplier
 Booth multiplier:
 Can perform both signed and unsigned multiplication
 Consumes less power compared to 8 bit multiplier
 Modified booth multiplier;
 It overcome the disadvantages occur due to booth multiplier
 It can perform both unsigned and signed multiplication
 This multiplier can perform multiplication upro the radix 16

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17
5.2.1 Future scope:
In this project we are not reducing any partial products. So, in feature we can reduce partial products
by adding extra circuitry.
5.2.2 Conclusion
The modified booth technique allows for flexible architectural solutions, where
the variation in operand bit width can be used to decrease power dissipation and to increase
throughput of multiplications
The booth algorithm is particularly suitable for a modified booth implementation. Due to the
simplicity of this algorithm, only minor modifications are needed to comply with the modified booth
technique. This makes for an efficient modified booths implementation, capable of both signed and
unsigned multiplications.
5.2.3:Comparision:
Type of Multiplier Time consumption
4*4 multiplier 16ns
8*8 multiplier 4.283 ns
Booths multiplier 4.08ns
Modified booths multiplier 3.235ns
Table 5.2.3.1 comparison table

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18
Appendix a
Source codes:
 4*4 multiplier:
module Multiply_4x4(
input [3:0] a,
input [3:0] b,
output [7:0] p );
wire [3:0]pp0,pp1,pp2,pp3;
wire c1,c2,c3,c4,c5,c6,c7,c8;
wire s1,s2,s3,s4,s5,s6;
assign pp0=a[0]*b[3:0];
assign p[0]=pp0[0];
halfadder HA1(pp0[1],pp1[0],p[1],c1);
fulladder FA1(c1,pp0[2],pp1[1],s1,c2);
halfadder HA2(s1,pp2[0],p[2],c3);
fulladder FA2(c2,c3,pp0[3],s2,c4);
fulladder FA3(s2,pp1[2],pp2[1],s3,c5);
fulladder FA4(c4,c5,c6,s4,c7);
fulladder FA5(s4,pp1[3],pp2[2],s5,c8);
fulladder FA6(c7,c8,c9,s6,c10);
fulladder FA7(s6,pp2[3],pp3[2],p[5],c11);
fulladder FA8(c10,c11,pp3[3],p[6],p[7]);
endmodule
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19
8*8 multiplier:
module multipler (
output reg [15:0] product,
input [7:0] multiplicand, multiplier,
input clock, clear);
integer i, j ;
wire [63:0] s ,c ;
reg p [7:0][7:0];
always@(multiplier, multiplicand)
begin
for (i = 0; i <= 7; i = i + 1)
for (j = 0; j <= 7; j = j + 1)
p[j][i] <= multiplicand[j] & multiplier[i];
end
adder_half ha_11 ( .sum(s[0]), .carry(c[0]), .a(p[1][0]), .b( p[0][1]) );
adder_full fa_11 ( .sum(s[1]), .carry(c[1]), .a(p[2][0]), .b( p[1][1]), .cin( p[0][2]) );
adder_half ha_12 ( .sum(s[7]), .carry(c[7]), .a( p[7][1]), .b ( p[6][2]) );
adder_half ha_21 ( .sum( s[8] ), .carry( c[8 ]), .a( p[1][3]), .b( p[0][4]) );
adder_full fa_21 ( .sum( s[9] ), .carry( c[9 ]), .a( p[2][3]), .b( p[1][4]), .cin( p[0][5]) );
adder_full fa_22 ( .sum( s[10]), .carry( c[10]), .a( p[3][3]), .b( p[2][4]), .cin( p[1][5]) );
MULTIPLIER
adder_half ha_22 ( .sum( s[15]), .carry( c[15]), .a( p[7][4]), .b ( p[6][5]) );
20
adder_half ha_31 ( .sum( s[16]), .carry( c[16]), .a( c[0]) , .b ( s[1]) );
adder_full fa_31 ( .sum( s[17]), .carry( c[17]), .a( c[1]) , .b ( s[2]) , .cin ( p[0][3]) );
adder_full fa_32 ( .sum( s[18]), .carry( c[18]), .a( c[2]) , .b ( s[3]) , .cin ( s[8] ) );
adder_full fa_33 ( .sum( s[19]), .carry( c[19]), .a( c[3]) , .b ( s[4]) , .cin ( s[9] ) );
adder_full fa_34 ( .sum( s[20]), .carry( c[20]), .a( c[4]) , .b ( s[5]) , .cin ( s[10]) );
adder_full fa_37 ( .sum( s[23]), .carry( c[23]), .a( c[7]) , .b ( p[7][2]), .cin ( s[13]) );
adder_half ha_41 ( .sum( s[24]), .carry( c[24]), .a( c[9] ) , .b( p[0][6]) );
adder_full fa_41 ( .sum( s[25]), .carry( c[25]), .a( c[10]) , .b( p[1][6]), .cin( p[0][7]) );
adder_half fa_47 ( .sum( s[31]), .carry( c[31]), .a( p[7][6]), .b ( p[6][7]) );
adder_half ha_51 ( .sum( s[32]), .carry( c[32]), .a( s[17]) , .b( c[16]) );
adder_half fa_51 ( .sum( s[33]), .carry( c[33]), .a( s[18]) , .b( c[17]) );
adder_full fa_52 ( .sum( s[34]), .carry( c[34]), .a( s[19]) , .b( c[18]), .cin( c[8] ) );
adder_full fa_53 ( .sum( s[35]), .carry( c[35]), .a( s[20]) , .b( c[19]), .cin( s[24]) );
adder_half ha_52 ( .sum( s[40]), .carry( c[40]), .a( s[15]) , .b ( s[29]) );
adder_half ha_53 ( .sum( s[41]), .carry( c[41]), .a( p[7][5]), .b ( s[30]) );
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adder_full fa_61 ( .sum( s[45]), .carry( c[45]), .a( s[36]) , .b( c[35]), .cin( c[24]) );
21
adder_half ha_64 ( .sum( s[52]), .carry( c[52]), .a( p[7][7]), .b ( c[31]) );
adder_full fa_71 ( .sum( s[54]), .carry( c[54]), .a( s[44]) , .b( c[43]), .cin ( c[53]) );
adder_half ha_72 ( .sum( s[63]), .carry( c[63]), .a( c[52]), .b ( c[62]) );
always@(posedge clock, negedge clear)

if(!clear) product <= 16'b0;
else product <= {s[63 : 53],s[42],s[32],s[16],s[0],p[0][0]};
endmodule
MULTIPLIER
22
Booths multiplier:
module multiplier(prod, busy, mc, mp, clk, start);

output [15:0] prod;
output busy;
input [7:0] mc, mp;
input clk, start;
reg [7:0] A, Q, M;
reg Q_1;
reg [3:0] count;
wire [7:0] sum, difference;
always @(posedge clk) begin if (start) begin

A <= 8'b0;
M <= mc;
Q <= mp;
Q_1 <= 1'b0;
count <= 4'b0;
end
else begin
case ({Q[0], Q_1})
2'b0_1 : {A, Q, Q_1} <= {sum[7], sum, Q};

2'b1_0 : {A, Q, Q_1} <= {difference[7], difference, Q};
default: {A, Q, Q_1} <= {A[7], A, Q};
endcase
count <= count + 1'b1;
end
end
alu adder (sum, A, M, 1'b0);

alu subtracter (difference, A, ~M, 1'b1);
assign prod = {A, Q};

assign busy = (count < 8);
endmodule
MULTIPLIER
assign out = a + b + cin;

endmodule
23
modified booths multiplier:

module MBA_module(p,a,b,clock);
output [15:0] p;
input [7:0] a, b;
input clock;
reg [15:0] p,ans;
integer i, lookup_tbl;
integer operate;
initial
begin
p=16'b0;
ans=16'b0;
end
always @(negedge clock)
begin
p=16'b0;
for(i=1;i<=7;i=i+2)
begin
if(i==1)
lookup_tbl = 0;
MULTIPLIER
else
lookup_tbl = b[i-2];
24
lookup_tbl = lookup_tbl + 4*b[i] + 2*b[i-1];
if(lookup_tbl == 0 || lookup_tbl == 7)
operate = 0;
else if(lookup_tbl == 3 || lookup_tbl == 4)
operate = 2;
else
operate = 1;
if(b[i] == 1)
operate = -1*operate;
case(operate)
1:
begin
ans=a;
ans=ans<<(i-1);
p=p+ans;
end
2:
begin
ans=a<<1;
ans=ans<<(i-1);
p=p+ans;
end
MULTIPLIER
-1:
begin
ans=~a+1;
25
ans=ans<<(i-1);
p=p+ans;
end
-2:
begin
ans=a<<1;
ans=~ans+1;
ans=ans<<(i-1);
p=p+ans;
end
endcase
end
end
endmodule
MULTIPLIER
26
BIBLIOGRAPHY:
Currently a lot of research is done on reconfigurable architectures, where the

architecture can be adapted to the applications to be executed. Some of these proposed
architectures can adapt their arithmetic logic units to operate with different bit width,
depending on the application.
1. https://www.slideshare.net/saikiranpanjala/design-and-simulation-of-different-8bit-
multipliers-using-verilog-code
2. http://murali-mm.blogspot.com/2014/06/4-bit-array-multiplier-verilog-code.html
3. https://www.slideshare.net/saikiranpanjala/design-and-simulation-of-different-8bit-
multipliers-using-verilog-code
4. https://www.edaboard.com/showthread.php?233431-structural-8x8-bit-multiplier
5. https://www.youtube.com/watch?v=QFXaddi-Ag8
6. https://www.youtube.com/watch?v=db9-g_nnZSE
MULTIPLIER
27

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MULTIPLIER

MULTIPLICATION ACCLERATION THROUGH BOOTH’S

Kakinada in Partial fulfilment for the award of degree of

ELECTRONICS & COMMUNICATION ENGINEERING

Mr. T.SRIRAM MURTY M.Tech,(ph.D)

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

QIS COLLEGE OF ENGINEERING & TECHNOLOGY

(Approved by AICTE, New Delhi & Affiliated to JNTUK, Kakinada)

With ‘A’ Grade Institution)

VENGAMUKKAPALEM, PONDUR ROAD, ONGOLE-523272, A.P.

QIS COLLEGEOF ENGINEERING AND TECHNOLOGY

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

Signature of the Guide Signature of the HOD

Signature of the External Examiner

We express our gratitude to the Honourable chairman Sri .N. NAGESWARARAO

We express our gratitude to Dr.D.VENKATARAO, Ph.D., Principal of QIS College of

We express our gratitude to the Head of the Department of ECE, Dr.CH.HIMA

G.HIMA SAILA (17495A0410)

5.1.1 Disadvantages ………………………………………………………16

5.2.1 Future scope ……………………………………………………….…..18

Table 3.2.1modified booth encoding table…….……………………..….…..20

Table 5.2.3.1comparision table……………………………………….….….26

Figure2.1.2 Circuit diagram of 2bit multiplier………………….……....…...11

Figure2.2.1Logic diagram of 4 bit multiplier………………….………...….12

Figure2.3.1logic diagram of 8bit multiplier.……………………………..…13

Figure3.2.1Structure of modified booth multiplier……………….………. ..18

Figure4.1.1output waveform of 4bit multiplier………………….……….....21

Figure4.2.1output waveform of 8bit multiplier………………….…...…......21

Figure4.3.1output waveform of booth multiplier……………………….…..22

Figure4.4.1output waveform of modified booth multiplier………...…….....22

This technique can reduce the power dissipation by adapting a multiplier.The

This scheme has several drawbacks:

1.2 Purpose of the project:

1.3 Aim of the project:

The main aim of the project is to developing a code for BOOTH’S

1.4 Scope of the project:

In this project having

1. Generalmultipliers for Signed and unsigned multipliers

2. Booth multiplier for Signed and unsigned multipliers

3. Modified booth multiplier for Signed and unsigned multipliers

2.1 2x2 multiplier:

Figure 2.1.1:2 bit multiplier logic diagram

Thus, we get the partial products as:

Figure2.1.2 circuit diagram of 2bit multiplier

2.2 4x4 multiplier:

Figure2.2.1 structure of 4bit multiplier

2.3 8X8 MULTIPLIER:

2.3.1 Logic diagram of 8bit multiplier

2‘s complement of 13---- 11110011

Then normal multiplication operation can be performed as:

2.Modified booth algorithm

3.1. Booth Multiplication Algorithm:

Booth's multiplication algorithm is a multiplication algorithm that multiplies two

Booth's algorithm involves repeatedly adding one of two predetermined

Determine the two least significant (rightmost) bits of P.

If they are 01, find the value of P + A. Ignore any overflow.

If they are 10, find the value of P + S. Ignore any overflow.

If they are 00, do nothing. Use P directly in the next step.

If they are 11, do nothing. Use P directly in the next step.

Let us consider an example with two unsigned numbers 11*13

11---------- 00001011(m) subtraction => a<=a-m (if 10)

13---------- 00001101(q) addition=> a<=a+m (if 01)

No of Operations done Accumulator content(a) Multiplier(q)

lookup_tbl = lookup_tbl + 4b[i] + 2b[i-1];