Verilog HDL LED Driver Report

VIETNAM NATIONAL UNIVERSITY - HCMC
HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY

FACULTY OF COMPUTER SCIENCE AND ENGINEERING
MINI-PROJECT REPORT
LOGIC DESIGN WITH VERILOG HDL
TOPICS
LED-DRIVERS
Instructor: Ngo Duc Minh

Stud: Doan Tan Loc
Stud: Bui Duc Thach
Stud: Van Chan Duong
HO CHI MINH CITY. NOVEMBER, 2019

Computer Science and Engineering CO2034 - Mini Project Report
Contents
1 Introduction 2
1.1 Why this project? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 The tools used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Design and implementation 4

2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 RTL model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Testing 13
3.1 Test cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Simulating: Part of waveform . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Simulating: Transcript . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4 Conclusion 17
Page 1/17
1 Introduction
Our project implements a system that display the LED lights in different modes and
patterns. The system consists of 17 red LED (LEDR) with specified switches (SWs) for
mode selecting and running speed adjusting.
1.1 Why this project?

The needs of applying the knowledge we had learned so far in this subject motivated us
to choose this project. While the result seems simple but the implementation behind
should include what we learned in this specific subject. Our implementations gave us
more appreciation for the profound complexities found in todays modern devices. This
project changed us.
1.2 Problem
Design and implement a LED-driver with 6 different types and variations (states):
Reset
6 2
5 3
Figure 1: LED-Driver
Where:
• State 1: Two LEDs run (active) from left to right.
• State 2: Three LEDs run from right to left.
• State 3: LEDs running and blinking from middle to two sides.
• State 4: All LEDs turned on, then turn off LEDs from two sides to the middle.
• State 5: LEDs run from left to right, when all LEDs are active, turn-off the LEDs one
by one from right to left.
• State 6: LEDs run from right to left, when all LEDs are active, turn-off the LEDs one
by one from left to right.
Page 2/17
There are 4 modes:
1. State are transition in default (Figure 1).
2. Odd-state only (1 → 3 → 5 → back to 1).
3. Even-state only (2 → 4 → 6 → back to 2).
4. Use SWs to choose state.
1.3 The tools used

1. DE2i-150 FPGA Development Kit
2. Intel
c
Quartus
c
Prime 17.1 Lite Edition
Page 3/17
2 Design and implementation

2.1 Block Diagram
Main module: LEDDriver
Mode 1
7-Segment LED
Mode 2
Clock Divider
7-Segment LED LED multiplexer

Mode chooser
Mode 3
LEDR
7-Segment LED
Mode 4
7-Segment LED
Figure 2: LED-Driver block diagram
This module includes 9 sub-module. The Modes represent each mode that the LED-
Driver has. The Clock Divider create a pulse that has its frequency changed using 4 SWs.
The 7-Segment LED display the current states of each mode. The Mode chooser indicate
what mode will be running using 3 SWs. The LED multiplexer displays the mode’s LED
which was chose by the Mode chooser.
Page 4/17
Sub module 1: Mode1
State 1
State 2
State 3
LED Chooser LEDR
State 4
State 5
State 6
Figure 3: Mode 1 block diagram
This module includes 7 sub-module. 6 State modules cycling using Finite State Machine
(FSM) showing their LEDs to the LED chooser to pick and let it show on to the LEDR.
Page 5/17
Sub module 2: Mode2
State 1
State 3 LED Chooser LEDR
State 5
Sub module 3: Mode3
State 2
State 4 LED Chooser LEDR
State 6
These two modules include 4 sub-module. 3 State modules cycling using Finite State
Machine (FSM) showing their LEDs to the LED chooser to pick and let it show on to the
LEDR with cycling order of 1 → 3 → 5 and 2 → 4 → 6 relatively for Mode 2 and Mode 3.
Page 6/17
Sub module 4: Mode4
State 1
State 2
State 3
State Chooser LED Chooser LEDR
State 4
State 5
State 6
This module includes 8 sub-module. The States are selected with State Chooser mod-
ules using indicated SWs. Then States’ LEDs then be chosen by the LED Chooser module
to appear on the Mode 4’s LEDR.
Page 7/17
Figure 7: LED Driver RTL model
Main module: LEDDriver
RTL model
2.2
Page 8/17
Figure 8: Mode 1 RTL model
Sub module 1: Mode1
Page 9/17
Sub module 2: Mode2
Page 10/17
Sub module 3: Mode3
Page 11/17
Sub module 4: Mode4
Page 12/17
3 Testing
3.1 Test cases
The test cases are demonstrated as Test bench file below:
`timescale 1ps/1ps
module LEDdriver_tb ();
reg clk;
reg [1:0]mode_sel;
reg [2:0]state_sel;
reg reset;
reg [8:0]sw;
wire [3:0] clock_sel = 4'b1111;
wire [17:0]ledr;
wire [6:0]hex0, hex1, hex2, hex3, hex4;
//[1:0]SW: mode selector,
//[4:2]SW: state selector for mode 4,
//[8:5]SW: Select clock divider
LEDdriver UUT (.CLOCK_50(clk),

.SW(sw),
.KEY0(reset), //asynchronous reset
.LEDR(ledr),
.HEX0(hex0),
.HEX1(hex1),
.HEX2(hex2),
.HEX3(hex3),
.HEX4(hex4));
always begin
#5 clk = !clk;
sw = {clock_sel,state_sel,mode_sel};
end
initial begin
$monitor ("led = %b, mode: %b, state in mode4: %b, sm1: %b, sm2: %b, sm3:
%b, sm4: %b", ledr, hex0, state_sel, hex1, hex2, hex3, hex4);
reset = 1;
clk = 0;
mode_sel = 0;
state_sel = 0;
#10 reset = 0;
#10 reset = 1;
#200 mode_sel = 2;
#200 mode_sel = 1;
#200 mode_sel = 3;
#100 state_sel = 1;
$stop;
end
endmodule
Page 13/17
Figure 12: Waveform window
Simulating: Part of waveform
3.2
Page 14/17
Figure 13: Transcript window
Simulating: Transcript
3.3
Page 15/17
3.4 Result
The project’s results:
Figure 14: Mode 1 - State 3 running
For full demonstration please use this Youtube URL: https://youtu.be/MssNMzh5w2Y
Page 16/17
4 Conclusion
The design is able to switch and display between different modes (Mode 1 through 4) and
states (Mode 4 exclusively). The speed for displaying the LEDs can be adjusted using 4
SWs [8:5] on the DE2i-150. The 7-segments LEDs indicate which modes and states are
running.
The design’s advantages and disadvantages:
1. Advantages:
- Easy to operate.
- User-friendly interface (kind of).
2. Disadvantages:
- Complex implementation.
Further intention: Will take advantages of using 16x2 LCD display for displaying the info
and maybe will find ways to come up with a more simple states implementation.
Page 17/17

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VIETNAM NATIONAL UNIVERSITY - HCMC

HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY

LOGIC DESIGN WITH VERILOG HDL

Instructor: Ngo Duc Minh

HO CHI MINH CITY. NOVEMBER, 2019

2 Design and implementation 4

1.1 Why this project?

• State 2: Three LEDs run from right to left.

• State 3: LEDs running and blinking from middle to two sides.

There are 4 modes:

1. State are transition in default (Figure 1).

2. Odd-state only (1 → 3 → 5 → back to 1).

3. Even-state only (2 → 4 → 6 → back to 2).

4. Use SWs to choose state.

1.3 The tools used

2 Design and implementation

7-Segment LED LED multiplexer

Figure 2: LED-Driver block diagram

Sub module 1: Mode1

LED Chooser LEDR

Figure 3: Mode 1 block diagram

Sub module 2: Mode2

State 3 LED Chooser LEDR

Figure 4: Mode 2 block diagram

Sub module 3: Mode3

State 4 LED Chooser LEDR

Figure 5: Mode 3 block diagram

Sub module 4: Mode4

State Chooser LED Chooser LEDR

Figure 6: Mode 4 block diagram

LEDdriver UUT (.CLOCK_50(clk),

Figure 14: Mode 1 - State 3 running

Figure 15: Mode 1 - State 5 running

Figure 16: Mode 1 - State 1 running

For full demonstration please use this Youtube URL: https://youtu.be/MssNMzh5w2Y

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