Introduction to CMOS VLSI

Design
 What is a transistor?
A transistor is a 3 terminal electronic device made of semiconductor material.
Transistors have many uses, including amplification, switching, voltage
regulation, and the modulation of signals
The word “transistor” is a combination of the terms “transconductance” and
“variable resistor”
 Transistor Types

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Bipolar Junction Transistors (BJT)

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Metal Oxide Semiconductor Field Effect
Transistors (MOSFET)
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Operating principles
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– Both are completely different.
Electrical Characteristics –
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Have some similarities.
 BJT
NPN or PNP silicon structure.
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Small current into very thin base layer controls large currents
between emitter and collector.
Current controlled device.
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Disadvantages :
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Width is decided by technology so we can't change it during
design.
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I-V characteristics can be optimized only by varying the emitter
area.
Base Current limits integration Density.
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 MOSFET
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Voltage applied to insulated gate controls current between source and
drain.
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Voltage controlled current device.
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Depletion type and Enhancement type. Both are having N-channel and P-
channel device.
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Mostly we use Enhancement type.
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At VGS = 0V,
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Enhancement type → No Conduction.
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Depletion type → Conducts Current.
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Advantages over BJT :
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Width and Length can be varied during the design.
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Channel length modulation can be minimized by increasing the length.
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 MOSFET

Four terminals: Gate, Source,Drain, Body (= Bulk = Substrate)

 NMOS Operation

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To keep source and drain junction diodes in reverse biased, body is
commonly tied to ground (0 V).
Source and drain are interchangeable.
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Cont.
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Mode of Operation :
(Keep drain and source potential as 0V and vary the gate potential)
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➢
Accumulation mode
➢
Depletion mode
➢
Inversion mode
➢
 12

Operating 10

modes
8

a) Accumulation
VGS < 0V 6
Column 1
Column 2
Column 3

b) Depletion 4

VT > VGS > 0V

c) Inversion
VGS > VT 0
Row 1 Row 2 Row 3 Row 4
PMOS Transistor
Switch model of NMOS transistor
Switch model of PMOS transistor
 Electric Fields in the MOSFET
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Transverse field :
Potential difference between the conductive gate and the substrate.
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Supports the substrate depletion region and inversion layer .

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Lateral field :
Due to a non-zero source to drain potential.
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Main mechanism for current flow in the MOSFET.

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NMOS – Operating region

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Cut off region
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Linear region
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Saturation region
 Cut off region

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With VGS < VT , no inversion layer
present under the surface
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At VDS = 0, the source and drain
depletion regions are symmetrical
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A positive VDS reverse biases the
drain substrate junction, hence the
depletion region around the drain
and in channel widen.
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No current flows even for VDS > 0,
since there is no conductive
channel between the source and
drain
 Linear region
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With VGS > VT , a conductive
channel forms under the surface- a
non-zero transverse field is present
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ID is zero for VDS = 0 since no
lateral field is present.
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Increasing VDS increases the
lateral field in the channel and
hence the current
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Increasing VGS increases the
transverse field and hence the
inversion layer density, which also
increases the current
Saturation region
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The point at which the inversion
layer density becomes very
small(essentially zero) at the drain
end is termed pinch-off.
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The value of VDS at pinch-off is
denoted VDS,sat.
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Since the drain end channel
density has become small, the
current is much less dependent on
VDS.
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But is still dependent on VGS ,
since increased VGS still increases
the inversion layer density.
 MOSFET ID -VDS Characteristic
For VGS < VT , ID = 0.
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As VDS increases at a fixed VGS ,
ID increases in the triode region
due to the increased lateral field,
but at a decreasing rate since the
inversion layer density is
decreasing.
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Once pinch-off is reached,
further VDS increases only
increase ID due to the formation
of the high field region.
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The device starts in triode, and
moves into saturation at higher
VDS.
 MOSFET ID -VGS Characteristic
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As ID is increased at fixed VDS , no
current flows until the inversion layer is
established.
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For VGS slightly above VT the device
is in saturation since there is little
inversion layer density (the drain end is
pinched off).
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As VGS increases, a point is reached
where the drain end is no longer
pinched off, and the device is in the
triode region.
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A larger VDS value postpones the
point of transition to triode.
 Complementary MOS (CMOS)
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CMOS are transistor circuits formed from a combination of NMOS and
PMOS devices in the same circuit.
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It accomplishes current reduction by complementing every NMOS with a
PMOS and connecting both gates and both drains together.
This arrangement greatly reduces power consumption and heat generation.
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But during the switching time both MOS conduct briefly. This induces a brief
spike in power consumption.
Cont..
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CMOS logic gates comprises a pull-up(PUN) and pull-down(PDN)
networks.
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PUN → PMOS transistors.
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PDN → NMOS transistors.
No. of transistors in the PUN and PDN is equal to the no. of inputs.
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For logic 0 outputs the PDN connects the output to gnd and the
PUN is an open circuit.
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For logic 1 outputs the PUN connects the output to VDD and the
PDN is an open circuit.
Pull-up network is complement of pull-down.
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Parallel -> series, series -> parallel.

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 CMOS Inverter

When Vin = 0,
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Vout → VDD
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When Vin = VDD,

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Vout → 0
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Cont.
CMOS NOR

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When any of the inputs is high, at
least one of the NMOS transistors
is closed.
Output is connected to the gnd.
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If both inputs are low, both PMOS
transistors are closed.
Output is connected to VDD.
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CMOS NAND

When both inputs are high, both

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NMOS transistors are closed.

Output is connected to gnd.
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When any of the inputs is low, at
least one of the PMOS transistors
is closed
Output is connected to VDD.
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 CMOS Pass Transistor

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NMOS pass transistor passes a strong
0 and a weak 1.
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PMOS pass transistor passes a strong
1 and a weak 0.
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Combine the two to make a CMOS
When C = 0
pass gate which will pass a strong 0
Open Circuit and a strong 1.
When C = 1,
OUT = IN.