1.

When both nMOS and pMOS transistors of CMOS logic gates are ON, the output is :
Crowbarred or Contention
2. When both nMOS and pMOS transistors of CMOS logic gates are OFF the output is :
High Impedance or Floating
3. In CMOS logic circuit, the switching operation occurs because:
N-MOSFET transistor turns ON, and p-MOSFET transistor turns OFF for input ‘1’ and N-
MOS transistor turns OFF, and p-MOS transistor turns ON for input ‘0’
4. In CMOS logic circuit the p-MOS transistor acts as: Pull Up Network
5. In CMOS logic circuit the n-MOS transistor acts as: Pull Down Network
6. The electrical equivalent component for MOS structure is: Capacitor
The MOS structure acts as a capacitor with metal gate and semiconductor acting as
parallel plate conductors and oxide as dielectric between them.
7. The Fermi potential is the function of: The Fermi potential, which is a function of
temperature and doping, denotes the difference between the intrinsic Fermi level and the
Fermi level.
8. The direction of electric field when the gate voltage is zero: Metal to Semiconductor
Metal being more positive compared to semiconductor.. Electric field exists from metal to
semiconductor.
9. When gate voltage is negative for enhancement mode n-MOS, the direction of electric
field will be: Semiconductor to Metal
When gate voltage is negative, holes in substrate are attracted towards surface creating
electric field from semiconductor to metal.
10. At threshold Voltage, the surface potential is: -Fermi Potential
When surface potential reaches –fermi potential, the surface inversion occurs. The gate
voltage which brings these changes is known as threshold voltage.
11. Surface inversion occurs when gate voltage is: Equal to Threshold Voltage
12. For enhancement mode n-MOSFET, the threshold voltage is: Greater Than Zero or
Positive Quantity
13. The threshold voltage depends on: The threshold voltage depends on: The work function
difference between gate and channel, The gate voltage component to change surface
potential, The gate voltage component to offset the depletion charge and fixed charges in
gate oxide
NOISE MARGIN
14. Noise Margin is amount of noise the logic circuit can withstand, it is given by difference
between VOH and VIH or VIL and VOL
15. The VIL is found from transfer characteristic of inverter by: The slope of the transition at a
point at which the slope is equal to -1
16. The VIH is found from transfer characteristic of inverter by: The slope of the transition at
a point at which the slope is equal to -1
17. The Lower Noise Margin is given by: VIL – VOL
18. The Higher Noise Margin is given by: VOH – VIH
19. The Uncertain or transition region is between: VIH and VIL
20. The noise immunity _______Increases_____ with noise margin. Noise Immunity is
directly proportional to noise margin
21. If VIL of the 2nd gate is higher than VOL of the 1st gate, then logic output 0 from the 1st
gate is considered as : Logic Input 0
22. If VIL of the 2nd gate is lower than VOL of the 1st gate, then logic output 0 from the 1st
gate is considered as : Uncertain
23. Input Voltage between VIL and VOL is considered as: Logic Input 0
24. If VIH of the 2nd gate is higher than VOH of the 1st gate, then logic output 0 from the 1st
gate is considered as : Uncertain
25. Noise margin of CMOS is : Better than ECL and TTL
 Noise in VLSI circuits mean: Unknown signal that limits the minimum signal level that a
circuit can process with acceptable quality.
26. In probability Noise is described as : Random Process
27. Noise generated by independent devices are: Noise generated by independent devices
are uncorrelated, eg: noise generated from resistor is not similar to noise generated from
transistor.
28. Thermal noise is generated from: Thermal noise is due to random motion of electrons in
a conductor.
29. Thermal noise is generated from MOSFET by: Conduction of Charge Carriers in the
Channel
30. Thermal noise current in the MOSFET is proportional to: Transconductance
31. Flicker noise is found in MOSFET at: Gate Oxide and Silicon Interface
32. Flicker noise originate due to: Dangling Bonds
33. The average power of flicker noise depends on: cleanness of the oxide silicon interface
34. If VIH of the 2nd gate is lower than VOH of the 1st gate, then logic output 0 from the 1st
gate is considered as : Logic Input 1
35. Input Voltage between VIH and VOH is considered as: Logic Input 1
36. The n-MOS invertor is better than BJT in terms of: Fast Switching Time, Low Power
Loss, Smaller Overall Layout Area
37. The n-MOS invertor consists of n-MOS transistor as driven and resistor or depletion
mode n-MOS or enhancement mode n-MOS at the pull up load.
38. If the n-MOS and p-MOS of the CMOS inverters are interchanged the output is measured
at: When the transistors are interchanged, The drain of n-MOS is connected to supply
voltage, drain of p-MOS is connected to ground . The output is measured at source of
both the transistors.
39. The n-MOS invertor is better than BJT in terms of: Fast Switching Time, Low Power
Loss, and Smaller Overall Layout Area
40. The n-MOS invertor consists of n-MOS transistor as driven and Resistor as a load,
Depletion mode n-MOS as a load. Enhancement mode n-MOS as a load
41. What will be the effect on output voltage if the positions of n-MOS and p-MOS in CMOS
inverter circuit are exchanged? Output is reversed
42. The average power dissipated in resistive load n-MOS inverter is: When the input voltage
is equal to VOH on the other hand, both the driver MOSFET and the load resistor
conduct a nonzero current. Since the output voltage in this case is equal to VOL, DC
power consumption of the inverter can be estimated as VDD.(VDD-VOL)/2R
43. The depletion mode n-MOS as an active load is better than enhancement load n-MOS in:
Sharp VTC transition and better noise margins. Single power supply. Smaller overall
layout area
44. The enhancement mode n-MOS load inverter requires 2 different supply voltages to:
Keep Load Transistor in Linear Region
45. The CMOS inverter consist of: Enhancement mode p-MOS transistor and enhancement
mode n-MOS transistor
46. In the CMOS inverter the output voltage is measured across: Drain of n-MOS transistor
and ground
47. When the input of the CMOS inverter is equal to Inverter Threshold Voltage Vth, the
transistors are operating in: Both the transistors are in saturation region
48. The switching threshold voltage VTH for an ideal inverter is equal to: (VDD)/2
MOS TRANSISTOR 1
49. The conductivity of the pure silicon is raised by : Introducing Dopants
50. The n-type semiconductor have _______ as majority carriers : Electrons
51. The majority carriers of p-type semiconductor are : Holes
52. The n-MOS transistor is made up of: N-type source, n-type drain and p-type bulk
53. The oxide layer formed in the MOSFET is : Silicon Dioxide
54. The drain current is varied by: Gate to Source Voltage
55. The low voltage on the gate of p-MOSFET forms : Channel of Positive Carriers
56. The n-MOSFET is working as accumulation mode when: When the negative voltage is
applied to the gate, there develops a presence of negative charge on the gate. The
mobile positively charged holes are attracted to the region beneath the gate. This
explains the formation of accumulation mode.
57. The current through the n-MOS transistor will flow when: Vgs > Vtreshold, Vds>0
58. The p-MOS Transistor is said to be in Saturation mode when: Vdsp < Vgsp – Vtp and
Vgsp < Vtp.
59. The principle of the MOSFET operation is: Control the conduction of current between the
source and the drain, using the potential difference applied at the gate voltage as a
control variable.
60. The conduction of current IDS depends on:
Gate to source voltage
Drain to source voltage
Bulk to source voltage
Threshold voltage
Dimensions of MOSFET
61. The impedance at the input of n-MOS transistor circuit is : Greater than BJT Transistor
62. The depletion mode n-MOS differs from enhancement mode n-MOS in: Threshold
Voltage. If n-MOS operates with negative threshold voltage then it is in depletion mode. If
n-MOS operates with positive threshold voltage then it is in enhancement mode.
63. Which contribute to the wiring capacitance? Fringing fields, Interlayer Capacitance,
Peripheral Capacitance.
64. What does the value d in fringing field capacitance measures? Wire and Substrate
Separation.
65. Total wire capacitance is equal to area capacitance + fringing field capacitance
66. Interlayer capacitance occurs due to : Interlayer capacitance occurs due to parallel plate
effect between one layer and another. When one capacitance value comes closer to
another they create some combined effects
67. Which capacitance must be higher? Metal to polysilicon capacitance should be higher
than metal to substrate capacitance. This is due to that when one layer underlies the
other and in consequence interlayer capacitance is highly dependent on layout.
68. Peripheral capacitance is given in _____ eper unit length Pico Farads. This is the
sidewall capacitance. Each diode has this side wall capacitance.
69. For greater relative value of peripheral capacitance, _______ should be small. Source
Area and Drain Area
70. Diffusion capacitance is equal to area capacitance + peripheral capacitance
71. Polysilicon is suitable for Small Distance: Polysilicon is unsuitable for routing Vdd or Vss
other than for very small distance because of the relatively high Rs value of the
polysilicon layer.
72. Which has high voltage drop? Polysilicon layer has high voltage drop. It has moderate
RC product.
73. Which layer has high capacitance value? Diffusion or active layer has high capacitance
value due to which it has low or moderate IR drop.
74. Which layer has high resistance value? Polysilicon layer has high resistance value and
due to this it has high IR drop.
75. z