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Design Activities assigned under The Clustered Project

Air Quality Monitoring System


Department of Electronics and Communication Engineering

National Institute of Technology Nagaland

SMDP-C2SD 2 November 2016

 We have been assigned with two design activities by
Resource Centre which is a part of the clustered project
“Building a prototype of air quality monitoring system
based on FPGA/ASIC platform”.
 In this regard we have been allotted with the following
design activities:
o Design of sensor interfacing circuitry
o Design of DMA Controller for processor

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Objective-Design Activity I
 Design Activity I : Design of sensor interfacing circuitry
 The aim of the design activity is to develop a low power
technique to interface the sensor data from the output of
 The design activity deals with the development of sensor
interfacing module through I2C communication protocol.
 In this regard an I2C compatible ADC module will be
utilized for serving the purpose.
 An interfacing module will be developed to communicate
the ADC module to the FPGA board

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Block diagram of sensor interfacing


Basic building block of the proposed design activity sensor interfacing circuitry

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Objective-Design Activity II
 Design Activity II : Design of DMA Controller for
 The aim of the design activity is to develop a
programmable Direct Memory Access (DMA) Controller
for the Processor.
 DMA is an I/O technique used for high speed data
transfer between and memory and peripherals.
 In DMA technique, the processor releases the control of
the buses to a device called DMA controller. Then, the
controller manages data transfer between the memory
and the peripheral under its control by bypassing the

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Block diagram of DMA Controller

Basic building block of the proposed design activity DMA


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Sensor Module specifications
CO CO2 NO2 Temperature and Humidity
(MQ 7) (MG 811) (MiCS-2710) (DHT 11)

Sensing layer: SnO2 Sensing element: NTC (Temp.)

Sensor layer/type Resistive
Sensor Type: Resistive Solid Electrolyte Resistive(Humidity)

Temp: 0-50°C
Range 0-2000 ppm 350-10000 ppm 0.05-5 ppm

Supply Voltage 5V 6 V±0.1 V 5V 5V

5.5 mW(Avg)
Power consumption About 350 mW < 1200 mW <50 mW
13.75mW (Max.)

Sensitivity 1.23 mV/ppm 25uV/ppm 1.3025 KΩ/ppb ± 2 °C

Temp:6-30 s
Response time <10 s <120 s < 30 s
Humidity:6-15 s

Operating Temperature -20 to -50 °C -20 to 50 °C -35 to 85 °C -2 to 40 °C

Interface Analog Analog Analog Serial Digital
Compatible Programmable Standard Standard
Standard MCUs/FPGA Standard MCUs/FPGA
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ADC Specification
Parameters AD7991
Supply Voltage, Vdd 2.7V to 5.5V
Number of Bits 12 ADC with fast conversion time: 1
μs typical
Channels 4 analog input channels/3 analog
input channels with reference input
Interface I2C compatible serial interface
supports standard, fast, and High-
speed modes
Power consumption 1.38mW(Fully operational)
Positive reference voltage, Vref+ 2.5V
Type SAR
Clock frequency 3.4 MHz
Operating temperature −40°C to 125°C

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Processor Specification
Parameters Basys 3 Artix-7 FPGA Board
I-V ratings (Voltage/Current)
FPGA Board-5V(External)
FPGA I/O,USB Ports,Clocks,Flash,PMODS-3.3V, 2A/0.1 to
FPGA Core-1.0V,
2A/0.2 to 1.3A
FPGA Auxiliary and Ram-1.8V,
300mA/ 0.05 to 0.15A
Architecture 33,280 Logic Cells
5,200 Slices CLBs
400 Distributed RAM
90 DSP Slices
5 CMT(each with 1MMCM and 1PLL)
5 I/O Banks
250 Max user I/O
Frequency 100 MHz
Internal clock speeds exceeding 450MHz
Memory 100(18kb)Block RAM
50 (36kb)Block RAM
1,800 Max(Kb)
Physical Dimensions 49 x 75.2 mm
I/O Pins 1 XADC
5 I/O Banks
250 Max user I/O
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External Memory and Display
Parameters Specification
Supply Voltage 3.3V
Size 32Mbit non-volatile serial Flash device
(on board)
16Mbit of non-volatile serial Flash memory
Interface SPI Interface
Speed Normal READ (Serial): 40 MHz clock rate
Quad I/O FAST_READ: 80 MHz clock rate
Or 40 MB/s effective data rate
External Memory Specification

Parameters Specification
Supply Voltage 3.3V
Type and Interface 16×2 character LCD with parallel interface
192 predefined characters including 93
Number of character ASCII characters
Up to 8 user-definable characters
Power Consumption Low power operation
Display Specification
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Current Project Status
 Finalization and detailed specification of the hardware
resources to be utilized for the SMDP-C2SD project.
 Procurement of Hardware Resources is in process.
 Finalization of the overall block diagram and sub-modules
for both the projects.
 Initial FPGA implementation of submodules of the I2C
and DMA core is in development.

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