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SRI VENKATESWARA COLLEGE OF ENGINEERING

COURSE DELIVERY PLAN - THEORY Page 1 of 8

LP: EC6302
Department of Electronics and Communication Engineering
Rev. No: 01
B.E/B.Tech/M.E/M.Tech : BE Regulation:2013 Date: 30/06/2015
PG Specialisation : NOT APPLICABLE
Sub. Code / Sub. Name : EC6302- DIGITAL ELECTRONICS
Unit : I
Unit Syllabus: MINIMIZATION TECHNIQUES AND LOGIC GATES
Minimization Techniques: Boolean postulates and laws – De-Morgan’s Theorem - Principle of Duality -
Boolean expression - Minimization of Boolean expressions –– Minterm – Maxterm - Sum of Products (SOP) –
Product of Sums (POS) – Karnaugh map Minimization – Don’t care conditions - Quine-McCluskey method of
minimization.
Logic Gates: AND, OR, NOT, NAND, NOR, Exclusive–OR and Exclusive–NOR- Implementations of Logic
Functions using gates, NAND–NOR implementations – Multi level gate implementations- Multi output gate
implementations. TTL and CMOS Logic and their characteristics – Tristate gates.
Objective: To introduce basic postulates of Boolean algebra and show the correlation between Boolean expressions. To
introduce the methods for simplifying Boolean expressions.
Session Topics to be covered Ref Teaching
No. Method
1. Introduction to Digital Electronics, Boolean 1 – Ch.2;Pg.39 – 46 PPT
postulates and laws, De-Morgan’s Theorem.
2. Principle of duality, Minimization of expressions 1 – Ch.2;Pg.41 - 44 PPT
using Boolean laws.
3. Minterm, Maxterm, Sum of Products (SOP), 1 – Ch.2;Pg.46 - 50 PPT,BB
Product of Sums (POS).
4. Minimization of expressions using Karnaugh map- 1 – Ch.3;Pg.67 -79 PPT,BB
3&4 variable K-map.
5. 5-variable K-map, K-map with don’t care 1 – Ch.3;Pg.79 -87 PPT,BB
conditions.
6. Quine-McCluskey method of minimization. 1 – Ch.3;Pg.112 - 120 PPT,BB

7. Truth table, symbol and expressions of AND, OR, 1 – Ch.2;56 PPT,BB

NOT, NAND, NOR, Ex–OR and Ex–NOR.

8. Implementation of logic function using Universal 1 – Ch.3;Pg.87 - 98 PPT

gates, Multi level-output gate implementations.

9. Characteristics of TTL and CMOS Logic, Tristate 1 – Ch.10;Pg.498 - 597 PPT

gates. 1 – Ch.10;Pg.512 - 515

10. Tutorial 1 PPT

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COURSE DELIVERY PLAN - THEORY Page 2 of 8

Content beyond the Syllabus

Introduction to Number systems
Course Outcome 1:
Students will be able to Analyze different methods used for simplification of Boolean expressions.
* Session duration: 50 minutes
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COURSE DELIVERY PLAN - THEORY Page 3 of 8

Sub. Code / Sub. Name: EC6302- DIGITAL ELECTRONICS

Unit : II

Unit Syllabus : COMBINATIONAL CIRCUTS

Design procedure – Half adder – Full Adder – Half subtractor – Full subtractor - Parallel binary adder,
parallel binary Subtractor – Fast Adder - Carry Look Ahead adder – Serial Adder/Subtractor - BCD adder –
Binary Multiplier – Binary Divider - Multiplexer/ Demultiplexer – decoder - encoder – parity checker –
parity generators - code converters - Magnitude Comparator.
Objective: To outline the procedures for the analysis and design of combinational circuits.

Session Topics to be covered Ref Teaching

No. Method
11. Design of half adder and full adder. 1 – Ch.4;Pg.143-146 PPT

12. Design of half subtractor, full subtractor and parallel 1 – Ch.4;Pg.150-154 PPT,BB
binary adder/subtractor.
13. Disadvantages of parallel adder, Carry lookahead adder 1 – Ch.4;Pg.147-150 PPT,BB

14. Design of serial adder/subtractor and BCD adder. 1 – Ch.6;Pg.258-261 PPT

1 – Ch.4;Pg.155-157

15. Binary multiplier and binary divider. 1 – Ch.4;Pg.158-159 PPT

CAT-I

16. Design and implementation of Multiplexer and 1 – Ch.4;Pg.168-173 PPT,BB

Demultiplexer.
17. Encoder and decoder, Odd, Even: Parity generators and 1 – Ch.4;Pg.162-168 PPT,BB
checker. 1 – Ch.3;Pg.102-105

18. Code converters. 1 – Ch.4;Pg.140-142 PPT,BB

19. 2-bit, 4-bit Magnitude comparator. 1 – Ch.4;Pg.160-161 PPT,BB

20. Tutorial 1 PPT

Content beyond the Syllabus

BCD to Seven Segment Decoder
Course Outcome 2:
Students will be able to Design and implement Combinational circuits.

* Session duration: 50 mins

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COURSE DELIVERY PLAN - THEORY Page 4 of 8

Sub. Code / Sub. Name: EC6302- DIGITAL ELECTRONICS

Unit : III

Unit Syllabus : SEQUENTIAL CIRCUITS

Latches, Flip-flops - SR, JK, D, T, and Master-Slave – Characteristic table and equation –Application table
– Edge triggering – Level Triggering – Realization of one flip flop using other flip flops – serial
adder/subtractor- Asynchronous Ripple or serial counter –Asynchronous Up/Down counter - Synchronous
counters – Synchronous Up/Down counters – Programmable counters – Design of Synchronous counters:
state diagram- State table –State minimization –State assignment - Excitation table and maps-Circuit
implementation - Modulo–n counter, Registers – shift registers - Universal shift registers – Shift register
counters – Ring counter – Shift counters - Sequence generators.
Objective: To outline the formal procedures for the analysis and design of sequential circuits.

Session Topics to be covered Ref Teaching

No. Method

21. Latches, Characteristic table and equation of SR, JK, 1 – Ch.5;Pg.199-204, PPT
D and T flip flop. 206-208

22. Level triggering and edge triggering of flip flop. 1 – Ch.5;Pg.204-206 PPT

23. Realization of one flip flop using other flip flops, 8 – Ch.7;Pg.278-286 PPT
Master-Slave flip flop. 6 – Ch.8;Pg.412-414
24. Asynchronous: ripple counter, Up/Down counter. 1 – Ch.6;Pg.268-270 PPT,BB
8 – Ch.8;Pg.304-305

25. Synchronous: Up/Down counters, Programmable 1 – Ch.6;Pg.282-284 PPT,BB

counters. 8 – Ch.8;Pg.310-311

26. State diagram, minimization and State assignment. 1 – Ch.5;Pg.210-214 PPT,BB

Excitation table and maps.
27. Design of Modulo-n counter. 1 – Ch.5;Pg.245-246 PPT

28. Tutorial 1&8 PPT

29. Shift registers, SISO, SIPO, PISO, PIPO ,Universal 8 – Ch9;Pg.346-360, PPT/ICT
shift registers 10

30. Shift register counters, ring counter and shift counter. 8 – Ch9;Pg.362-372, PPT/ICT
10
31. Design of sequence generators. 8 – Ch9;Pg.373-378 PPT

Content beyond the Syllabus

State Assignment
Course Outcome 3:
Students will be able to Design and implement Sequential circuits.
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COURSE DELIVERY PLAN - THEORY Page 5 of 8

* Session duration: 50 mins

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COURSE DELIVERY PLAN - THEORY Page 6 of 8

Sub. Code / Sub. Name: EC6302- DIGITAL ELECTRONICS

Unit : IV

Unit Syllabus : MEMORY DEVICES

Classification of memories – ROM - ROM organization - PROM – EPROM – EEPROM – EAPROM, RAM
– RAM organization – Write operation – Read operation – Memory cycle - Timing wave forms – Memory
decoding – memory expansion – Static RAM Cell-Bipolar RAM cell – MOSFET RAM cell – Dynamic
RAM cell –Programmable Logic Devices – Programmable Logic Array (PLA) - Programmable Array Logic
(PAL) - Field Programmable Gate Arrays (FPGA) - Implementation of combinational logic circuits using
ROM, PLA, PAL.
Objective: To introduce the concept of memories and programmable logic devices.

Session Topics to be covered Ref Teaching

No. Method
32. Classification of memories- ROM, RAM 2 – Ch10;Pg.857-864 PPT

33. ROM Organisation - PROM, EPROM, 5-Ch12;Pg.388-394 PPT,BB

EEPROM,EAPROM
34. RAM organization, - Write and Read operation, 2 – Ch10;Pg.880-886 PPT
Memory cycle and Timing wave forms.
35. Memory decoding and memory expansion. 8 – Ch10;Pg.423-429 PPT,BB

CAT II

36. Static RAM Cell, Bipolar RAM cell , 6-Ch 12;Pg.622-623 PPT
Dynamic RAM Cell and MOSFET RAM cell. 6-Ch 12;Pg.628-633

37 Introduction to Programmable Logic Devices. 1 – Ch.7;Pg.322-330 PPT

38 Implementation of combinational logic circuits 1 – Ch.7;Pg.331-336 PPT

using ROM, PLA, PAL.

39 Field Programmable Gate Arrays (FPGA). 1 – Ch.7;Pg.339-344 PPT,BB

Content beyond the Syllabus

Sequential Programmable Logic Device and Complex Programmable Logic Device.
Course Outcome 4:
Students will be able to To study the various types of memory devices and PLD.

* Session duration: 50 mins

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COURSE DELIVERY PLAN - THEORY Page 7 of 8

Sub. Code / Sub. Name: EC6302- DIGITAL ELECTRONICS

Unit : V

Unit Syllabus : SYNCHRONOUS AND ASYNCHRONOUS SEQUENTAL CIRCUITS

Synchronous Sequential Circuits: General Model – Classification – Design – Use of Algorithmic State
Machine – Analysis of Synchronous Sequential Circuits
Asynchronous Sequential Circuits: Design of fundamental mode and pulse mode circuits – Incompletely
specified State Machines – Problems in Asynchronous Circuits – Design of Hazard Free Switching circuits.
Design of Combinational and Sequential circuits using VERILOG.
Objective: To introduce the concept of synchronous and asynchronous sequential circuits and to design
Combinational and Sequential circuits using VERILOG.

Session Topics to be covered Time Ref Teachin

No. (minutes) Method
40. General sequential Model – Classification and 50 7-Ch:7;Pg.367-371 BB/PPT
design of synchronous sequential circuit.
41 Analysis of Synchronous Sequential circuit. 50 7-Ch:7;Pg.371-380 BB/PPT

42 Algorithmic State Machines and design problem. 50 7-Ch:8;Pg.444-468 BB/PPT

43 Design of fundamental mode and design problem 50 3-Ch.8;Pg.442- BB/PPT

444,465-470

44. Design of Pulse mode and design problem 50 3-Ch.8;Pg.442-444 PPT

463-465
45. Problems in Asynchronous Circuits - Hazards and 50 4-Ch.26;Pg.657-668 PPT
types of hazards.
46. Design of Hazard free Switching circuits. 50 3-Ch.4;Pg.234-236 PPT

47. Design of Combinational and Sequential circuits 50 1-Ch.4;Pg.174-189,10 PPT/ICT

using Verilog.
48. Design of Combinational and Sequential circuits 50 1-Ch.45;Pg.221- PPT/ICT
using Verilog. 233,10
CAT - III. 90

Content beyond the Syllabus

Mixed Operating Mode Asynchronous Circuits
Course Outcome 5:
Students will be able to Design and implement synchronous and asynchronous sequential circuits

* Session duration: 50 mins

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COURSE DELIVERY PLAN - THEORY Page 8 of 8

Sub Code / Sub Name: EC6302 - DIGITAL ELECTRONICS

Mapping CO – PO:

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10

CO1 A B B C

CO2 A B B C

CO3 A B C B C

CO4 B C C

CO5 A B C C

A – Excellent; B – Good; C - Average

TEXT BOOK:

1. M. Morris Mano, “Digital Design”, 4th Edition, Prentice Hall of India Pvt. Ltd.,
2008 / Pearson Education (Singapore) Pvt. Ltd., New Delhi, 2003.

REFERENCES:
2. John F.Wakerly, “Digital Design”, Fourth Edition, Pearson/PHI, 2008
3. John.M Yarbrough, “Digital Logic Applications and Design”, Thomson Learning, 2006.
4. Charles H.Roth. “Fundamentals of Logic Design”, 6th Edition, Thomson Learning, 2013.
5. Donald P.Leach and Albert Paul Malvino, “Digital Principles and Applications”, 4th Edition, TMH,
2001
6. Thomas L. Floyd, “Digital Fundamentals”, 8th Edition, Pearson Education Inc, 2004
7. Donald D.Givone, “Digital Principles and Design”, TMH, 2003.
8. S. Salivahanan & S. Arivazhagan, “Digital Circuits and Design”,3 rd Edition, Vikas Publishing House
Pvt. Ltd. 2007
9. http://nptel.ac.in
10.http://distrct.bluegrass.kctcs.edu/kevin.dunn/files/shift_registers.

Prepared by Approved by

Signature

Name Mr.M.Athappan, Mr.M.K.Varadarajan, Dr.S.Ganesh Vaidyanthan

Mr.B.Nethaji
Designation Assistant Professor Professor & Head

Date 30/06/2015 30/06/2015

Remarks: