A STUDY OF SCHEMATIC ENTRY TOOL – TANNER

1. To launch S-Edit in PC, go to START > PROGRAMS > TANNER > S-EDIT

2. Click on Module > Symbol Browser or click on to launch the symbol browser
window. Choose your device and click on Place.
3. Once the main parts are in place, it is time to add I/O pins and wire the parts together.
Select and place an Input Pad and an Output pad on the schematic and give the pads a
unique name.

4. Now using the wiring tool make appropriate connections

5. Output – Transient Analysis
1. Once Design Entry is over, Click and open T-Spice, then open Insert Command Dialog and select
Transient  Enter the time step and length -> Click Insert
2. Select Files Include Files  Browse for ml2_125 and open. Click Insert

3. Select Transient Result by expanding Output  Enter the node to be traced

4. Select Voltage Sources and Enter the values for inputs stream
5. Select Constant from Voltage sources and enter the constants

6. Finally all the Commands are entered in Module0 Window

7. Save and run Simulation. Expand Chart to view the output
10. DESIGN AND SIMULATE A CMOS INVERTING AMPLIFIER.

AIM
To design a CMOS inverter using the Schematic entry tool, Tanner and verify its
functioning.

APPARATUS REQUIRED:
1. Tanner tool
2. PC

THEORY:

CMOS Inverter consists of nMOS and pMOS transistor in series connected between
VDD and GND. The gate of the two transistors are shorted and connected to the input. When the
input to the inverter A = 0, nMOS transistor is OFF and pMOS transistor is ON. The output is
pull-up to VDD. When the input A = 1, nMOS transistor is ON and pMOS transistor is OFF. The
Output is Pull-down to GND.

PROCEDURE

1. Draw the schematic of CMOS Inverter using S-edit.

2. Perform Transient Analysis of the CMOS Inverter.

3. Obtain the output waveform from W-edit.

4. Obtain the spice code using T-edit.

CIRCUIT DIAGRAM - S-EDIT

CMOS INVERTER:

OUTPUT

* SPICE export by: S-Edit 14.11

* Export time: Mon Dec 09 11:14:52 2019
* Design: dhivya
* Cell: Cell0
* View: view0
* Export as: top-level cell
* Export mode: hierarchical
* Exclude empty cells: yes
* Exclude .model: no
* Exclude .end: no
* Expand paths: yes
* Wrap lines: no
* Root path: C:\Users\Administrator\Desktop\dhivya
* Exclude global pins: no
* Control property name: SPICE

********* Simulation Settings - General section *********

.probe
.option probev

.lib "C:\Users\Administrator\Documents\Tanner EDA\Tanner Tools

v14.1\Libraries\Models\Generic_025.lib" TT
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 --------
MNMOS_1 Out In Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_1 Out In Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
VVoltageSource_1 Vdd Gnd DC 5
********* Simulation Settings - Analysis section *********
.tran/Powerup 5n 40n
Vv1 In Gnd Bit {10101010}

********* Simulation Settings - Additional SPICE commands *********

.end
WAVEFORM

RESULT

Thus the CMOS inverter has been designed and simulated using S-Edit of
Tanner EDA Tools.
11. DESIGN AND SIMULATE BASIC COMMON SOURCE, COMMON GATE AND
COMMON DRAIN AMPLIFIERS.
AIM
To design and simulate basic common source, common Gate and common drain using
the Schematic entry tool, Tanner and verify its functioning.

APPARATUS REQUIRED:
1. Tanner tool
2. PC

THEORY:

COMMON SOURCE: This FET configuration is probably the most widely

used. The common source circuit provides a medium input and output impedance
levels. Both current and voltage gain can be described as medium, but the output is
the inverse of the input, i.e. 180° phase change. This provides a good overall
performance and as such it is often thought of as the most widely used
configuration.
COMMON DRAIN: This FET configuration is also known as the source
follower. The reason for this is that the source voltage follows that of the gate.
Offering a high input impedance and a low output impedance it is widely used as a
buffer. The voltage gain is unity, although current gain is high. The input and
output signals are in phase.
COMMON GATE: This transistor configuration provides a low input
impedance while offering a high output impedance. Although the voltage is high,
the current gain is low and the overall power gain is also low when compared to
the other FET circuit configurations available. The other salient feature of this
configuration is that the input and output are in phase.
COMMON SOURCE:

Tspice commands:

********* Simulation Settings - General section *********

.lib "C:\Users\student\Documents\Tanner EDA\Tanner Tools v14.1\Libraries\Models\Generic_025.lib" tt

********* Simulation Settings - Parameters and SPICE Options *********

*-------- Devices: SPICE.ORDER > 0 --------

RResistor_1 Vdd N_4 R=70.9k

RResistor_2 N_4 Gnd R=29.1k

RResistor_3 N_1 N_2 R=4k

RResistor_4 Vdd Out R=5k

MNMOS_1 Out N_2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

VVoltageSource_1 N_1 Gnd DC 0 AC 5 0

VVoltageSource_2 Vdd Gnd DC 0 AC 5 0

********* Simulation Settings - Analysis section *********

.ac dec 10 1N 100g

.print ac vdb(Out,Gnd)

********* Simulation Settings - Additional SPICE commands *********

.end

Output:
To add analysis,

Input impedance:

Ri = R1 || R2 = 20.6 Kilo ohm

Output impedance:

R0 = RD || r0 = 4.76 Kilo ohm

Gain:

Av = -gm (RD || r0) (Ri /Ri+Rsi), gm = 1.41 mA/V, Rsi = 4 Kilo ohm

3db Bandwidth can be calculated from the figure.

COMMON GATE AMPLIFIER:

Net List:

* SPICE export by: S-Edit 14.11

* Export time: Tue Dec 10 10:10:32 2019

* Design: dhivya

* Cell: Cell2

* View: view0

* Export as: top-level cell

* Export mode: hierarchical

* Exclude empty cells: yes

* Exclude .model: no

* Exclude .end: no

* Expand paths: yes

* Wrap lines: no
* Root path: C:\Users\Administrator\Desktop\dhivya

* Exclude global pins: no

* Control property name: SPICE

********* Simulation Settings - General section *********

.probe

.option probev

.lib "C:\Users\Administrator\Documents\Tanner EDA\Tanner Tools

v14.1\Libraries\Models\Generic_025.lib" TT

********* Simulation Settings - Parameters and SPICE Options *********

*-------- Devices: SPICE.ORDER > 0 --------

RResistor_1 Vdd Out R=5.1k

MNMOS_1 Out In N_1 N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

VVoltageSource_2 Vdd Gnd DC 5

VVoltageSource_1 N_1 Gnd DC 5 AC 1 0

********* Simulation Settings - Analysis section *********

.ac dec 100 1 1g

********* Simulation Settings - Additional SPICE commands *********

.end
OUTPUT WAVEFORM:
COMMON DRAIN:

Tspice commands:

********* Simulation Settings - General section *********

.lib "C:\Users\student\Documents\Tanner EDA\Tanner Tools v14.1\Libraries\Models\Generic_025.lib"

TT

********* Simulation Settings - Parameters and SPICE Options *********

*-------- Devices: SPICE.ORDER > 0 --------

CCapacitor_1 N_2 N_3 1u

RResistor_1 Vdd N_3 R=162k

RResistor_2 N_3 Gnd R=463k

RResistor_3 Out Gnd R=750

RResistor_4 N_1 N_2 R=4k

MNMOS_1 Vdd N_3 Out Out NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

VVoltageSource_2 Vdd Gnd 5

vin N_1 Gnd dc 0 SIN (0 5) AC 5 0

********* Simulation Settings - Analysis section *********

.ac dec 10 100 100G

.print ac vdb(Out,gnd)

********* Simulation Settings - Additional SPICE commands *********

.end

OUTPUT:
Input impedance:

Ri = R1 || R2 = 120 Kilo ohm

Output impedance:

R0 = RS || r0 || 1/gm

Gain:

Av = [gm (RS || r0) /(1+ gm (RS || r0))] * (Ri /Ri+Rsi), gm = 11.3 mA/V, Rsi = 4 Kilo ohm

3db Bandwidth can be calculated from the figure.

Result:

Thus the Basic Common source, Common Gate and Common Drain Amplifiers are
designed and simulated using S-Edit of Tanner EDA Tools.
12. DESIGN AND SIMULATE SIMPLE 5 TRANSISTOR DIFFERENTIAL AMPLIFIER.
ANALYZE GAIN, BANDWIDTH AND CMRR BY PERFORMING SCHEMATIC
SIMULATIONS.

AIM
To design a simple 5 transistor Differential Amplifier using the Schematic entry tool, Tanner
and verify its functioning.

APPARATUS REQUIRED:
1. Tanner tool
2. PC

THEORY:
A differential amplifier is a type of electronic amplifier that multiplies the difference between two inputs
by some constant factor (the differential gain). Many electronic devices use differential amplifiers
internally. The output of an ideal differential amplifier is given by:

Where Vin+ and Vin- are the input voltages and Ac is the differential gain. In practice,
however, the gain is not quite equal for the two inputs. This means that if Vin+ and Vin- are equal, the
output will not be zero, as it would be in the ideal case. A more realistic expression for the output of a
differential amplifier thus includes a second term.

Ac is called the common-mode gain of the amplifier. As differential amplifiers are often used when it is
desired to null out noise or bias-voltages that appear at both inputs, a low common-mode gain is usually
considered good.

The common-mode rejection ratio, usually defined as the ratio between differential-mode gain and
common-mode gain, indicates the ability of the amplifier to accurately cancel voltages that are common
to both inputs. Common-mode rejection ratio (CMRR):
PROCEDURE
1. Draw the schematic of CMOS Inverter using S-edit.
2. Perform Transient Analysis of the CMOS Inverter.
3. Obtain the output waveform from W-edit.
4. Obtain the spice code using T-edit.

DIFFERENTIAL AMPLIFIER USING 5 TRANSISTOR:

OUTPUT:
NETLIST:
* SPICE export by: S-Edit 14.11
* Export time: Wed Dec 11 12:24:17 2019
* Design: dhivya
* Cell: Cell4
* View: view0
* Export as: top-level cell
* Export mode: hierarchical
* Exclude empty cells: yes
* Exclude .model: no
* Exclude .end: no
* Expand paths: yes
* Wrap lines: no
* Root path: C:\Users\Administrator\Desktop\dhivya
* Exclude global pins: no
* Control property name: SPICE

********* Simulation Settings - General section *********

.probe
.option probev
.lib "C:\Users\Administrator\Documents\Tanner EDA\Tanner Tools
v14.1\Libraries\Models\Generic_025.lib" TT

********* Simulation Settings - Parameters and SPICE Options *********

*-------- Devices: SPICE.ORDER > 0 --------

MNMOS_1 N_1 N_3 N_2 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_2 N_2 N_5 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_3 Out N_4 N_2 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_1 N_1 N_1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_2 Out N_1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
VVoltageSource_1 Vdd Gnd DC 5
VVoltageSource_2 N_3 Gnd DC 5
VVoltageSource_3 N_4 Gnd DC 3
VVoltageSource_4 N_5 Gnd DC 0 AC 1 0
********* Simulation Settings - Analysis section *********
.ac dec 100 1 1g
.tran/powerup 5n 40n
********* Simulation Settings - Additional SPICE commands *********
.end
WAVEFORM

RESULT
Thus the 5 transistor Differential Amplifier has been designed and simulated performed using
Tanner EDA Tools.