Computer Architecture D.

Waechter@SheridanCollege

Computer Architecture
“A Look @ the Core”

Computer architecture is concerned with the structure and behaviour of the various
functional modules of a computer and how they interact to provide the processing needs
of the user. In particular, this course starts with the structure of Von Neumann computers
and progresses through the various generations of computer architectures to the
principles that govern today’s computers. As well as writing assembler language
programs, some of which will include systems programming structures and constructs,
students will learn how modern computers work and how benchmarks are employed to
measure the performance of today’s computer systems.

D. Waechter@Sheridan College

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Computer Architecture D. Waechter@SheridanCollege

What is this course all about?

In developing application software we define a computer system as follows:

The premise of the above definition is that data is collected as input to processed by
software and procedures to produce output in the form of information. A more complete
approach to defining a computer system would include all the aspects of computing as
given below.

The above diagram shows that the development of a computer system generally includes
many areas of knowledge and expertise. In these notes investigate how the hardware of a
system is designed and how the operating system interfaces with the hardware to support
the operation of an application. In this course we take “A Look @ the Core” of a
computer system.

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Computer Architecture: A Look @ the Core:

These notes are presented in two parts:

Part I Chapters 1 – 6, studies the traditional Von Neumann Fetch-Decode-Execute-Write

architectural model. The various components of a computer are discussed and how a
computer stores signed and unsigned integers and alphanumeric data is presented. The
Architecture of Intel’s 8086 chip is studied and students learn how to write assembler
language programs some of which include systems programming structures and
constructs.

Part II Chapters 7 – 10, presents a more modern view of computer architecture. Floating
point and extended data types are presented and the Von Neumann architecture is
extended to include a more modern approach to the computer; CISC, RISC and EPIC are
discussed and compared. The notes end with a comparison of several modern
architectures including Intel’s Hyper-Threading technology, Motorola’s PowerPC
architecture, AMD64 64-bit architecture and Intel Itanium’s approach to processor
design.

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Table of Contents
Part I

Chapter 1: Getting Started Page 5

1.0 Introduction .
1.1 Numbering Systems
1.2 Converting Between Numbering Systems
1.3 Exercise
1.4 A Simple Computer Model
1.5 The Computer’s Memory
1.6 The Systems Bus
1.7 Memory (Addresses and Contents)
1.8 Storing Data
1.9 Exercise
1.10 The Clock
1.11 Programming Languages
1.12 Von Neumann Computers
1.13 Technology Trends
1.14 Performance Metrics
1.15 Exercise

Chapter 2: Computer (CPU) Organization Page 32

2.0 Computer Organization
2.1 The CPU Organization
2.3 Our First Assembler Program
2.4 Inside the Executing Unit (ALU)
2.5 Metrics Used to Compare Architectures
2.6 Exercise

Chapter 3: The 8086 Architecture Page 49

3.0 Introduction
3.1 The Architectural Model
3.2 The Register File
3.3 The Executing Unit(s)
3.4 The Instruction Set
3.5 Data Types Supported by the 8086
3.6 Exercise

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Chapter 4: Assembler Language Programming (Part I) Page 62

4.0 Introduction
4.1 Types of Instructions
4.2 The Starter Instruction Set
4.3 Writing Assembler Language Programs
4.4 Programming Exercise 1
4.5 Interrupts (Software)
4.6 Programming Exercise 2
4.7 Controlling Traffic Lights
4.8 Programming Exercise 3

Chapter 5: Some More Advanced Topics Page 77

5.1 Addressing Memory
5.2 Global Memory Table
5.3 Hardware Interrupts (IRQ’s)
5.4 The System Stack
5.5 Postfix Notation

Chapter 6: Assembler Language Programming (Part II)

6.1 The Structured Programming Theorem Page 91
6.2 Procedures
6.3 “Systems Programming” A Brief Introduction
6.4 Programming Exercise
6.5 Macros
6.6 Variables
6.7 Address of a Variable
6.8 Constants

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Table of Contents
Part II

Chapter 7 Data Types

7.1 Fundamental Data Types Page 107
String Data Types
Numeric Data Types
7.2 Integer data Types 107
Signed Integers
Signed Integers
7.3 Floating Point Values 108
Representing Real Number Data
Excess-50 representation
Normalization and Formatting Floating Point Decimal Numbers
Normalization algorithm
Floating Point Representation in Computers
7.4 IEEE Standard 754 112
Single Precision Floating Point Standard
The Double Precision Floating Point Format Standard
NaN’s (Not a Number)
Exceptions

Rounding
The IA-32 Architecture Floating Point formats
7.5 Floating Point Registers: 116

7.6 x87 FPU Instructions 117

Data Transfer Instructions
Basic Arithmetic Instructions
Comparison Instructions
7.7 BCD (Binary Coded Decimal) Integers 118
Unpacked (BCD)
Packed (BCD)
7.8 Exercise 121

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Chapter 8: Beyond von Neumann Computer Architecture

8.1 Review of the Von Neumann Architecture Page 123
Early Days
The Data Stream
The Instruction Stream
8.2 Cache Memory 123
write – back & write – through
8.3 Flynn’s Taxonomy 124
SISD Computers
SIMD Computers
MISD Computers
MIMD Computers
8.4 Multiple Processor Systems (MPS) 126
Symmetrical Multiprocessing (SMP)
Massively Parallel Processing (MPP)

Clusters: Aggregating Machines into a Single System

8.5 Multiple Executing Units within a Single CPU 128

Pipelining

Scalar Processing
Superscalar Processing
Instruction Level Parallel (ILP-Processing)
VLIW Very Long Instruction Word

8.6 Scheduling Instruction Execution 131

Static: done by compiler
Dynamic: done by processor
8.7 Hazards “Problems” 132
Data Hazards
Structural Hazards
Branching Hazards
Consistency
8.8 Computer Architecture: A Modern Approach 135
Front End
Executing Units
Retire Unit
8.9 A word about RISC, CISC and EPIC 136

8.10 Exercise 137

8.11 Even More Data Types 139

Pointer Data Types
Vector Data Types
Single Instruction Multiple Data (SIMD)
MMX Multi Media Extensions
SSE Streaming Extensions

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SIMD Data Types, Registers and Instructions

Data Swizzling
8.12 Exercise 145

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Chapter 9: Intel IA-32 ─ PowerPC Architectures

9.1 Introduction “A little bit of History” Page 147
The Intel 8086
The Intel® 286 Processor (1982)
The Intel386™ Processor (1985)
The Intel486™ Processor (1989)
The Intel® Pentium® Processor (1993)

9.2 The P6 Family of Processors (1995-1999) (ATCE Architecture) 149

Intel Pentium Pro processor
Intel Pentium II processor
Intel Pentium® II Xeon™ processor
Intel Celeron® processor
Intel Pentium III processor
Intel Pentium® III Xeon™ processor.

9.3 Since the Turn of the Century (2000 – Present) 150

Intel NetBurst® Microarchitecture
The Intel® Pentium® M Processor (2003-2005)
Hyper-Treading Technology
Dual Core Technology
The Intel Pentium Processor Extreme Edition (2005)
Dual-Core Technology
Intel Extended (64- bit Technology) IA-32e

9.4 Summary of Intel’s Processors 151

9.5 IA-32 Architectural Models (Using Our Metrics) 153

Architectural Model
First Generation (8086 – Pentium) Von Neumann
NetBurst Technology (Superscalar Processing)
Front End Pipeline
The out-of-order Executing Core
The Retirement Unit
Executing Environments (Modes)
Protected mode:
Real-address mode:
System management mode (SMM):
The IA-32 Register Set
The Execution Core
The Instruction Set
The Data Types Supported

9.6 The PowerPC – An Overview 160

9.7 The PowerPC (G4) (Using our Metrics) 160

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Chapter 10: Other IA-32 Enhancements – AMD – Itanium 2

10.1 Other IA-32 Enhancements Page 167
Intel Pentium M Processor (2003 – 2005)
Intel Hyper-Threading Technology
Intel Dual Core Technology
IA-32e (64 bit Extension)

10.2 AMD64 Architecture 169

Modes of Operation
Legacy Mode
Protected Mode
8086 Virtual Mode
Real Mode
Long Mode
64 Bit Mode
Compatibility Mode
The Register File

10.3 Intel IA-32e (64 bit Extension) 171

10.4 Memory Alignment 173

10.5 Intel Itanium2 (For Completeness) 175