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Digital Electronic Circuits

Assignment- Week 1
TYPE OF QUESTION: MCQ/MSQ/Short answer
Number of questions: 20 Total mark: 20 X 1 = 20
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QUESTION 1:

Considering the propagation delay of transistors, which of the following statements are true?

1. Propagation delay occurs due to finite switching speed of transistor and circuit capacitor.
2. Propagation delay is directly proportional to power dissipation.
3. Propagation delay is associated with rise time and fall time.
4. Propagation delay is quantified by averaging the time taken for high to low and low to high
transitions.
a. 1, 2 and 3
b. 1, 2 and 4
c. 2, 3 and 4
d. 1, 3 and 4

Correct Answer: d

Detailed Solution:

(Refer to Performance Issues and Introduction to TTL, lecture 3 (slide 3), NPTEL online
certification courses)

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QUESTION 2:

For a given logic family, 𝑉𝑉𝑂𝑂𝑂𝑂 = 0 𝑉𝑉 and 𝑉𝑉𝑂𝑂𝑂𝑂 = 5 𝑉𝑉 . What would be the best option for noise
values of 𝑁𝑁𝑀𝑀𝐿𝐿 and 𝑁𝑁𝑀𝑀𝐻𝐻 for an ideal circuit with zero transition width?

a. 𝑁𝑁𝑀𝑀𝐿𝐿 = 0 𝑉𝑉, 𝑁𝑁𝑀𝑀𝐻𝐻 = 5𝑉𝑉

b. 𝑁𝑁𝑀𝑀𝐿𝐿 = 5𝑉𝑉, 𝑁𝑁𝑀𝑀𝐻𝐻 = 0 𝑉𝑉
c. 𝑁𝑁𝑀𝑀𝐿𝐿 = 2.5 𝑉𝑉, 𝑁𝑁𝑀𝑀𝐻𝐻 = 2.5 𝑉𝑉
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d. 𝑁𝑁𝑀𝑀𝐿𝐿 = 5 𝑉𝑉, 𝑁𝑁𝑀𝑀𝐻𝐻 = 5 𝑉𝑉

Correct Answer: c

Detailed Solution:
0+5𝑉𝑉
For an ideal circuit with zero transition width, 𝑁𝑁𝑀𝑀𝐿𝐿 = 𝑁𝑁𝑀𝑀𝐻𝐻 = 2
= 2.5𝑉𝑉

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QUESTION 3:
In the given circuit, 𝑅𝑅𝐵𝐵 = 15kΩ, 𝑅𝑅𝐶𝐶 = 2kΩ, 𝛽𝛽𝐹𝐹 = 100, 𝑉𝑉𝐵𝐵𝐵𝐵(𝑂𝑂𝑂𝑂) =𝑉𝑉𝐵𝐵𝐵𝐵(𝑆𝑆𝑆𝑆𝑆𝑆) = 0.7V and
𝑉𝑉𝐶𝐶𝐶𝐶(𝑆𝑆𝑆𝑆𝑆𝑆) = 0.2V. Find the value of noise margin, transition width and logic swing from input-
output characteristics of the transistor (Transistor as a switch):

a. 0.5V,0.36V and 4.8V

b. 1.2V, 4.8V and 0.42V
c. 1.0V, 0.5V and 4.8V
d. 3.88V, 0.36V and 4.8V

Correct Answer: a

Detailed Solution:

Transistor acts as an open switch in cut-off region and closed switch in saturation region.

At the edge of cutoff region, 𝑉𝑉𝑖𝑖𝑖𝑖 = 𝑉𝑉𝐼𝐼𝐼𝐼 = 0.7V;𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 = 𝑉𝑉𝑂𝑂𝑂𝑂 = 5V

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At the edge of saturation region, 𝐼𝐼𝐶𝐶 = (𝑉𝑉𝐶𝐶𝐶𝐶 –𝑉𝑉𝐶𝐶𝐶𝐶(𝑆𝑆𝑆𝑆𝑆𝑆) )/ 𝑅𝑅𝐶𝐶 = (5-0.2)/2 = 2.4mA

And 𝐼𝐼𝐵𝐵 = 𝐼𝐼𝐶𝐶 /βF= 2.4/100 = 0.024mA

Then, 𝑉𝑉𝑖𝑖𝑖𝑖 =𝑉𝑉𝐵𝐵𝐵𝐵(𝑂𝑂𝑂𝑂) +𝐼𝐼𝐵𝐵 𝑅𝑅𝐵𝐵 = 0.7 + (0.024 x 15) = 1.06V=𝑉𝑉𝐼𝐼𝐼𝐼

𝑉𝑉𝐼𝐼𝐼𝐼 = 1.06𝑉𝑉; 𝑉𝑉𝑂𝑂𝑂𝑂 = 0.2V

𝑁𝑁𝑀𝑀𝐻𝐻 = 𝑉𝑉𝑂𝑂𝑂𝑂 - 𝑉𝑉𝐼𝐼𝐼𝐼 = 5V –1.06V = 3.94V

𝑁𝑁𝑀𝑀𝐿𝐿 = 𝑉𝑉𝐼𝐼𝐼𝐼 - 𝑉𝑉𝑂𝑂𝑂𝑂 =0.7V – 0.2V = 0.5V

Noise Margin = min (𝑵𝑵𝑴𝑴𝑯𝑯 , 𝑵𝑵𝑴𝑴𝑳𝑳 ) = min (3.94V, 0.5V) = 0.5V

Transition width = 𝑽𝑽𝑰𝑰𝑰𝑰 - 𝑽𝑽𝑰𝑰𝑰𝑰 = 1.06V – 0.7V = 0.36V

Logic Swing =𝑽𝑽𝑶𝑶𝑶𝑶 - 𝑽𝑽𝑶𝑶𝑶𝑶 = 5V – 0.2V = 4.8V

QUESTION 4:
Refer Table 1 for this question: Let the load gate be from the 74ALS00 series. Which of the
following driver gates yield the highest fan-out?

7400 74LS00 74ALS00 74AS00

𝐼𝐼𝑂𝑂𝑂𝑂(max) −400𝜇𝜇𝜇𝜇 −400 𝜇𝜇𝜇𝜇 −400 𝜇𝜇𝜇𝜇 −2000 𝜇𝜇𝜇𝜇

𝐼𝐼𝐼𝐼𝐼𝐼(max) 40 𝜇𝜇𝜇𝜇 20 𝜇𝜇𝜇𝜇 20 𝜇𝜇𝜇𝜇 20 𝜇𝜇𝜇𝜇

𝐼𝐼𝑂𝑂𝑂𝑂(max) 16 𝑚𝑚𝑚𝑚 8 𝑚𝑚𝑚𝑚 8 𝑚𝑚𝑚𝑚 20 m𝐴𝐴

𝐼𝐼𝐼𝐼𝐼𝐼(max) −1.6 𝑚𝑚𝑚𝑚 −0.4 𝑚𝑚𝑚𝑚 −0.2 𝑚𝑚𝑚𝑚 −0.5 𝜇𝜇𝜇𝜇

a. 7400
b. 74ALS00
c. 74LS00
d. 74AS00

Correct Answer: d

Detailed Solution:
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QUESTION 5:
In the given circuit, 𝑉𝑉𝐶𝐶𝐶𝐶(𝑆𝑆𝑆𝑆𝑆𝑆) = 0.2V, 𝛽𝛽𝐹𝐹 = 50 ,𝑉𝑉𝐵𝐵𝐵𝐵(𝑂𝑂𝑂𝑂) =𝑉𝑉𝐵𝐵𝐵𝐵(𝑆𝑆𝑆𝑆𝑆𝑆) = 0.7V, 𝑉𝑉𝐼𝐼𝐼𝐼 = 1.66 V . Compute the
fan-out when noise margin high (𝑁𝑁𝑀𝑀𝐻𝐻 ) = 1V. What is the effect of noise margin on fan-out?
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a. 10, fan-out decreases with increase in noise margin

b. 11, fan-out decreases with increase in noise margin
c. 11, fan-out increases with increase in noise margin
d. 10, fan-out increases with increase in noise margin

Correct Answer: b

Detailed Solution:

Refer Lecture 02 (Slide 10) of Digital Electronic Circuits, NPTEL Online Certification Course

When 𝑉𝑉𝑖𝑖𝑖𝑖 is HIGH, driver-transistor is saturated and 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 will be LOW. With 𝑉𝑉𝐶𝐶𝐶𝐶(𝑆𝑆𝑆𝑆𝑆𝑆) = 0.2V all the load
transistors will be in the OFF state.

When 𝑉𝑉𝑖𝑖𝑖𝑖 is LOW, driver-transistor will be OFF and 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 will be at HIGH level. A limit in the fan-out is
set when the voltage at 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 is insufficient to saturate load gate transistors.

When 𝑉𝑉𝐼𝐼𝐼𝐼 = 1.66V with noise margin=0,

𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 = 𝑉𝑉𝑂𝑂𝑂𝑂 = 𝑉𝑉𝐼𝐼𝐼𝐼 + 𝑁𝑁𝑀𝑀𝐻𝐻 =1.66+0=1.66V

𝐼𝐼𝐶𝐶 (Driver)= (𝑉𝑉𝐶𝐶𝐶𝐶 –𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 )/ 𝑅𝑅𝐶𝐶 =(5 -1.66)/1=3.34mA

𝐼𝐼𝐵𝐵 (Load)= (𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 –𝑉𝑉𝐵𝐵𝐵𝐵(𝑆𝑆𝑆𝑆𝑆𝑆) )/ 𝑅𝑅𝐵𝐵 =(1.66 -0.7)/10=0.096mA

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𝐼𝐼𝐶𝐶 (Driver) 3.34

N= 𝐼𝐼𝐵𝐵 (Load)
= 0.096 = 34.79 ≈ 34

As Noise margin high (𝑁𝑁𝑀𝑀𝐻𝐻 ) = 1V in question,

𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 = 𝑉𝑉𝑂𝑂𝑂𝑂 = 𝑉𝑉𝐼𝐼𝐼𝐼 + 𝑁𝑁𝑀𝑀𝐻𝐻 = 1.66+1=2.66V

𝐼𝐼𝐶𝐶 (Driver)= (𝑉𝑉𝐶𝐶𝐶𝐶 –𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 )/ 𝑅𝑅𝐶𝐶 = (5 -2.66)/1=2.34mA

𝐼𝐼𝐵𝐵 (Load)= (𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 –𝑉𝑉𝐵𝐵𝐵𝐵(𝑆𝑆𝑆𝑆𝑆𝑆) )/ 𝑅𝑅𝐵𝐵 = (2.66 -0.7)/10=0.196mA

𝐼𝐼𝐶𝐶 (Driver) 2.34

N= 𝐼𝐼𝐵𝐵 (Load)
= 0.196 = 11.938 ≈ 11

Hence, fan-out decreases with increase in noise margin.

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QUESTION 6:
For proper operation of the NAND logic circuit shown below, the input voltage at logic LOW
needs to be less than:

a. 0V
b. 0.7 V
c. 1.4 V
d. 2.1 V

Correct Answer: c
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Detailed Solution:

Refer Lecture 03 (Slide 8) of Digital Electronic Circuits, NPTEL Online Certification Course

For the NAND gate, the output Y is HIGH when any of the inputs is LOW. For proper operation
when any of the inputs is LOW, the transistor is cut-off. This pulls up the voltage at Y to HIGH.

Let the maximum acceptable input LOW voltage be 𝑉𝑉𝐼𝐼𝐼𝐼

The diodes D1 and D2 are forward biased when their corresponding inputs are LOW, clamping
the voltage at P to:

𝑉𝑉𝑃𝑃 = 𝑉𝑉𝐼𝐼𝐼𝐼 + 0.7

For proper operation (i.e. to maintain the transistor in OFF),

𝑉𝑉𝑃𝑃 < 𝑉𝑉𝐷𝐷3 + 𝑉𝑉𝐷𝐷4 + 𝑉𝑉𝐵𝐵𝐵𝐵(𝑂𝑂𝑂𝑂)

⇒ 𝑉𝑉𝐼𝐼𝐼𝐼 + 0.7 < 3 × 0.7

𝑽𝑽𝑰𝑰𝑰𝑰 < 𝟏𝟏. 𝟒𝟒

Hence, the maximum acceptable input LOW voltage is 1.4 V.

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QUESTION 7:
For the standard TTL inverter shown below, determine the approximate output voltage 𝑉𝑉0 when the
input voltage, 𝑉𝑉𝑖𝑖 = 1𝑉𝑉. Assume 𝑉𝑉𝐵𝐵𝐵𝐵(𝑂𝑂𝑂𝑂𝑂𝑂→𝑂𝑂𝑂𝑂) = 0.65 𝑉𝑉, 𝑉𝑉𝐵𝐵𝐵𝐵(𝑂𝑂𝑂𝑂) = 0.7 𝑉𝑉, 𝑉𝑉𝐵𝐵𝐵𝐵(𝑠𝑠𝑠𝑠𝑠𝑠) = 0.75 𝑉𝑉 and
𝑉𝑉𝐶𝐶𝐶𝐶(𝑠𝑠𝑠𝑠𝑠𝑠) = 0.1 𝑉𝑉. (Hint: Use the transfer characteristics of standard TTL inverter for calculation of output
voltage).
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a. 𝑉𝑉0 = 4.2 𝑉𝑉
b. 𝑉𝑉0 = 2.9 𝑉𝑉
c. 𝑉𝑉0 = 3.5 𝑉𝑉
d. 𝑉𝑉0 = 2.1 𝑉𝑉

Correct Answer: b

Detailed Solution:

Figure below shows the voltage transfer characteristics of the standard TTL inverter.

The applied input voltage 𝐕𝐕𝐢𝐢 = 𝟏𝟏 𝐕𝐕 corresponds to region II of the curve shown. Hence, the
output voltage𝐕𝐕𝟎𝟎 satisfies the following relation (straight line equation):
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𝑽𝑽𝟎𝟎 − 𝟑𝟑. 𝟓𝟓 = −𝟏𝟏. 𝟒𝟒 ∗ (𝑽𝑽𝒊𝒊 − 𝟎𝟎. 𝟓𝟓𝟓𝟓)

⇒ 𝑽𝑽𝟎𝟎 = −𝟏𝟏. 𝟒𝟒𝑽𝑽𝒊𝒊 + 𝟒𝟒. 𝟐𝟐𝟐𝟐 = (−𝟏𝟏. 𝟒𝟒 × 𝟏𝟏) + 𝟒𝟒. 𝟐𝟐𝟐𝟐 = 𝟐𝟐. 𝟖𝟖𝟖𝟖 𝑽𝑽≈ 2.9V

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QUESTION 8:
In the following figure, match the components (in Column A) to their respective functions (in
Column B).

Column A Column B

A. Multi-emitter transistor Q1 1. Level shifting

B. Transistor Q4 2. Current steering
C. Diodes D1 & D2 3. Phase-splitter
D. Diode D3 4. To prevent ringing

a. A-1, B-3, C-4, D-2

b. A-3, B-2, C-1, D-4
c. A-2, B-1, C-4, D-3
d. A-2, B-3, C-4, D-1
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Correct Answer: d

Detailed Solution:

Figure shows the TTL logic NAND gate.

• The multi-emitter transistor acts as a current-steering network, which serves to “steer” current
to or away from the base of transistor Q4, depending on the logic level of the input.
• The transistor Q4 acts as a phase splitter, i.e. it controls which of the transistors Q2 and Q3 is ON
at any given time.
• The diodes D1 and D2 suppress ringing effects in the inputs A & B respectively.
• The diode D3 requires the extra voltage drop of 0.7V which prevents the transistor Q2 from
going into ON state while Q4 and Q3 are ON. Hence, it performs the function of level-shifting by
controlling the input ON voltage of transistor Q4.

(Refer to Transistor-Transistor Logic, lectures 3 & 4, Digital Electronic Circuits, NPTEL

online certification courses)

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QUESTION 9:
In a standard TTL, which of the following statements are TRUE?
(i) Totem-pole output has lower propagation delay as compared to open-collector
configuration.
(ii) The open-collector outputs of TTL gates can be tied together.
(iii) The totem-pole outputs of TTL gates can be tied together.
(iv) In absence of noise, an open circuit to an input of a TTL gate behaves as if it is a high level
input.

a. (i), (ii)
b. (iii), (iv)
c. (i), (ii), (iv)
d. (i), (iii), (iv)
Correct answer: c
Detailed solution:

• The open-collector TTL gate is used with an external pull-up resistor (typically few
KOhm) which increases the delay due to charging/discharging of stray wiring
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capacitances. On the other hand, the Totem-pole output employs active pull-up
reducing the switching time, and hence exhibits lower propagation delay.
• The open-collector outputs of TTL gates can be tied together along with a single external
resistor to perform wired-AND logic.
• The totem-pole outputs of TTL gates cannot be tied together. When two totem poles
are wired together with the output of one gate HIGH and the output of the second gate
LOW, the excessive amount of current drawn can produce enough heat to damage the
transistors in the circuit.
• An open circuit to an input of a TTL gate behaves as if it’s a high level input. In this case,
the input (multi-emitter) transistor is in OFF state. This is similar to the operation for
HIGH input, where the base-emitter junction is reverse biased. But, the presence of a
small amount of noise at the open input can change this to a low level.

(Reference: Pg. 500-504, Digital Design, Mano & Ciletti, 4th Edition)

________________________________________________________________________

QUESTION 10:
Identify the following circuit?
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a. Tristate buffer
b. Tristate inverter
c. Open collector logic
d. Totem pole logic

Correct Answer: b

Detailed Solution:

(Refer to Transistor-Transistor Logic, lecture 4 (slide 6), NPTEL online certification courses)

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QUESTION 11:

For the 2-input TTL NAND gate, 𝑉𝑉𝑐𝑐𝑐𝑐 = 5 𝑉𝑉 and a 1 𝐾𝐾Ω load is connected to its output. Consider
𝑉𝑉𝐶𝐶𝐶𝐶(𝑠𝑠𝑠𝑠𝑠𝑠) = 0 (deep into saturation), 𝑉𝑉𝐶𝐶𝐶𝐶(𝑠𝑠𝑠𝑠𝑠𝑠) = 0.3 (onset of saturation) and the current gain
ℎ𝐹𝐹𝐹𝐹 = 100 for any of the transistors. Consider the diode drop in forward bias 𝑉𝑉𝐷𝐷 = 0.7 𝑉𝑉. The
output voltage when both inputs are 0V is (i)_________ and when both inputs are 5V is (ii)
_________ respectively.

a. (i) 0.3 V, (ii) 4 V

b. (i) 2.5 V (ii) 0.3 V
c. (i) 3.54 V, (ii) 0 V
d. (i) 3.54 V, (ii) 0.3 V

Correct Answer: c

Detailed Solution:
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Let R1 = 4KΩ, R2 = 1.6KΩ, R3 = 1KΩ, R4 = 130 Ω and R L = 1KΩ.

______________________________________________________________________________

QUESTION 12:
In the following circuit, each of the 2-input gates are implemented using open-collector TTL
logic. Then, the value of Boolean output for the given input conditions is ______________? (1:
if HIGH and 0: if LOW).
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5V

A=0
B=1

C=1
Output
D=0

E=0
F=0

Correct answer: 1

Detailed Solution:

The circuit describes wired AND operation. In the given input conditions, all input to wire
junction is 1. Hence output will be at logic 1 (since there is no sink to bypass the voltage).

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QUESTION 13:

In the following circuit (Motorola MC715P 3 Input NOR gate), suppose 0V is given as input to
pin number 2, 12 and 13. The output pin 3 is then connected directly to pin 5, 6 and 9. What is
the value of voltage appearing at output pin 10? (Consider VCC=+5V and VCE(sat) across
transistors to be 0.2V)
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a. 0V
b. 5V
c. 0.7V
d. 0.2V

Correct Answer: d

Detailed Solution:

When input at pin number 2, 12 and 13 are 0V, the corresponding transistors would be OFF and
a high voltage would appear at terminal 3 due to Vcc.

As terminal 3 is directly connected to pins 5, 6 and 9, the corresponding transistors (of pins 5, 6
and 9) will turn ON and move into saturation region. Since it is given that collector-emitter
saturation voltage across transistors is 0.2V, the voltage at terminal 10 would become 0.2V.
______________________________________________________________________________

QUESTION 14:
In the figure shown below, which logic operation is implemented?
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a) NOT operation
b) OR operation
c) XOR operation
d) AND operation

Correct Answer: d

Detailed Solution:

The circuit consists of three NAND gates connect in a way, shown below to form AND gate.

X = (A’B’)’ = AB
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Where every NAND gate is given by its RTL implementation:

p
+5V

R1

Y = (A. B)′
R2
A

R3
B

The question can also be solved analytically. Output will be 1 only when both the inputs to
outer NAND circuit is 0, which is possible only when both A and B are 0. When both A and B are
zero, transistors of left most NAND circuit are off and all of the VCC appears at the output.

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QUESTION 15:
Which of the following statements are TRUE about Schottky TTL logic?
(i) The Schottky diode is formed by the junction of a metal and semiconductor.
(ii) The Schottky diode is placed at the base-collector junction of transistors.
(iii) The Schottky diode is placed at the base-emitter junction of transistors.
(iv) The Schottky diode prevents the transistors from going into saturation.
a. (i), (ii), (iv)
b. (i), (iii), (iv)
c. (i), (ii)
d. (iii),(iv)

Correct answer: a

Detailed Solution:
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The Schottky diode is formed by the junction of a metal and semiconductor. Saturation can be
eliminated by placing a Schottky diode between the base and collector of each saturated
transistor in the circuit. The presence of a Schottky diode between the base and collector
prevents the transistor from going into saturation.

(Reference: Pg. 504, Digital Design, Mano & Ciletti, 4th Edition)

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QUESTION 16:
Which of the following statements are TRUE about CMOS logic?

(i) CMOS has very high input resistance and hence, draws very low current.
(ii) CMOS has high fan-out as compared to TTL.
(iii) CMOS is generally faster than TTL.
(iv) CMOS has low packing density.
(v) CMOS exhibits low power dissipation.

a. (i), (iii), (iv)

b. (i), (ii), (iii), (v)
c. (i), (ii), (v)
d. (ii), (v)

Correct Answer: c

Detailed Solution:
Reference: Pg. 514-515, Digital Design, Mano & Ciletti, 4th Edition
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QUESTION 17:
Which logic operation is described by the following circuit?
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a. NOT gate
b. OR gate
c. AND gate
d. Pass through (Input = Output)

Correct Answer: d

Detailed Solution:

The circuit consists cascade of two inverters, first is made using TTL logic and second using
CMOS logic. TTL-CMOS interface has the required pull up resistor. Hence, the circuit
implements two NOT gates in cascade which passes the input through (input = output).

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QUESTION 18:
The given CMOS circuit implements the logic:
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a. Y = A’B’ + AB
b. Y = A’B + AB’
c. Y = (AB)’
d. Y = (A + B)’

Correct Answer: b

Detailed Solution:

P1 P2

P3 P4

N1 N2

N3 N4
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A B P1 P2 P3 P4 N1 N2 N3 N4 Y

0 0 ON ON OFF OFF OFF ON ON OFF 0

0 1 ON OFF ON OFF OFF OFF ON ON 1

1 0 OFF ON OFF ON ON ON OFF OFF 1

1 1 OFF OFF ON ON ON OFF OFF ON 0

When A and B both are 0, N2 and N3 are ON which connect the output Y to ground, making it
OFF (0).

When A=0 and B=1, P1 and P3 are at ON state, connecting output Y directly to +5V, making
them ON (1).

When A=1 and B=0, P2 and P4 are at ON sate, connecting output Y directly to +5V, making them
ON (1).

When A=1 and B=1, N1 and N4 are ON which connect the output Y to ground, making it OFF (0).

Hence, Y = AB’ + A’B

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QUESTION 19:
Based on the transfer characteristics of CMOS inverter, determine the correct relation when
the PMOS transistor, Qp is in saturation while the NMOS transistor, Qn is not where Vss is
supply voltage, VT(p) is threshold voltage of Qp and VT(n) is threshold voltage of Qn.

a. Voutput — VT(p) ≤ Vinput ≤ Vss — VT(p)

b. VT(n) ≤ Vinput ≤ Voutput + VT(n)
c. Vinput ≤ VT(n)
d. Vinput ≥ Vss — VT(p)

Correct Answer: a

Detailed Solution: Refer CMOS Transfer characteristics of Lecture 05 (slide 5), Digital
Electronics Circuits NPTEL online certification course.
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QUESTION 20:
Fill up the truth table according to the input:

a. (i) 0 (ii) High Impedance (iii) 1 (iv) High Impedance

b. (i) 1 (ii) High Impedance (iii) 0 (iv) High Impedance
c. (i) High Impedance (ii) 1 (iii) High Impedance (iv) 0
d. (i) High Impedance (ii) 0 (iii) High Impedance (iv) 1

Correct Answer: c

Detailed Solution: Refer Lecture 05 (Slide 8), Digital Electronics Circuits NPTEL online
certification course.

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