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M. B. Patil
mbpatil@ee.iitb.ac.in
www.ee.iitb.ac.in/~sequel
* Real signals (e.g., a voltage measured with a thermocouple or a speech signal recorded with a microphone)
are analog quantities, varying continuously with time.
* Real signals (e.g., a voltage measured with a thermocouple or a speech signal recorded with a microphone)
are analog quantities, varying continuously with time.
* Digital format offers several advantages: digital signal processing, storage, use of computers, robust
transmission, etc.
* Real signals (e.g., a voltage measured with a thermocouple or a speech signal recorded with a microphone)
are analog quantities, varying continuously with time.
* Digital format offers several advantages: digital signal processing, storage, use of computers, robust
transmission, etc.
* An ADC (Analog-to-Digital Converter) is used to convert an analog signal to the digital format.
* Real signals (e.g., a voltage measured with a thermocouple or a speech signal recorded with a microphone)
are analog quantities, varying continuously with time.
* Digital format offers several advantages: digital signal processing, storage, use of computers, robust
transmission, etc.
* An ADC (Analog-to-Digital Converter) is used to convert an analog signal to the digital format.
* The reverse conversion (from digital to analog) is also required. For example, music stored in a DVD in
digital format must be converted to an analog voltage for playing out on a speaker.
* Real signals (e.g., a voltage measured with a thermocouple or a speech signal recorded with a microphone)
are analog quantities, varying continuously with time.
* Digital format offers several advantages: digital signal processing, storage, use of computers, robust
transmission, etc.
* An ADC (Analog-to-Digital Converter) is used to convert an analog signal to the digital format.
* The reverse conversion (from digital to analog) is also required. For example, music stored in a DVD in
digital format must be converted to an analog voltage for playing out on a speaker.
* A DAC (Digital-to-Analog Converter) is used to convert a digital signal to the analog format.
VR
DN−1
N-bit analog
digital DAC VA
output
input
D2
D1
D0
ground
DAC
VR
DN−1
N-bit analog
digital DAC VA
output
input
D2
D1
D0
ground
N-bit analog
digital DAC VA
output
input
D2
resolution
D1
D0
ground
digital
input
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
* For a 4-bit DAC, with input S3 S2 S1 S0 , the output voltage is
VA = K (S3 × 23 ) + (S2 × 22 ) + (S1 × 21 ) + (S0 × 20 ) .
PN−1
In general, VA = K 0 Sk 2k .
DAC
VA
N=4
VR
maximum
output
DN−1 voltage
N-bit analog
digital DAC VA
output
input
D2
resolution
D1
D0
ground
digital
input
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
* For a 4-bit DAC, with input S3 S2 S1 S0 , the output voltage is
VA = K (S3 × 23 ) + (S2 × 22 ) + (S1 × 21 ) + (S0 × 20 ) .
PN−1
In general, VA = K 0 Sk 2k .
* K is proportional to the reference voltage VR . Its value depends on how the DAC is implemented.
M. B. Patil, IIT Bombay
DAC using binary-weighted resistors
A3 I3 A3 I3
VR
Inputs: S3 , S2 , S1 , S0 S3 VR
R3 = R R3 = R
Output: VA
A2 I2 A2 I2
S2 VR
R2 = 2 R R2 = 2 R
A1 I1 A1 I1
Rf S1 VR Rf
R1 = 4 R R1 = 4 R
A0 I0 I A0 I0 I
S0 VR
R0 = 8 R R0 = 8 R
VA VA
A3 I3 A3 I3
VR
Inputs: S3 , S2 , S1 , S0 S3 VR
R3 = R R3 = R
Output: VA
A2 I2 A2 I2
S2 VR
R2 = 2 R R2 = 2 R
A1 I1 A1 I1
Rf S1 VR Rf
R1 = 4 R R1 = 4 R
A0 I0 I A0 I0 I
S0 VR
R0 = 8 R R0 = 8 R
VA VA
A3 I3 A3 I3
VR
Inputs: S3 , S2 , S1 , S0 S3 VR
R3 = R R3 = R
Output: VA
A2 I2 A2 I2
S2 VR
R2 = 2 R R2 = 2 R
A1 I1 A1 I1
Rf S1 VR Rf
R1 = 4 R R1 = 4 R
A0 I0 I A0 I0 I
S0 VR
R0 = 8 R R0 = 8 R
VA VA
* If the input bit Sk is 1, Ak gets connected to VR ; else, it gets connected to ground. → V (Ak ) = Sk × VR .
A3 I3 A3 I3
VR
Inputs: S3 , S2 , S1 , S0 S3 VR
R3 = R R3 = R
Output: VA
A2 I2 A2 I2
S2 VR
R2 = 2 R R2 = 2 R
A1 I1 A1 I1
Rf S1 VR Rf
R1 = 4 R R1 = 4 R
A0 I0 I A0 I0 I
S0 VR
R0 = 8 R R0 = 8 R
VA VA
* If the input bit Sk is 1, Ak gets connected to VR ; else, it gets connected to ground. → V (Ak ) = Sk × VR .
V (Ak ) − 0 Sk VR
* Since the inverting terminal of the op-amp is at virtual ground, Ik = = .
Rk Rk
A3 I3 A3 I3
VR
Inputs: S3 , S2 , S1 , S0 S3 VR
R3 = R R3 = R
Output: VA
A2 I2 A2 I2
S2 VR
R2 = 2 R R2 = 2 R
A1 I1 A1 I1
Rf S1 VR Rf
R1 = 4 R R1 = 4 R
A0 I0 I A0 I0 I
S0 VR
R0 = 8 R R0 = 8 R
VA VA
* If the input bit Sk is 1, Ak gets connected to VR ; else, it gets connected to ground. → V (Ak ) = Sk × VR .
V (Ak ) − 0 Sk VR
* Since the inverting terminal of the op-amp is at virtual ground, Ik = = .
Rk Rk
N−1
S0 VR S1 VR S2 VR S3 VR VR X k
* I = + + + = N−1 Sk × 2 (N = 4).
8R 4R 2R R 2 R 0
A3 I3 A3 I3
VR
Inputs: S3 , S2 , S1 , S0 S3 VR
R3 = R R3 = R
Output: VA
A2 I2 A2 I2
S2 VR
R2 = 2 R R2 = 2 R
A1 I1 A1 I1
Rf S1 VR Rf
R1 = 4 R R1 = 4 R
A0 I0 I A0 I0 I
S0 VR
R0 = 8 R R0 = 8 R
VA VA
* If the input bit Sk is 1, Ak gets connected to VR ; else, it gets connected to ground. → V (Ak ) = Sk × VR .
V (Ak ) − 0 Sk VR
* Since the inverting terminal of the op-amp is at virtual ground, Ik = = .
Rk Rk
N−1
S0 VR S1 VR S2 VR S3 VR VR X k
* I = + + + = N−1 Sk × 2 (N = 4).
8R 4R 2R R 2 R 0
N−1
Rf X k
* The output voltage is Vo = −Rf I = −VR Sk × 2 .
2N−1 R 0
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
* Consider an 8-bit DAC with VR = 5 V. What is the smallest value of R which will limit the current drawn from the supply
(VR ) to 10 mA?
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
* Consider an 8-bit DAC with VR = 5 V. What is the smallest value of R which will limit the current drawn from the supply
(VR ) to 10 mA?
Maximum current is drawn from VR when the input is 1111 1111.
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
* Consider an 8-bit DAC with VR = 5 V. What is the smallest value of R which will limit the current drawn from the supply
(VR ) to 10 mA?
Maximum current is drawn from VR when the input is 1111 1111.
→ All nodes A0 to A7 get connected to VR .
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
* Consider an 8-bit DAC with VR = 5 V. What is the smallest value of R which will limit the current drawn from the supply
(VR ) to 10 mA?
Maximum current is drawn from VR when the input is 1111 1111.
→ All nodes A0 to A7 get connected to VR .
VR VR VR 1 VR 0 1 7
→ 10 mA = + + ··· + 7 = 7 2 + 2 + ··· + 2
R 2R 2 R 2 R
1 VR 8 255 VR
= 7 2 −1 =
2 R 128 R
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
* Consider an 8-bit DAC with VR = 5 V. What is the smallest value of R which will limit the current drawn from the supply
(VR ) to 10 mA?
Maximum current is drawn from VR when the input is 1111 1111.
→ All nodes A0 to A7 get connected to VR .
VR VR VR 1 VR 0 1 7
→ 10 mA = + + ··· + 7 = 7 2 + 2 + ··· + 2
R 2R 2 R 2 R
1 VR 8 255 VR 5V 255
= 7 2 −1 = → Rmin = × = 996 Ω .
2 R 128 R 10 mA 128
(Ref.: K. Gopalan, Introduction to Digital Microelectronic Circuits, Tata McGraw-Hill, New Delhi, 1998)
M. B. Patil, IIT Bombay
DAC using binary-weighted resistors: Example (from Gopalan)
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
* If Rf = R, what is the resolution (i.e., ∆VA corresponding to the input LSB changing from 0 to 1 with other input bits
constant)?
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
* If Rf = R, what is the resolution (i.e., ∆VA corresponding to the input LSB changing from 0 to 1 with other input bits
constant)?
Rf h
7 1 0
i
VA = −VR N−1 S7 2 + · · · + S1 2 + S0 2
2 R
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
* If Rf = R, what is the resolution (i.e., ∆VA corresponding to the input LSB changing from 0 to 1 with other input bits
constant)?
Rf h
7 1 0
i
VA = −VR N−1 S7 2 + · · · + S1 2 + S0 2
2 R
VR Rf 5V 5
→ ∆VA = N−1 = 8−1 × 1 = = 0.0391 V.
2 R 2 128
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
* If the resistors are specified to have a tolerance of 1 %, what is the range of |VA | corresponding to input 1111 1111?
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
* If the resistors are specified to have a tolerance of 1 %, what is the range of |VA | corresponding to input 1111 1111?
|VA | is maximum when (a) currents I0 , I1 , etc. assume their maximum values, with Rk = Rk0 × (1 − 0.01) and (b) Rf is
maximum, Rf = Rf0 × (1 + 0.01).
(The superscript ‘0’ denotes nominal value.)
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
* If the resistors are specified to have a tolerance of 1 %, what is the range of |VA | corresponding to input 1111 1111?
|VA | is maximum when (a) currents I0 , I1 , etc. assume their maximum values, with Rk = Rk0 × (1 − 0.01) and (b) Rf is
maximum, Rf = Rf0 × (1 + 0.01).
(The superscript ‘0’ denotes nominal value.)
255 Rf max 255 1.01
→ |VA |max
11111111 = VR × × =5× × = 10.162 V.
128 R 128 0.99
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
* If the resistors are specified to have a tolerance of 1 %, what is the range of |VA | corresponding to input 1111 1111?
|VA | is maximum when (a) currents I0 , I1 , etc. assume their maximum values, with Rk = Rk0 × (1 − 0.01) and (b) Rf is
maximum, Rf = Rf0 × (1 + 0.01).
(The superscript ‘0’ denotes nominal value.)
255 Rf max 255 1.01
→ |VA |max
11111111 = VR × × =5× × = 10.162 V.
128 R 128 0.99
255 0.99
Similarly, |VA |min
11111111 = 5 × × = 9.764 V.
128 1.01
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
* ∆VA for input 1111 1111 = 10.162 − 9.764 ≈ 0.4 V which is larger than the resolution (0.039 V) of the DAC. This
situation is not acceptable.
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
* ∆VA for input 1111 1111 = 10.162 − 9.764 ≈ 0.4 V which is larger than the resolution (0.039 V) of the DAC. This
situation is not acceptable.
* The output voltage variation can be reduced by using resistors with a smaller tolerance. However, it is difficult to
fabricate an IC with widely varying resistance values (from R to 2N−1 R) and each with a small enough tolerance.
A7 I7
VR
R7 = R
A1 I1
Rf
6
R1 = 2 R
A0 I0 I
7
R0 = 2 R
VA
* ∆VA for input 1111 1111 = 10.162 − 9.764 ≈ 0.4 V which is larger than the resolution (0.039 V) of the DAC. This
situation is not acceptable.
* The output voltage variation can be reduced by using resistors with a smaller tolerance. However, it is difficult to
fabricate an IC with widely varying resistance values (from R to 2N−1 R) and each with a small enough tolerance.
→ use R − 2R ladder network instead.
R R R
2R 2R 2R 2R 2R
A0 A1 A2 A3
LSB MSB
R R R
2R 2R 2R 2R 2R
A0 A1 A2 A3
LSB MSB
2R 2R 2R 2R 2R
S 0 VR S1 VR S2 VR S3 VR
R R R
2R 2R 2R 2R 2R
R-2R ladder network: Thevenin resistance
R R R
2R 2R 2R 2R 2R
R-2R ladder network: Thevenin resistance
R R R
2R 2R 2R 2R 2R
R R R
R 2R 2R 2R
R-2R ladder network: Thevenin resistance
R R R
2R 2R 2R 2R 2R
R R R
R 2R 2R 2R
R-2R ladder network: Thevenin resistance
R R R
2R 2R 2R 2R 2R
R R R
R 2R 2R 2R
R R
R 2R 2R
R-2R ladder network: Thevenin resistance
R R R
2R 2R 2R 2R 2R
R R R
R 2R 2R 2R
R R
R 2R 2R
R-2R ladder network: Thevenin resistance
R R R
2R 2R 2R 2R 2R
R R R
R 2R 2R 2R
R R
R 2R 2R
R
R 2R
R-2R ladder network: Thevenin resistance
R R R
2R 2R 2R 2R 2R
R R R
R 2R 2R 2R
R R
R 2R 2R
R
R 2R
R-2R ladder network: Thevenin resistance
R R R
2R 2R 2R 2R 2R
R R R
R 2R 2R 2R
R R
R 2R 2R
R
R 2R RTh = R
VTh for S0 = 1 2R 2R 2R 2R 2R
VR
R-2R ladder network: R R R
VTh for S0 = 1 2R 2R 2R 2R 2R
VR
R-2R ladder network: R R R
VTh for S0 = 1 2R 2R 2R 2R 2R
VR
R R R
R 2R 2R 2R
VR
2
R-2R ladder network: R R R
VTh for S0 = 1 2R 2R 2R 2R 2R
VR
R R R
R 2R 2R 2R
VR
2
R-2R ladder network: R R R
VTh for S0 = 1 2R 2R 2R 2R 2R
VR
R R R
R 2R 2R 2R
VR
2
R R
R 2R 2R
VR
4
R-2R ladder network: R R R
VTh for S0 = 1 2R 2R 2R 2R 2R
VR
R R R
R 2R 2R 2R
VR
2
R R
R 2R 2R
VR
4
R-2R ladder network: R R R
VTh for S0 = 1 2R 2R 2R 2R 2R
VR
R R R
R 2R 2R 2R
VR
2
R R
R 2R 2R
VR
4
R 2R
VR
8
R-2R ladder network: R R R
VTh for S0 = 1 2R 2R 2R 2R 2R
VR
R R R
R 2R 2R 2R
VR
2
R R
R 2R 2R
VR
4
R 2R
VR
8
R-2R ladder network: R R R
VTh for S0 = 1 2R 2R 2R 2R 2R
VR
R R R
R 2R 2R 2R
VR
2
R R
R 2R 2R
VR
4
R 2R
VR
VTh =
VR 16
8
VTh for S1 = 1 2R 2R 2R 2R 2R
VR
R-2R ladder network: R R R
VTh for S1 = 1 2R 2R 2R 2R 2R
VR
R-2R ladder network: R R R
VTh for S1 = 1 2R 2R 2R 2R 2R
VR
R R
2R 2R 2R 2R
VR
R-2R ladder network: R R R
VTh for S1 = 1 2R 2R 2R 2R 2R
VR
R R
2R 2R 2R 2R
VR
R-2R ladder network: R R R
VTh for S1 = 1 2R 2R 2R 2R 2R
VR
R R
2R 2R 2R 2R
VR
R R
R 2R 2R
VR
2
R-2R ladder network: R R R
VTh for S1 = 1 2R 2R 2R 2R 2R
VR
R R
2R 2R 2R 2R
VR
R R
R 2R 2R
VR
2
R-2R ladder network: R R R
VTh for S1 = 1 2R 2R 2R 2R 2R
VR
R R
2R 2R 2R 2R
VR
R R
R 2R 2R
VR
2
R 2R
VR
4
R-2R ladder network: R R R
VTh for S1 = 1 2R 2R 2R 2R 2R
VR
R R
2R 2R 2R 2R
VR
R R
R 2R 2R
VR
2
R 2R
VR
4
R-2R ladder network: R R R
VTh for S1 = 1 2R 2R 2R 2R 2R
VR
R R
2R 2R 2R 2R
VR
R R
R 2R 2R
VR
2
R 2R
VR
VTh =
VR 8
4
VTh for S2 = 1 2R 2R 2R 2R 2R
VR
R-2R ladder network: R R R
VTh for S2 = 1 2R 2R 2R 2R 2R
VR
R-2R ladder network: R R R
VTh for S2 = 1 2R 2R 2R 2R 2R
VR
2R 2R 2R
VR
R-2R ladder network: R R R
VTh for S2 = 1 2R 2R 2R 2R 2R
VR
2R 2R 2R
VR
R-2R ladder network: R R R
VTh for S2 = 1 2R 2R 2R 2R 2R
VR
2R 2R 2R
VR
R 2R
VR
2
R-2R ladder network: R R R
VTh for S2 = 1 2R 2R 2R 2R 2R
VR
2R 2R 2R
VR
R 2R
VR
2
R-2R ladder network: R R R
VTh for S2 = 1 2R 2R 2R 2R 2R
VR
2R 2R 2R
VR
R 2R
VR
VTh =
VR 4
2
VTh for S3 = 1 2R 2R 2R 2R 2R
VR
R-2R ladder network: R R R
VTh for S3 = 1 2R 2R 2R 2R 2R
VR
R-2R ladder network: R R R
VTh for S3 = 1 2R 2R 2R 2R 2R
VR
2R 2R
VR
R-2R ladder network: R R R
VTh for S3 = 1 2R 2R 2R 2R 2R
VR
2R 2R
VR
VTh =
2
VR
R R R
2R 2R 2R 2R 2R RTh
VTh
S0 VR S1 VR S2 VR S3 VR
R R R
2R 2R 2R 2R 2R RTh
VTh
S0 VR S1 VR S2 VR S3 VR
* RTh = R .
R R R
2R 2R 2R 2R 2R RTh
VTh
S0 VR S1 VR S2 VR S3 VR
* RTh = R .
(S0) (S1) (S2) (S3)
* VTh = VTh + VTh + VTh + VTh
VR h
0 1 2 3
i
= S0 2 + S1 2 + S2 2 + S3 2 .
16
R R R
2R 2R 2R 2R 2R RTh
VTh
S0 VR S1 VR S2 VR S3 VR
* RTh = R .
(S0) (S1) (S2) (S3)
* VTh = VTh + VTh + VTh + VTh
VR h
0 1 2 3
i
= S0 2 + S1 2 + S2 2 + S3 2 .
16
* We can use the R-2R ladder network and an op-amp
to make up a DAC → next slide.
Rf Rf
R R R RTh
2R 2R 2R 2R 2R Vo VTh Vo
S 0 VR S 1 VR S 2 VR S 3 VR
Rf Rf
R R R RTh
2R 2R 2R 2R 2R Vo VTh Vo
S 0 VR S 1 VR S 2 VR S 3 VR
Rf Rf VR h 0 1 2 3
i
* Vo = − VTh = − S0 2 + S1 2 + S2 2 + S3 2 .
RTh RTh 16
Rf Rf
R R R RTh
2R 2R 2R 2R 2R Vo VTh Vo
S 0 VR S 1 VR S 2 VR S 3 VR
Rf Rf VR h 0 1 2 3
i
* Vo = − VTh = − S0 2 + S1 2 + S2 2 + S3 2 .
RTh RTh 16
N−1
Rf Rf VR X k
* For an N-bit DAC, Vo = − VTh = − N
Sk 2 .
RTh RTh 2 0
Rf Rf
R R R RTh
2R 2R 2R 2R 2R Vo VTh Vo
S 0 VR S 1 VR S 2 VR S 3 VR
Rf Rf VR h 0 1 2 3
i
* Vo = − VTh = − S0 2 + S1 2 + S2 2 + S3 2 .
RTh RTh 16
N−1
Rf Rf VR X k
* For an N-bit DAC, Vo = − VTh = − N
Sk 2 .
RTh RTh 2 0
* 6- to 20-bit DACs based on the R-2R ladder network are commercially available in monolithic form (single chip).
Rf Rf
R R R RTh
2R 2R 2R 2R 2R Vo VTh Vo
S 0 VR S 1 VR S 2 VR S 3 VR
Rf Rf VR h 0 1 2 3
i
* Vo = − VTh = − S0 2 + S1 2 + S2 2 + S3 2 .
RTh RTh 16
N−1
Rf Rf VR X k
* For an N-bit DAC, Vo = − VTh = − N
Sk 2 .
RTh RTh 2 0
* 6- to 20-bit DACs based on the R-2R ladder network are commercially available in monolithic form (single chip).
* Bipolar, CMOS, or BiCMOS technology is used for these DACs.
Rf
8R 4R 2R R 8R 4R 2R R Vo
S0 VR S 1 VR S2 VR S 3 VR S4 VR S5 VR S6 VR S7 VR
Rf
8R 4R 2R R 8R 4R 2R R Vo
S0 VR S 1 VR S2 VR S 3 VR S4 VR S5 VR S6 VR S7 VR
* Find the value of r for the circuit to work as a regular (i.e., binary to analog) DAC.
Rf
8R 4R 2R R 8R 4R 2R R Vo
S0 VR S 1 VR S2 VR S 3 VR S4 VR S5 VR S6 VR S7 VR
* Find the value of r for the circuit to work as a regular (i.e., binary to analog) DAC.
* Find the value of r for the circuit to work as a BCD to analog DAC.
VR
VA
DN−1
final
value
N-bit analog
digital VA initial
output
input value
D2
D1
D0 t
ground
VR
VA
DN−1
final
value
N-bit analog
digital VA initial
output
input value
D2
D1
D0 t
ground
* When there is a change in the input binary number, the output VA takes a finite time to settle to the new
value.
VR
VA
DN−1
final
value
N-bit analog
digital VA initial
output
input value
D2
D1
D0 t
ground
* When there is a change in the input binary number, the output VA takes a finite time to settle to the new
value.
* The finite settling time arises because of stray capacitances and switching delays of the semiconductor
devices used within the DAC chip.
VR
VA
DN−1
final
value
N-bit analog
digital VA initial
output
input value
D2
D1
D0 t
ground
* When there is a change in the input binary number, the output VA takes a finite time to settle to the new
value.
* The finite settling time arises because of stray capacitances and switching delays of the semiconductor
devices used within the DAC chip.
* Example: 500 ns to 0.2 % of full scale.
Vmax
111
V7R
VR 110
V6R
101
D2 V5R
V′A 100
analog digital
VA D1 V4R
input output
011
D0 V3R
010
V2R
ground 001
V1R
3−bit ADC 000
0
Vmax
111
V7R
VR 110
V6R
101
D2 V5R
V′A 100
analog digital
VA D1 V4R
input output
011
D0 V3R
010
V2R
ground 001
V1R
3−bit ADC 000
0
* If the input VA is in the range VRk < VA < VRk+1 , the output is the binary number corresponding to the
integer k. For example, for VA = VA0 , the output is 100.
Vmax
111
V7R
VR 110
V6R
101
D2 V5R
V′A 100
analog digital
VA D1 V4R
input output
011
D0 V3R
010
V2R
ground 001
V1R
3−bit ADC 000
0
* If the input VA is in the range VRk < VA < VRk+1 , the output is the binary number corresponding to the
integer k. For example, for VA = VA0 , the output is 100.
* We may think of each voltage interval (corresponding to 000, 001, etc.) as a “bin.” In the above example,
the input voltage VA0 falls in the 100 bin; therefore, the output of the ADC would be 100.
Vmax
111
V7R
VR 110
V6R
101
D2 V5R
V′A 100
analog digital
VA D1 V4R
input output
011
D0 V3R
010
V2R
ground 001
V1R
3−bit ADC 000
0
* If the input VA is in the range VRk < VA < VRk+1 , the output is the binary number corresponding to the
integer k. For example, for VA = VA0 , the output is 100.
* We may think of each voltage interval (corresponding to 000, 001, etc.) as a “bin.” In the above example,
the input voltage VA0 falls in the 100 bin; therefore, the output of the ADC would be 100.
* Note that, for an N-bit ADC, there would be 2N bins.
Vmax
111
V7R
VR 110
V6R
101
D2 V5R
V′A 100
analog digital
VA D1 V4R
input output
011
D0 V3R
010
V2R
ground 001
V1R
3−bit ADC 000
0
Vmax
111
V7R
VR 110
V6R
101
D2 V5R
V′A 100
analog digital
VA D1 V4R
input output
011
D0 V3R
010
V2R
ground 001
V1R
3−bit ADC 000
0
Vmax
111
V7R
VR 110
V6R
101
D2 V5R
V′A 100
analog digital
VA D1 V4R
input output
011
D0 V3R
010
V2R
ground 001
V1R
3−bit ADC 000
0
Vmax
111
V7R
VR 110
V6R
101
D2 V5R
V′A 100
analog digital
VA D1 V4R
input output
011
D0 V3R
010
V2R
ground 001
V1R
3−bit ADC 000
0
Vmax
111
V7R
VR 110
V6R
101
D2 V5R
V′A 100
analog digital
VA D1 V4R
input output
011
D0 V3R
010
V2R
ground 001
V1R
3−bit ADC 000
0
Vmax
111
V7R
VR 110
V6R
101
D2 V5R
V′A 100
analog digital
VA D1 V4R
input output
011
D0 V3R
010
V2R
ground 001
V1R
3−bit ADC 000
0
R/2
V7R C6
Vmax R
111
V7R C5
V6R
110
VR
V6R R
101
V5R C4
D2 V5R D2
V′A 100
digital R
analog D1 V4R D1
input VA output C3 LOGIC
011 V4R
D0 V3R D0
010 R
V2R C2
V3R
ground 001
V1R R
3−bit ADC 000
0
V2R C1
V1R C0
R/2
R C5
R C4
D2
R C3
LOGIC D1
D0
R C2
R C1
R C0
R
2
3-bit parallel (flash) ADC VA
VR
R
2 C6
R C5
R C4
D2
R C3
LOGIC D1
D0
R C2
R C1
R C0
R
2
* Practical difficulty: As the input changes, the comparator outputs (C0 , C1 , etc.) may not settle to their new values at the
same time. → ADC output will depend on when we sample it.
3-bit parallel (flash) ADC VA
VR
R
2 C6
R C5
R C4
D2
R C3
LOGIC D1
D0
R C2
R C1
R C0
R
2
* Practical difficulty: As the input changes, the comparator outputs (C0 , C1 , etc.) may not settle to their new values at the
same time. → ADC output will depend on when we sample it.
* Add D flip-flops. Allow sufficient time (between the change in VA and the active clock edge) so that the comparator
outputs have already settled to their new values before they get latched in.
VA
VA VR
3-bit parallel (flash) ADC VR
R
R C6
C6
2 D Q6
2 Q
R C5
R C5 D Q5
Q
R C4
R C4 D Q4
Q
D2 D2
R C3
R C3 D Q3
LOGIC D1 Q LOGIC D1
D0 R C2 D0
R C2 D Q2
Q
R C1
R C1 D Q1
Q
R C0
R C0 D Q0
Q
R
R
2 Clock
2
* Practical difficulty: As the input changes, the comparator outputs (C0 , C1 , etc.) may not settle to their new values at the
same time. → ADC output will depend on when we sample it.
* Add D flip-flops. Allow sufficient time (between the change in VA and the active clock edge) so that the comparator
outputs have already settled to their new values before they get latched in.
M. B. Patil, IIT Bombay
Parallel (flash) ADC
VA * In the parallel (flash) ADC, the conversion gets
VR
R done “in parallel,” since all comparators operate
2 C6 on the same input voltage.
D Q6
Q
R C5
D Q5
Q
R C4
D Q4
Q
D2
R C3
D Q3
Q LOGIC D1
R C2 D0
D Q2
Q
R C1
D Q1
Q
R C0
D Q0
Q
R
2 Clock
R C2 D0
D Q2
Q
R C1
D Q1
Q
R C0
D Q0
Q
R
2 Clock
R C2 D0
D Q2
Q
R C1
D Q1
Q
R C0
D Q0
Q
R
2 Clock
R
D2 * 2N comparators are required for N-bit ADC →
C3
D Q3 generally limited to 8 bits.
Q LOGIC D1
R C2 D0
D Q2
Q
R C1
D Q1
Q
R C0
D Q0
Q
R
2 Clock
Va Vs
clock
Tc
Vs
S buffer
Va buffer C t
Va Vs
clock
Tc
Vs
S buffer
Va buffer C t
* An ADC typically operates on a “sampled” input signal (Vs (t) in the figure) which is derived from the continuously
varying input signal (Va (t) in the figure) with a “sample-and-hold” (S/H) circuit.
Va Vs
clock
Tc
Vs
S buffer
Va buffer C t
* An ADC typically operates on a “sampled” input signal (Vs (t) in the figure) which is derived from the continuously
varying input signal (Va (t) in the figure) with a “sample-and-hold” (S/H) circuit.
* The S/H circuit samples the input signal Va (t) at uniform intervals of duration Tc , the clock period.
Va Vs
clock
Tc
Vs
S buffer
Va buffer C t
* An ADC typically operates on a “sampled” input signal (Vs (t) in the figure) which is derived from the continuously
varying input signal (Va (t) in the figure) with a “sample-and-hold” (S/H) circuit.
* The S/H circuit samples the input signal Va (t) at uniform intervals of duration Tc , the clock period.
* When the clock goes high, switch S (e.g., a FET or a CMOS pass gate) is closed, and the capacitor C gets charged to the
signal voltage at that time. When the clock goes low, switch S is turned off, and C holds the voltage constant, as desired.
Va Vs
clock
Tc
Vs
S buffer
Va buffer C t
* An ADC typically operates on a “sampled” input signal (Vs (t) in the figure) which is derived from the continuously
varying input signal (Va (t) in the figure) with a “sample-and-hold” (S/H) circuit.
* The S/H circuit samples the input signal Va (t) at uniform intervals of duration Tc , the clock period.
* When the clock goes high, switch S (e.g., a FET or a CMOS pass gate) is closed, and the capacitor C gets charged to the
signal voltage at that time. When the clock goes low, switch S is turned off, and C holds the voltage constant, as desired.
* Op-amp buffers can be used to minimise loading effects.
M. B. Patil, IIT Bombay
Successive Approximation ADC
D3 D2 D1 D0
4−bit DAC
VDAC
o
C
VA
Comparator
D3 D2 D1 D0
4−bit DAC
VDAC
o
C
VA
Comparator
* Suppose we have a 4-bit DAC. We can use it to perform A-to-D conversion by successively setting the four
bits as follows.
D3 D2 D1 D0
4−bit DAC
VDAC
o
C
VA
Comparator
* Suppose we have a 4-bit DAC. We can use it to perform A-to-D conversion by successively setting the four
bits as follows.
- Start with D3 D2 D1 D0 = 0000, I = 3.
D3 D2 D1 D0
4−bit DAC
VDAC
o
C
VA
Comparator
* Suppose we have a 4-bit DAC. We can use it to perform A-to-D conversion by successively setting the four
bits as follows.
- Start with D3 D2 D1 D0 = 0000, I = 3.
- Set D[I] = 1 (keep other bits unchanged).
D3 D2 D1 D0
4−bit DAC
VDAC
o
C
VA
Comparator
* Suppose we have a 4-bit DAC. We can use it to perform A-to-D conversion by successively setting the four
bits as follows.
- Start with D3 D2 D1 D0 = 0000, I = 3.
- Set D[I] = 1 (keep other bits unchanged).
- If VoDAC > VA (i.e., C = 0), set D[I] = 0; else, keep D[I] = 1.
D3 D2 D1 D0
4−bit DAC
VDAC
o
C
VA
Comparator
* Suppose we have a 4-bit DAC. We can use it to perform A-to-D conversion by successively setting the four
bits as follows.
- Start with D3 D2 D1 D0 = 0000, I = 3.
- Set D[I] = 1 (keep other bits unchanged).
- If VoDAC > VA (i.e., C = 0), set D[I] = 0; else, keep D[I] = 1.
- I ← I − 1; go to step 1.
D3 D2 D1 D0
4−bit DAC
VDAC
o
C
VA
Comparator
* Suppose we have a 4-bit DAC. We can use it to perform A-to-D conversion by successively setting the four
bits as follows.
- Start with D3 D2 D1 D0 = 0000, I = 3.
- Set D[I] = 1 (keep other bits unchanged).
- If VoDAC > VA (i.e., C = 0), set D[I] = 0; else, keep D[I] = 1.
- I ← I − 1; go to step 1.
* At the end of four steps, the digital output is given by D3 D2 D1 D0 .
Example → next slide.
30 k
24 k
23 k
D4 D3 D2 D1 D0
VA
22 k
20 k
20 k
VR 5−bit DAC 16 k
VDAC
o
D4 =1 D4 =1 D4 =1 D4 =1 D4 =1
C D3 =0 D3 =1 D3 =0 D3 =0 D3 =0
VA 10 k D2 =0 D2 =0 D2 =1 D2 =1 D2 =1
D1 =0 D1 =0 D1 =0 D1 =1 D1 =1
D0 =0 D0 =0 D0 =0 D0 =0 D0 =1
(Note: k ∝ VR )
C=1 C=0 C=1 C=1 C=0
→ reset D3 → reset D0
1 2 3 4 5 step
30 k
24 k
23 k
D4 D3 D2 D1 D0
VA
22 k
20 k
20 k
VR 5−bit DAC 16 k
VDAC
o
D4 =1 D4 =1 D4 =1 D4 =1 D4 =1
C D3 =0 D3 =1 D3 =0 D3 =0 D3 =0
VA 10 k D2 =0 D2 =0 D2 =1 D2 =1 D2 =1
D1 =0 D1 =0 D1 =0 D1 =1 D1 =1
D0 =0 D0 =0 D0 =0 D0 =0 D0 =1
(Note: k ∝ VR )
C=1 C=0 C=1 C=1 C=0
→ reset D3 → reset D0
1 2 3 4 5 step
th
* At the end of the 5 step, we know that the input voltage corresponds to 10110.
30 k
24 k
23 k
D4 D3 D2 D1 D0
VA
22 k
20 k
20 k
VR 5−bit DAC 16 k
VDAC
o
D4 =1 D4 =1 D4 =1 D4 =1 D4 =1
C D3 =0 D3 =1 D3 =0 D3 =0 D3 =0
VA 10 k D2 =0 D2 =0 D2 =1 D2 =1 D2 =1
D1 =0 D1 =0 D1 =0 D1 =1 D1 =1
D0 =0 D0 =0 D0 =0 D0 =0 D0 =1
(Note: k ∝ VR )
C=1 C=0 C=1 C=1 C=0
→ reset D3 → reset D0
1 2 3 4 5 step
th
* At the end of the 5 step, we know that the input voltage corresponds to 10110.
* For the digital representation to be accurate up to ± 12 LSB, ∆V corresponding to 1
2 LSB is added to VA (see [Taub]).
VA
V′A (t) S/H Successive
Control Approximation
logic N−bit SAR
D4 D3 D2 D1 D0 VDAC
o
Register
Comparator
clock
digital
VR 5−bit DAC output
VDAC
o
C
VA VR N−bit DAC
VA
V′A (t) S/H Successive
Control Approximation
logic N−bit SAR
D4 D3 D2 D1 D0 VDAC
o
Register
Comparator
clock
digital
VR 5−bit DAC output
VDAC
o
C
VA VR N−bit DAC
* Each step (setting SAR bits, comparison of VA and VoDAC ) is performed in one clock cycle → conversion
time is N cycles, irrespective of the input voltage value VA .
VA
V′A (t) S/H Successive
Control Approximation
logic N−bit SAR
D4 D3 D2 D1 D0 VDAC
o
Register
Comparator
clock
digital
VR 5−bit DAC output
VDAC
o
C
VA VR N−bit DAC
* Each step (setting SAR bits, comparison of VA and VoDAC ) is performed in one clock cycle → conversion
time is N cycles, irrespective of the input voltage value VA .
* S. A. ADCs with built-in or external S/H (sample-and-hold) are available for 8- to 16-bit resolution and
conversion times of a few µsec to tens of µsec.
VA
V′A (t) S/H Successive
Control Approximation
logic N−bit SAR
D4 D3 D2 D1 D0 VDAC
o
Register
Comparator
clock
digital
VR 5−bit DAC output
VDAC
o
C
VA VR N−bit DAC
* Each step (setting SAR bits, comparison of VA and VoDAC ) is performed in one clock cycle → conversion
time is N cycles, irrespective of the input voltage value VA .
* S. A. ADCs with built-in or external S/H (sample-and-hold) are available for 8- to 16-bit resolution and
conversion times of a few µsec to tens of µsec.
* Useful for medium-speed applications such as speech transmission with PCM.
M. B. Patil, IIT Bombay
Counting ADC (digital-ramp ADC)
digital
output VA
clock
VR N−bit DAC
VDAC Comparator Tc
o
VA S/H t
C Tc
digital
output VA
clock
VR N−bit DAC
VDAC Comparator Tc
o
VA S/H t
C Tc
* The “start conversion” signal clears the counter; counting begins, and VoDAC increases with each clock cycle.
digital
output VA
clock
VR N−bit DAC
VDAC Comparator Tc
o
VA S/H t
C Tc
* The “start conversion” signal clears the counter; counting begins, and VoDAC increases with each clock cycle.
* When VoDAC exceeds VA , C becomes 0, and counting stops.
digital
output VA
clock
VR N−bit DAC
VDAC Comparator Tc
o
VA S/H t
C Tc
* The “start conversion” signal clears the counter; counting begins, and VoDAC increases with each clock cycle.
* When VoDAC exceeds VA , C becomes 0, and counting stops.
* Simple scheme, but (a) conversion time depends on VA , (b) slow (takes (2N − 1) clock cycles in the worst case)
→ tracking ADC
M. B. Patil, IIT Bombay
Tracking ADC
Up/Down
VDAC
o
clock
N−bit Counter
Tc VA
digital
output
VR N−bit DAC
Comparator
VA S/H t
Tc
C
VDAC
o
Up/Down
VDAC
o
clock
N−bit Counter
Tc VA
digital
output
VR N−bit DAC
Comparator
VA S/H t
Tc
C
VDAC
o
Up/Down
VDAC
o
clock
N−bit Counter
Tc VA
digital
output
VR N−bit DAC
Comparator
VA S/H t
Tc
C
VDAC
o
Up/Down
VDAC
o
clock
N−bit Counter
Tc VA
digital
output
VR N−bit DAC
Comparator
VA S/H t
Tc
C
VDAC
o
S
T1 T2
0
C t
VA
VR
VR Vi R Z slope = −
1 RC
Vo = − Vi dt −V1
RC
VA
slope = −
RC
S
T1 T2
0
C t
VA
VR
VR Vi R Z slope = −
1 RC
Vo = − Vi dt −V1
RC
VA
slope = −
RC
S
T1 T2
0
C t
VA
VR
VR Vi R Z slope = −
1 RC
Vo = − Vi dt −V1
RC
VA
slope = −
RC
S
T1 T2
0
C t
VA
VR
VR Vi R Z slope = −
1 RC
Vo = − Vi dt −V1
RC
VA
slope = −
RC
S
T1 T2
0
C t
VA
VR
VR Vi R Z slope = −
1 RC
Vo = − Vi dt −V1
RC
VA
slope = −
RC
S
T1 T2
0
C t
VA
VR
VR Vi R Z slope = −
1 RC
Vo = − Vi dt −V1
RC
VA
slope = −
RC
S
T1 T2
0
C t
VA
VR
VR Vi R Z slope = −
1 RC
Vo = − Vi dt −V1
RC
VA
slope = −
RC
SPDT
A C T1 = 2N Tc T2
VA comparator
0
VR B R
Vo t
VR
slope = −
integrator RC
−V1
VA
N−bit Counter
slope = −
RC
overflow clock
clock
digital output Tc
SPDT
A C T1 = 2N Tc T2
VA comparator
0
VR B R
Vo t
VR
slope = −
integrator RC
−V1
VA
N−bit Counter
slope = −
RC
overflow clock
clock
digital output Tc
SPDT
A C T1 = 2N Tc T2
VA comparator
0
VR B R
Vo t
VR
slope = −
integrator RC
−V1
VA
N−bit Counter
slope = −
RC
overflow clock
clock
digital output Tc
SPDT
A C T1 = 2N Tc T2
VA comparator
0
VR B R
Vo t
VR
slope = −
integrator RC
−V1
VA
N−bit Counter
slope = −
RC
overflow clock
clock
digital output Tc
* K. Gopalan, Introduction to Digital Microelectronic Circuits, Tata McGraw-Hill, New Delhi, 1998.
* H. Taub and D. Schilling, Digital Integrated Electronics, McGraw-Hill, 1977.