Digital IC-Design Digital IC-Design

Chapter 5 Fundamental
parameters
for digital gates
The CMOS Inverter

Goal With This Chapter Robustness

Analyze Fundamental Parameters

Noise - “unwanted variations of voltages and
A general understanding of the inverter
currents in logical
g nodes”
behavior is useful to understand more complex
functions
Classical noise such as thermal and flicker noise are
not critical in digital design
Outline
Noise
Noise sources in digital circuits are
Reliability
Capacitive coupling
P f
Performance
Inductive coupling
Power Consumption Power and ground noise

1
Capacitive and Inductive Coupling Power and Ground Noise

V A voltage or a current A big

change may influence problem on
VDD large
CCoupling th signal
the i l on a parallel
ll l RWire
V VDD synchronously
wire, especially when: clocked chips
ISwitch
Long wires V On chip
Sub micron tech. decoupling
I
Many metal layers capacitors
p helps
p
Mutual
Inductance (≈ 1/10 of the
Conclusion: The world is switched C)
I
not digital. We need to
know the limitations

Definitions DC Operation

Voltage Transfer
Characteristic (VTC)
5 VIN VOUT
VOH

DC Operation 4
Switching Threshold
Noise Margins VM when VIN = VOUT

VOUT
3
Vout = VIN
Fan OUT - Fan IN VM
Balanced if VM = VDD/2
2

1
Logical “1” at VOH
VOL Logical “0” at VOL
1 2 3 4 5

VIN

2
Analog versus Digital Signals Analog versus Digital Signals

Nominal Accepteble
VOUT
VOH, VOL = nominal Output Levels Input Levels
The noise margins
5

output
t t voltage
lt
VOH

4
VOH are defined as the
NMH difference
3
VIH between VOH/VOL
VIH, VIL = acceptable
Slope = -1
Undefined and VIH/VIL
2
input voltage Region
1 NML = VIL - VOL
O
VIL NMH = VOH - VIH
VOL NML
1 2 3 4 VIN VOL
VIL VIH

Fan-In and Fan-Out The Ideal Gate

VOUT
Fan-in = M Fan-out = N
Rin=∞
Rout=0
Noise Margin=VDD/2
Gain = ∞
Fan-in = The Fan-out = The
number of number of
inputs to the gates that loads
gate the gate VIN

3
A Real Gate Dynamic Definitions

NML = VIL - VOL = 0.75 - 0.50 = 0.25V

5
Propagation delay
NMH = VOH - VIH = 3.50 - 2.25 = 1.25V
4
VOH VM = 1.75V Rise and fall time
Power consumption
VOUT

VIL VDD
3

VM
2

1 VIH
VOL
GND
1 2 3 4 5

VIN

Delay Definitions Ring Oscillator – minimum tp

V1 V2 V3 V4 V5
VIN
Odd # of
50% inverters
V1
t pHL + t pLH “De-facto
tpHL tpLH t tp = V2
2 Standard” for
VOUT 90% V3 performance
50% V2
Fan-out = 1
10% V5
tf tr t
2 N tp t

4
Ring Oscillator Power Dissipation

Do tp = 100ps mean 10 GHz chip? Two measures are important

Peak power (Sets wire dimensions)
Good Custom Design ≈ 1/10
Synthesized design ≈ 1/50 - 1/100 Ppeak = VDD × iDD max

Why? V1 V2 V3 V4 V5
Average power (Battery and cooling)
Low load
Short Wires T
V
Pav = DD ∫ iDD (t ) dt
Fan-out = 1
Low complexity
T 0

Power-Delay Product Digital IC-Design

PDP = t p × Pav ( J )
The CMOS Inverter
Energy per operation

Energy per switching event

5
Inverters The CMOS Inverter

VDD
On-chip resistors are large VDD + Lower static power
St ti power consumption
Static ti consumption
ti
VOL ≠ 0 + VOH = VDD; VOL = 0
GND
Large tpLH + tpLH = tpHL If properly designed
+ Low Impedance connection
to ground and VDD
VDD
Extra process step
Static power consumption
VOL ≠ 0 - More fab. stages
Large tpLH GND - Lower hole mobility
GND

The CMOS Inverter The CMOS Inverter

VDD VDD
Wider PMOS to
Shared power and ground compensate for
lower mobility
GND
Cascaded Abuted cells GND VDD
VDD
VDD VDD

In Out In Out In Out In Out

GND GND
GND GND

6
CMOS Inverter - Model CMOS Static Behavior

VDD
Complementary i.e. output
Req-p
y a low impedance
have always p Load characteristics
connection to GND or VDD
VTC
VOH = VDD Switching threshold
CL
VOL = 0
Noise margin
g
Req-n
VM = f(Req-n, Req-p)
VM = VDD/2 if Req-n = Req-p

Load Lines Inverter Load Characteristics

The VTC can be determined graphically

N-channel P-channel
IDn = -IDp ID VGS=5V Vin=0V - IDp IDn VGS=5V

VDS Vin = VDD-V

VGSp
ID VGS=4V Vin=1V VGS=4V
VGS=5V ID
VGS=3V Vin=2V VGS=3V

VGS=-3V

VGS=4V VDS VDS

VGS=-4V
VGS=-3V Vout = VDD-VDSp
VGS=3V VGS=-4V

Vin = Vout =
VGS=-5V VDD-VGSp VDD-VDSp
VGS=-5V

VDS

7
Inverter Load Characteristics Region: Linear - Saturation

Vin=0V
I Vin=5V

Vin=0V
I Vin=5V
5
N sat
N off
VOUT P lin P lin
Vin=1V Vin=4V
4
Vin=2V Vin=3V

Vin=1V Vin=4V 3 VM
N sat Vin=3V Vin=2V
P sat Vout
2
Vin=2V Vin=3V

VM 1
N lin
Vin=3V Vin=2V N lin
P sat P off
Vout 1 2 3 4
VIN 5

CMOS Inverter VTC Switching Threshold Long Channel

Transistors
VTC graphically
extracted from the Both transistors are saturated
5

VOUT VOH= VDD l d li

load lines k
kn
4 (VM − VTn ) 2 = −(− p (VM − VDD − VTp ) 2 ) ⇒
2 2
High noise margin
3
NMH=VOH-VIH ≈ 5-2.9 = 2.1V
kp
VM= VDD/2 VM − VTn = − (−VM + VDD + VTp ) ⇒
NML =VIL-VOL ≈ 2.1-0 = 2.1V kn
2

VM + r × VM = VTn + r × (VDD + VTp ) ⇒

1

VOL= 0 VTn + r (VDD + VTp ) −k p

⇒ VM = with r =
1 2 3 4 5
1+ r kn
VIN

8
Switching Threshold Long Channel Switching Threshold
Transistors
r (VDD + VTp ) + VTn −k p r (VDD + VTp ) + VTn −k p
VM = with r = (VTn = -VTp = 0.5 V) VM = with r =
1+ r kn 1+ r kn
5

5 5
VM
4
VM
4
VM
4
Moderate deviation from
kp/kn = 1 gives only 3

3 3
small changes in VM 2

2 2

Wp = 2Wn common to t 1
1 1
save area, since the
change in VM is small 0.1 0.32 1 3.2
1 2 4 6 8
kp/kn10 0.1 0.32 1 3.2
kp/kn10 kp/kn10

Wp≈3Wn

Switching Threshold: Example Simulated VTC: Short Channel

Inverter with W/L = 0.6 μ / 0.35 μ Balanced 0.25μm inverter

VTn = 0.50, kn = 300 μ, VTp = - 0.65, kp = -103 μ 2.5

−k p 103μ
r= = = 0.59
2

kn 300μ VDD = 3V
1.5

(V)
r (VDD + VTp ) + VTn
VM = =

out
V
1+ r 1

0.59 (3 − 0.65) + 0.5 0.5

= 1.18 V
1 + 0.59 GND
0
0 0.5 1 1.5 2 2.5
V (V)
in

9
 VTC: Short Channel Wp 0.375 VTC: Short Channel
=
Lp 0.25
0.25

Minimum sized 0.25μm transistors ID (mA)

Wn 0.375 VIN = 2.5
0.25 = 0.20
Ln 0.25
ID (mA) VGS = 2.5
25 0 25
0.25
ID (mA) VGS = 2.5
0.20 0.20
VIN = 1.875
0.15 VGS = 1.875
0.15 VGS = 1.875
0.10
0.10
VIN = 0
0.10 VGS = 1.25
0.05
VGS = 1.25 VGS = 1.0 VIN = 1.25

0.05 PMOS 0
VGS = -0.625
VGS = -1.25
VGS = 0.625
VIN = 0.625

VGS = 1.0
10 VIN = 1.0
10 VIN = 1.0
10
VGS = -1.25 VIN = 1.25
VGS = -0.625 VGS = 0.625 -0.05
0 VGS = -1.5
VDS (V) VIN = 1.875 VIN = 0.625
NMOS
VGS = -2.5 VGS = -1.875
0 0.5 1.0 1.5 2.0 2.5
-0.10
-2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 VOUT (V)
-0.05
VGS = -1.5
VGS = -2.5 VGS = -1.875 VDS (V)
-0.10 Move the PMOS part to the first quadrant
-2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5

VTC: Short Channel - Graphically Switching Threshold: Short Channel

0.25
ID (mA) Vout (V)
Vout (V)
VIN = 2.5 2.5
0.20 2.5
20
2.0

VTC
The threshold
2.0
1.5

VM is when
VIN = 1.875
1.5

VIN=VOUT
1.0
VM =1 V
0.10
VIN = 0 1.0
0.5
VIN = 1.25
VIN = 0.625 0.5
VIN = 1.0 VIN = 1.0 0 0.5 1.0 1.5 2.0 2.5
VIN = 1.25
Vin (V)
VIN = 1.875 VIN = 0.625 0
0 0.5 1.0 1.5 2.0 2.5
0.5 1.0 1.5 2.0 2.5
VOUT (V) Vin (V)

10
Switching Threshold: Short Channel Example 0.25 μm technology

Minimum transistor dimensions

Both NMOS and PMOS are velocity saturated
VDSATn = 0.63; VDSATp = −1; VTn = 0.43; VTp = −0.4; Parameters from
the inside back
2 2 0.375 0.375
VDSATn VDSATp kn = ×115 = 172.5; k p = × (−30) = −45 cover in the book
kn ((VM −VTn )VDSATn − ) = k p ((VDD −VM + VTp )VDSATp + ) 0.25 0.25
2 2
k p VDSATp −45× (−1)
Solving VM yields r= = = 0.41
kn VDSATn 172.5× 0.63

VDSATn ⎛ V ⎞
VTn +
VDSATn ⎛ V ⎞
+ r ⎜VDD +VTp + DSATp ⎟ 0.43 + 0.63 + 0.41⎛⎜ 2.5 − 0.4 − 1 ⎞⎟
VTn + + r ⎜VDD +VTp + DSATp ⎟
2 ⎝ 2 ⎠ k p VDSATp VM =
2 ⎝ 2 ⎠
=
2 ⎝ 2⎠
= 1.0 V
VM = where r = 1+ r 1+ 0.41
1+ r kn VDSATn

Example 0.25 μm technology Balancing the inverter

IF VDD >> VDSAT and VT It is desirable to have VM around VDD/2

2
⎛ V ⎞ Wn V 2 W V
V
VTn + DSATn + r ⎜VDD + VTp + DSATp ⎟ kn' ((VM −VTn )VDSATn − DSATn ) = k p' p ((VDD −VM + VTp )VDSATp + DSATp )
2 ⎝ 2 ⎠ r VDD 0.41× 2.5 Ln 2 Lp 2
VM = ≈ = = 0.73 V
1+ r 1+ r 1+ 0.41
Assuming Ln = Lp yields

VDD not high enough in this case VDSATn2

Wp kn' ((VM −VTn )VDSATn −)
= 2
Wn V 2
k p' ((VDD −VM +VTp )VDSATp + DSATp )
2

11
 Balancing the inverter Balancing the inverter
1.8

Example using the same data 1.7

1.6

2 2 15
1.5
VDSATn 0.63
Wp kn' ((VM −VTn )VDSATn −
) 115× ((1.25 − 0.43) × 0.63 − ) 1.4

V (V)
= 2 = 2 = 3.5 1.3
−1

M
2
Wn V
−k p' ((VDD +VM −VTp )VDSATp + DSATp ) −30 × (−2.5 +1.25 − (−0.4) − ) 1.2

2 2 1.1

To be balanced, The PMOS should be 3.5 0.9

times wider than the NMOS 0

0.8
8
10
0
2 10
1

W p /W n

For the minimal NMOS with Wn=0.375 μm, VM is rather insensitive to changes in the device ratio
the corresponding PMOS has Wp=1.3 μm A ratio decrease from 3.5 to 2 yields VM = 1.13 V
which often is acceptable
Saves area

Determining VIH and VIL Determining VIH and VIL

VIH and VIL when ∂VOUT Vout (V)

the slope is -1
⇒ = −1 VIL A simplified
∂Vin
2.5
piecewise linear VTC
p
2.0
A reasonable
ΔVOUT
2.5

2 approximation is 1.5
g=
1.5
to use the gain (g) 1.0
VM
ΔVin
around VM
(V)
out
V

1
0.5

ΔVOUT
g=
0.5
VIH

ΔVin
0
0 0.5 1.0 1.5 2.0 2.5
0 0.5 1 1.5 2 2.5
V (V)
in
Vin (V)

12
 Determining VIH and VIL ΔVOUT The Inverter Gain (g) Derived at
g=
ΔVin page 189

VDD −VM
Vout (V) g= 1 knVDSATn + k pVDSATp 1+ r
VIL −VM g =− ≈−
2.5 VIL
I D (VM ) λn − λp VDSAT
(VM −VTn − DSATn )(λn − λp )
VDD −VM 2
2.0
VIL = VM +
VDD-VM g 0

-2
1.5
-4
Note that the gain is
VM
very
y sensitive to the
-6
1.0
VM-VIL VM
g=
-8
8

channel-length

gain
VM −VIH
-10
0.5

modulation
-12

VIH -14

V
0 0.5 1.0 1.5 2.0 2.5 VIH = VM − M -16

Vin (V) g -18

0 0.5 1
V (V)
1.5 2 2.5

in

Noise Margins Example (Minimum sized transistors)

VDD −VM 1+ r
Vout (V)
VIL = VM + Vout (V) g ≈−
V
=
2.5 VIL g 2.5 VIL (VM −VTn − DSATn )(λn − λp )
2
V
2.0
VIH = VM − M 2.0
VDD-VM
g VDD-VM 1 + 0.41
1.5 1.5 =− =
0.63
(1 − 0.43 − )(0.06 + 0.1)
1.0
VM
1.0
VM 2
VM-VIL NMH = VDD −VIH ; NML = VIL VM-VIL
0.5 0.5 = −34.6
VIH VIH
0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5
Vin (V) Vin (V)

13
 Example (Minimum size transistors) CMOS Dynamic Behavior

VDD −VM 2.5 −1

Vout (V) VIL = VM + = 1+ = 0.96 V
2.5 VIL g −34.6
V 1
VIH = VM − M = 1− = 1.03 V Capacitors
2.0
g −34.6
Propagation delay
VDD-VM
1.5

VM NMH = VDD −VIH = 2.5 − 0.96 = 1.54 V Power consumption

1.0
VM-VIL NML = VIL = 1.03
1 03 V
0.5

VIH Slightly to large

0 0.5 1.0 1.5 2.0 2.5 values due to the
Vin (V) approximation

Inverter Load Vin Vout Inverter Load

Cgd = Overlap Capacitance

Capacitance model CL
for propagation Cdb = Junction Capacitance
d l
delay calculations
l l ti Cw = Wire
Wi Capacitance
C i
VDD
Cg = Overlap & Gate Capacitance
VDD

Vin
i
Cgd2
d2 Cdb2 Voutt Cg44 Vout2
t2
Vin Cgd2 Cdb2 Vout Cg4 Vout2

Cgd1 Cdb1 Cw Cg3

Cgd1 Cdb1 Cw Cg3

14
 Cgd - Overlap Capacitance The Miller Effect

Assumed to be in Cut-off or Saturation

- No Channel Capacitance (at output side) If Cgd is modeled from Vout to
- Only Overlap Capacitance GND, the value shall be doubled
GND

Cgd
VDD
ΔV ΔV
ΔV ΔV
2Cgdd
Vin Cgd2 Cdb2 Vout Cg4 Vout2

Cgd1 Cdb1 Cw Cg3 Cgd = 2 Cgd0 W

Cdb - Junction Capacitance Cw - Wire Capacitance

Cdb = Keq × C j 0 Neglected on short distances

Depends on grading coefficient I
Increased
d importance
i t in
i new technologies
t h l i
Diode area and perimeter

VDD VDD

Vin Cgd2 Cdb2 Vout Cg4 Vout2 Vin Cgd2 Cdb2 Vout Cg4 Vout2

Cgd1 Cdb1 Cw Cg3 Cgd1 Cdb1 Cw Cg3

15
Channel Capacitance Cg - Gate Capacitance

Region Cg C gs C gd Overlap – Cgs (Not Cgd)

Cut off C OX WL eff 0 0 Ch l – WLCox
Channel
Linear 0 (1/2)C OX WL eff (1/2)C OX WL eff
Saturation 0 (2/3)C OX WL eff 0
VDD

Cut off: No channel ⇒ CG = CGB

Linear: Channel ⇒ Divide channel in two parts Vin Cgd2 Cdb2 Vout Cg4 Vout2

Saturation: ≈ 2/3 Channel connected to source Cgd1 Cdb1 Cw Cg3

Inverter Load Model Inverter - Transient Response

t
-
Capacitor Expression Vout = (1- e RC )V ; tr = t90 - t10
VDD t10 t10
Cgdd 2Cgd0
d0W − −
Req-p 0.1VDD = (1 − e RC
)VDD ⇔ 0.9 = e RC
⇔
Model
Cdb Keq(ACj+PCjsw) t10 = − RC ln(0.9)
Vin
Vout
Cg Cgs0W+CoxWL CL
t90 = − RC ln(0.1)
CL
Cw Area + Fringe
g Cap.
p
tr = t90 − t10 = (− ln(0.1)
l ( ) + ln(0.9))
l ( )) RC = tr = 2.2 RC
Req-n
The values differ for n- and p-channel
The values differ for L to H / H to L t pHL = t50 = − ln(0.5) RC = t pHL = 0.69 RC
Se table 5-2

16
Req in Short Channel Transistors Digital IC-Design

Rn (VOUT =VDD ) + Rn (VOUT =VDD / 2)

Chapter 5
Req -n = =
2
⎡VDS ⎤ ⎡ VDS ⎤ The CMOS Inverter
⎢ ⎥ + ⎢ ⎥
⎣ I D ⎦ (VOUT =VDD ) ⎣ I D ⎦ (VOUT =VDD / 2)
=
Cont.
Req -n
2

Req in Short Channel Transistors Req in Short Channel Transistors

Graphical
Graphical Method
Method
I D (mA)
VGS = 2 V
I D VDD / 2 = 145 μ A; I D VDD = 153 μ A;
0 15
0.15
I D VDD = 153 μ A

I D VDD / 2 = 145 μ A
0.1 ⎡VDS ⎤ ⎡V ⎤
⎢I ⎥ + ⎢ DS ⎥
In Velocity ⎣ D ⎦ (VOUT =VDD ) ⎣ I D ⎦ (VOUT =VDD / 2)
05
0.5 Saturation Req -n = =
2
2 1
+
VDS (V)
−6
= 153 × 10 145 ×10−6 = 10 kΩ
0
0 0.63 V 1 2
Req -n
2

17
Req in Short Channel Transistors Req for Short Channel NMOS
I D (mA)

Find IDSAT
0.15
VGS = 2 V
Model Based Method
0.1

VDD = 2 V; VT = 0.43 V; I DSAT

⎛ VDD ⎞ 0.5

1⎜ VDD ⎟ 3 VDD ⎛ 5 ⎞ VDSAT = 0.63 V; kn' = 115 mA/V 2

Req = ⎜ + 2 ≈ 1 − λV
VDD ⎟ 4 I DSAT ⎜⎝ 6 DD ⎟⎠
VDS (V)

2 ⎜ I DSAT (1 + λVDD ) I )⎟ W = 0.375 μ m; = 0.25 μ m

0

DSAT (1 + λ
0 0.63 V 1 2

⎝ 2 ⎠
IDSAT = ID when
W ⎛ V2 ⎞ VDS = 0
⎛ V2 ⎞ I DSAT =k'
⎜⎜ (VDD − VT )VDSAT − DSAT ⎟⎟ =
with I DSAT = k ⎜ (VDD − VT )VDSAT − DSAT ⎟ In Velocity n
L ⎝ 2 ⎠ (extrapolated)
⎜ 2 ⎟⎠ Saturation
⎝ 0.375 ⎛ 0.63 ⎞ 2
I DSAT = 115 ⎜ (2 − 0.43)0.63 − ⎟ = 136 μ A
0.25 ⎝ 2 ⎠

Req in Short Channel Transistors Inverter - Transient Response

I DSAT = 136 μ A; λ =0.06 V

VDD
⎛ VDD ⎞ Req-p CL = 2 fF ; Req − n = 10 k Ω
1⎜ VDD ⎟ 3 VDD ⎛ 5 ⎞
⎜1 − λVDD ⎟
Req = ⎜ + 2 ≈
2 ⎜ I DSAT (1 + λVDD ) I VDD ⎟ 4 I DSAT ⎝ 6 ⎠
(1 + λ ) ⎟
⎝ 2 ⎠
DSAT

tr = 2.2 RC = 2.2 × 10 × 103 × 2 × 10−15 = 44 ps

⎛ 2 ⎞ CL
1⎜ 2 2 ⎟ 3 2 ⎛ 5 ⎞
Req = ⎜ + ⎟≈ ⎜1 − 0.06
0 06 × 2 ⎟
2 ⎜ 136 ×10−6 (1 + 0.06 × 2) 136 × 10−6 (1 + 0.06 × 2 ) ⎟ 4 136 × 10−6 ⎝ 6 ⎠ t pHL = 0.69 0 69 × 10 × 103 × 2 × 10−15 = 14 ps
0 69 RC = 0.69
⎝ 2 ⎠ Req-n

Req = 10.0 kΩ ≈ 9.9 kΩ (1 % error)

18
 Inverter - Propagation Delay Propagation Delay (page 202)
Long Channel Short
Q = C × ΔU = CL (VOH - VOL ) / 2 = CLVDD / 2 Transistors
Channel
Q = I ×t =
kn k
(VGS - VT ) 2 × t pHL = n (VDD - VT ) 2 × t pHL 3 CLVDD
Transistors
2 2 t pHL = 0.69 =
4 I DSAT
CLVDD CL CLVDD
t pHL = ≈ = 0.52
2 VDSATn
kn (VDD - VT ) knVDD
V knVDSATn (VDD − VTn − ) V
2
C 1 1
tp = L ( + )
2VDD kn k p CL CL

Ideal Vin (Step)

Ideal Vin (Step)

Propagation Delay Simulation Short Channel

What Ratio Should be Chosen? Short-channel
Transistors Transistors
-11
x 10
5
Wp
t pLH t pHL Fan-Out = 1 β= Fan-Out = 1
4.5 Wn
tp
β=3.5 balance the inverter (VM=VDD/2)
t (sec)

t p (s)4 V
β=2 (or 2.4) for equal delays
p

CL Wp
3.5
(tpLH=tpHL) V
Wn CL
3 However, β=2 might be acceptable
1 1.5 2 2.5 3 3.5 4 4.5 5
β
β = Wp/Wn (VM≈0.45 VDD)

A ratio around 2 is close to optimum

19
Effect of Input Rise Time Digital IC-Design

tpHL Increase
tpHL [ns] Note the linearly with the
0 35
0.35 gain
input rise time trise
0.30
Driving a Large Fan-out
0.25 tr2
t pHL ( actual ) = t 2pHL ( step ) +
4
0.20

0.15
0.2 0.4 0.6 0.8 1.0
trise [ns]

Inverter Chain Driving a Large Fan-Out

Typical examples: Driving a large

In Out capacitance
Busses
CL Clock network
Control wires (e.g. set and reset signals)
Memories (driving many storage cells)
If CL is given:
VDD
- How many stages are needed to minimize the delay?
- How to size the inverters? Worst case:
Off chip signals
CL

20
 Inverter with Load (External only) Inverter with Internal Load

Delay Delay

Req

Cint Cext
Cext
Req
Load (Cext) External Load
tp = 0.69 Req Cext tp = 0.69 Req (Cint + Cext)

Internal (intrinsic) load is neglected Self-loading if Cint dominate

Not the case in modern technologies Should be avoided

Device Sizing (W scaled with S) Driving Large Capacitances

3.8
x 10
-11
Req Cint = Intrinsic capacitance
3.6 (for fixed load) External load Cext = Extrinsic capacitance
capacitances
3.4
dominate Req = Resistance in channel
3.2 Cint = Cdb+Cgd
Cext = Cw + Cg
t (sec)

Cw = Wire capacitance
p

2.8 Self-loading effect:

Intrinsic capacitances Req
2.6
dominate ((W is to VDD Cg = Gate C in next stage
2.4 wide compared to the
load) Req
2.2

2
2 4 6 8 10 12 14
S Req Cint Cext

21
Scaling to Increase Driving Capability Scaling to increase driving capability

Req
Scaling W with a factor S: Delay RC-model
Cext
t p = 0.69 Req (Cint + Cext ) = 0.69 Req Cint (1 + )
Cint = S × Ciref Cint
Cint = Cdb+Cgd
Scaling with a factor S
Rref
Req = t p = 0.69
Rref
S Ciref (1 +
Cext C
) = t p 0 (1 + ext )
Req S S S Ciref S Ciref
VDD

Req tp0 = intrinsic delay

Independent of S
Req Cint Cext

Scaling Example (page 206) Scaling Example (page 206)

t p 0 = 19.3 ps; Cext = 3.15 fF ; Ciref = 3.0 fF 1

t p = 19.3 × (1 + ) ps
C 1 1.05 × S
t p = t p0 (1 + ext ) = 19.3 (1 + ) ps
S Ciref 1.05 × S tp (ps) S =5, Substantial improvement
40

S >10, ”No more gain”

30

Ciref Cext 20

10

S
0
5 10 15

22
 Sizing a Chain of Inverters Sizing a Chain of Inverters
Cg , j +1
γ = Capacitive proportionality Cint, j f=
factor for each inverter
γ= Cg , j
Cg, j
- Technology Dependent f = The loading capacitive ratio
- Independent of the size (W)
The in- and in two following stages
output
- Close to 1 in Submicron capacitive ratio

1 2 N 1 2 N

Cg,1 Cint,1 Cg,2 Cint,2 Cg,N Cint,N Cg,N+1= CL Cg,1 Cint,1 Cg,2 Cint,2 Cg,N Cint,N Cg,N+1= CL

Sizing a Chain of Inverters Sizing a Chain of Inverters Known

Cg , j +1
Cint, j = γ Cg, j f= Cg ,2 Cg ,3 Cg , j Cg , j +1 CL
Cg , j f= = = = =
Cg ,1 Cg ,2 Cg , j −1 Cg , j Cg , N
Total Delay:
Cext , j C g , j +1 fj
t p , j = t p 0 (1 + ) = t p 0 (1 + ) = t p 0 (1 + ) N fj If each stage is scaled
Cint , j γ Cg , j γ t p = t p0 ∑ (1 + γ
j =1
)
with the same factor f

1 2 N 1 2 N

Cg,1 Cint,1 Cg,2 Cint,2 Cg,N Cint,N Cg,N+1= CL Cg,1 Cint,1 Cg,2 Cint,2 Cg,N Cint,N Cg,N+1= CL

23
Sizing a Chain of Inverters Sizing a Chain of Inverters
f =NF
Cg ,2 N fj N
F
f=
Cg ,1 C
f =N L =NF
t p = t p0 ∑ (1 +
j =1 γ
) = N × t p 0 (1 +
γ
)=

f2=
Cg ,3 Known Cg ,1
Cg ,1
Optimum is found by setting the derivative to 0
C
fN= L =F (F = overall effective fan- out) γ
Cg ,1 (1+ )
1 2 N f =e f

1 2 N

Cg,1 Cint,1 Cg,2 Cint,2 Cg,N Cint,N Cg,N+1= CL

Cg,1 Cint,1 Cg,2 Cint,2 Cg,N Cint,N Cg,N+1= CL

Sizing a Chain of Inverters Sizing a Chain of Inverters f=

Cg , j +1
Cg , j
γ Too many
(1+ ) Has no closed form Normalized delay
tp

f =e f
solution
so u o except
p for
o γ=00 6
t popt stages

γ=0 when intrinsic capacitance is neglected Common

4
Practice
f =e Otherwise: f is
solved numerically
Around 4

1 2 N
2
1
(1+ )
f for f = e f

Cg,1 Cint,1 Cg,2 Cint,2 Cg,N Cint,N Cg,N+1= CL

1 2 3 4 5

24
Buffer Design Inverter Chain

Common practice:
N f tp
1 64 1 64 65
Optimum fan-out around f=4
1 8 2 8 18
64

1 3 4 15 1 4 16
4 16 64
I
In O t
Out
1 64 4 2.8 15.3
CL
2.8 8 22.6

Digital IC-Design Dynamic Power Consumption

VDD Energy charged in a capacitor

CV2 C V2
Charge EC = = L DD
2 2

Power Consumption Energy EC is also discharged, i.e.

Etot = CL VDD
2

Discharge Power consumption

P = f CL VDD
2

25
Dynamic Power Consumption Current Spikes – Direct Path
Current peak
VDD Edp = VDD
I peak × tr
+ VDD
I peak × t f
=
tr × t f when both N-
Note: The power is VDD I peak
2 2 2 and PMOS are
dissipated in the transistor
Charge open
resistance, Req tr × t f
Pdp = VDD I peak f
2
However: the power VDD-VT
consumption is independent
of the value of Req VT
Discharge
P = CL VDD2 f Ipeak
N open
P open

Static Power Consumption Dynamic vs. Static Power

Ileakage increases The dynamic and static power is about

with decreasing VT equal in the 65 nm Technology
VDD
Pstat =Ileakage × VDD 100

Dynamic power

Normalized power
1

0 Drain leakage 65 nm

to bulk &
0.01

drain-source
0.0001
subthreshold Static power
current Year
0.0000001
1990 2000 2010 2020
Source: ITRS

26
Digital IC-Design Power-Delay Product

Helps to measure the quality

of different circuit topologies

Energy per switching event

Power Delay Product For static CMOS

tp CL × VDD
2
PDP = P × t p = CL × VDD
2
× f max × t p = CL × VDD
2
× = (J )

(PDP)
2t p 2

Independent of operating
frequency

Power-Delay Product Some Examples - Cascaded Inverters

Minimal Design Compensated to

Energy per switching event Decrease tpLH
CL × VDD
2
If we lower the supply, the
PDP = P × t p = PDP will be reduced, but also VDD
2 the performance
30 kΩ 15 kΩ

In Out
2 fF Out

Energy and performance

10 kΩ 10 kΩ
CL × VDD
2 Some claims that EDP is a
EDP = P × t p2 = ×tp better measure since it GND
2 includes the delay
1 fF + 2 fF 1 fF + 3 fF

Req − n = 10 k Ω; Req − p = 30 k Ω; Req − n = 10 k Ω; Req −Comp = 15 k Ω;

CMin = 4 fF CComp = 6 fF

27
Propagation Delay Power Consumption at Max Speed

Req − n = 10 k Ω; Req − p = 30 k Ω; Req − Comp = 15 k Ω; CMin = 4 fF ; CComp = 6 fF ; VDD = 2 V

CMin = 4 fF ; CComp = 6 fF ; VDD = 2 V
Not much faster but 1 1 Compensating
f Max − Min = = 9.1 f Max − Comp = = 99.7
more symmetric gives higher
9 1 GHz
GH ; 7 GH
GHz
2t p 2t p
t pHL − Min = 0.69 × CMin × Req − n = 28 ps
t pHL − Min + t pLH − Min
PMin = CMin × VDD × f Max − Min = CL × VDD ×
1
= 140 μW
power
t pLH − Min = 0.69 × CMin × Req − p = 83 ps t p − Min = = 55 ps
2 2

2 2t p − Min consumption
t pHL − Comp = 0.69 × CComp × Req − n = 41 ps t pHL −Comp + t pLH −Comp 1
PComp = CComp × VDD × f Max − Comp = CL × VDD × = 230 μW
t pLH − Comp = 0.69 × CComp × Req − Comp = 62 ps t p −Comp = = 52 ps
2 2

2 2t p − Comp

VDD VDD

In Out In Out In Out In Out

GND GND

Power-Delay Product Total Power Consumption and PDP

tp CL × VDD
2
PDP = P × t p = CL × VDD
2
× f max × t p = CL × VDD
2
× = (J )
2t p 2 Ptot = Pdyn + Pdp + Pstat =
CMin × VDD
2
Compensating
PDPMin = = 8 fJ
gives higher
2
CComp × VDD energy per
tr + t f
= CLVDD + +
2
2
PDPComp = = 12 fJ f VDD I peak f I leakageVDD
2 switching event 2
VDD

CL × VDD
2
PDP = P × t p = (J )
In Out In Out
2

GND

28