Solid-State Electronics 97 (2014) 66–75

Contents lists available at ScienceDirect

Solid-State Electronics
journal homepage: www.elsevier.com/locate/sse

Characteristics of GaN and AlGaN/GaN FinFETs

Ki-Sik Im a, Hee-Sung Kang a, Jae-Hoon Lee b, Sung-Jae Chang c, Sorin Cristoloveanu c, Maryline Bawedin d,
Jung-Hee Lee a,⇑
a
School of Electronics Engineering, Kyungpook National University, Daegu, Republic of Korea
b
Discrete Development Team, System LSI, Samsung Electronics Co., Ltd., Giheung, Republic of Korea
c
IMEP-LAHC, Grenoble Institute of Technology, Minatec, BP 257, 38016 Grenoble Cedex 1, France
d
IES, University of Montpellier II, 34095 Montpellier, France

a r t i c l e i n f o a b s t r a c t

Article history: AlGaN/GaN FinFETs, with high quality atomic layer deposited (ALD) Al2O3 gate dielectric, have been fab-
Available online 6 May 2014 ricated. The devices have a two-dimensional electron gas (2DEG) channel formed at AlGaN/GaN hetero-
interface and two sidewall GaN MOS channels. Two distinct transconductance peaks can be observed, one
The review of this paper was arranged by
for the 2DEG channel and the other for the sidewall GaN MOS channels. On the other hand, we present
Prof. S. Cristoloveanu
heterojunction-free GaN FinFETs with junctionless configuration. The current flows through the volume
of the heavily doped GaN fin rather than at the surface channel, which leads to superior off-state perfor-
Keywords:
mance and less drain-induced virtual substrate biasing (DIVSB) effect.
AlGaN/GaN
MOSFET
Ó 2014 Elsevier Ltd. All rights reserved.
Normally-off
FinFET
Junctionless
Nanochannel

1. Introduction 3-dimensional (3-D) configuration which improves the gate control

Superior material parameters of GaN, such as wide band-gap,
high breakdown electric field, and high electron velocity compared
to other materials (Si, SiC, GaAs, etc.), make the AlGaN/GaN hetero-
junction field-effect-transistor (HFET) exhibit potential advantages
for high voltage and high frequency applications [1]. However, it is
difficult to achieve normally-off operation (mandatory for power
switching), due to the inherent presence of polarization-induced
two-dimensional electron gas (2DEG) at AlGaN/GaN heterointer-
face. The large 2DEG density is nevertheless essential for greatly
reducing the on-resistance of the device [2].
It was reported that normally-off operation can be envisaged by
using recessed-gate [3,4], p-GaN gate [5], tunnel-junction structure
[6], or GaN MOSFET [7]. A more pragmatic solution is to adopt
narrow FinFET configuration, where the activation of the 2DEG
channel can be controlled by the lateral gates.
In recently fabricated nanochannel FinFETs with AlGaN/GaN
heterostructure [8–11], the threshold voltage (Vth) shifts to positive
direction by reducing the fin width. In addition to normally-off
capability, these AlGaN/GaN FinFETs demonstrated excellent
performance [8–11]. The main reason for high performance is the
⇑ Corresponding author. Tel.: +82 53 950 6555; fax: +82 53 950 7489.
E-mail address: jlee@ee.knu.ac.kr (J.-H. Lee).
of the channel in nanosize devices, as already highlighted for Si
FinFETs [12–15]. For example, Zimmermann et al. [8] and Lu et al.
[9] showed that very low subthreshold slope (SS) and high
maximum drain current (Id,max) can be obtained from AlGaN/GaN
nano-devices.
Another device attracting interest is the junctionless transistor
first demonstrated on ultrathin SOI [16]. It features reduced
short-channel effects and simpler technology.
In this paper, we report on the fabrication and characterization
of AlGaN/GaN FinFETs and heavily doped junctionless GaN FinFETs.
These devices have high-quality atomic layer deposition (ALD)
Al2O3 layer as gate dielectric [11,17]. When the fin width becomes
sufficiently small, both devices successfully demonstrate normally-
off operation (with positive Vth) and high on-state performance
[18]. We complement these results by comparing the experimental
characteristics with 3D simulations and focusing on the saturation
region of operation.
2. Growth and device fabrication
AlGaN/GaN heterostructure investigated in this work consists of
(i) low-temperature-grown initial GaN buffer layer, (ii) 2 lm-thick
highly resistive GaN layer, (iii) 80 nm-thick GaN channel layer, and
(iv) 30 nm-thick Al0.3Ga0.7N barrier layer. This growth sequence

http://dx.doi.org/10.1016/j.sse.2014.04.033
0038-1101/Ó 2014 Elsevier Ltd. All rights reserved.
 K.-S. Im et al. / Solid-State Electronics 97 (2014) 66–75
was performed on sapphire substrate by metal–organic chemical
vapor deposition (MOCVD). The measured Hall data for the hetero-
structure showed that the 2DEG density and electron mobility
were 8.8  1012 cm 2 and 1500 cm2 V 1 s 1, respectively.
The epitaxial growth of GaN layer for the heterojunction-free
GaN FinFET is rather simple due to the absence of the AlGaN barrier
layer. It consists of 120-nm-thick Si-doped n-type GaN layer grown
on 2 lm-thick highly resistive undoped GaN/sapphire template by
MOCVD. The GaN layer is heavily doped with Si in order to ensure
ohmic source/drain contacts and low series resistances of this
device which operates as a junctionless transistor. Hall effect
measurements indicated reasonable values for the electron
concentration (4  1018 cm 3) and mobility (234 cm2 V 1 s 1) in
the Si-doped GaN layer.
The active region of the devices was patterned by Raith150
electron-beam lithography (EBL) system (using hydrogen sils-
esquioxane (HSQ) as a negative e-beam resist) and defined by
transformer-coupled plasma-reactive ion etching (TCP-RIE) using
a BCl3/Cl2 gas mixture. The 3-D nanochannel structure was shaped
by optimizing the energy and dose of EBL and the etching condition
for the epitaxial layer. Tetramethylammonium hydroxide (TMAH)
treatment (in 25% solution at 85 °C) was directly followed to smooth
the etched side-wall GaN surfaces and also to remove the plasma
damage from the etched surface [4]. A 20 nm-thick Al2O3 gate insu-
lator layer was then deposited by ALD. After contact hole opening
for the source and drain (S/D), Ti/Al/Ni/Au was deposited using an
electron-beam evaporator, followed by rapid thermal annealing at
900 °C for 30 s in nitrogen ambient. Finally, Ni/Au (30/200 nm) gate
metal stack was deposited by using a lift-off process.
3. AlGaN/GaN FinFETs: characteristics and discussion
The schematic configuration of the proposed AlGaN/GaN FinFET
is shown in Fig. 1a. The device consists of a 2DEG channel formed
(a)
Gate
Source
Lg
HR-GaN / Sapphire
(b) gate electrode
Top channel
AlGaN
2DEG
GaN
Al2 O3
Side-wall
channels
Fig. 1. (a) Schematic illustration of the proposed AlGaN/GaN FinFET including device dimensions and layer structure. (b) Cross-section of the channel region showing one top
2DEG channel and two side-wall GaN MOSFET channels and (c) cross-sectional TEM image of the AlGaN/GaN FinFET.
67
at AlGaN/GaN heterointerface near the top of the fin and two side-
wall MOSFET channels on the etched GaN surface, as shown in
Fig. 1b. The channels in the AlGaN section of the fin have much
higher threshold voltage and are hardly activated under normal
bias conditions. The cross-sectional transmission electron micros-
copy (TEM) image is reproduced in Fig. 1c. The nanochannel struc-
ture is entirely covered by 20 nm-thick Al2O3 gate insulator layer
prior to the deposition of Ni/Au gate metal layer. The fin height
is Hfin = 120 nm and the fin widths (Wfin) vary from 60 to 140 nm.
Fig. 2 shows typical characteristics of FinFET with Wfin = 140 nm.
The device exhibits Id,max of 0.45 mA (Fig. 2a) and maximum gm of
0.18 mS (Fig. 2d) at Vgs = 6 V and Vds = 7 V. The corresponding dc
performances, normalized by the total gate width (sum of width
and two heights of the nanowire Wtot = 140 nm + 2  120 nm), are
1.18 A/mm and 470 mS/mm, respectively. Pragmatic normalization
by the top gate width (140 nm which corresponds to the real-estate
on the wafer surface) yields even better results: 3.2 A/mm and
1275 mS/mm.
The on-resistance of the FinFET is 0.1 mX cm2 in the linear
region, a much lower value than previously reported for other
types of devices [3,7,10,19]. These superior characteristics result
essentially from the triple-gate structure which improves the
gate control on the channel [8–11]. The subthrehold swing is
S = 142 mV/decade at Vds = 0.1 V. The slightly larger S value
compared to previous reports [9,20] (Fig. 2b) may originate from
the inadequate resistivity of the undoped GaN buffer layer and
imperfect Al2O3 interface. The subthreshold characteristics can be
improved by optimizing the growth condition to increase the
resistivity of the buffer layer and the dielectric quality.
The transfer curves in Fig. 2b–d clearly exhibit two distinct gm
peaks, especially in the linear region of operation at low drain
voltage. For negative gate voltage (Vgs  4 V), the first gm peak
indicates that only the top 2DEG channel is conducting as shown
in Figs. 1b and 2b. The drain current increases slowly (and the gm
Gate oxide
Al2 O3 : 20 nm
Drain
AlGaN (30 nm)
GaN (80 nm)
(c)
140 nm
120 nm
Al2O3
GaN (20 nm)
68 K.-S. Im et al. / Solid-State Electronics 97 (2014) 66–75

(a) 0.5 Vgs = 6 V ~ -5 V, ΔV = 1 V

0.04 Vgs = 2 V
0.4 0.03 Vgs = 1 V

Ids [mA]
Ids [mA] Vgs = 0 ~ -3 V
0.3 0.02

0.2 0.01 Vgs = -4 V

Vgs = -5 V
0.00
0.1 0 2 4 6 8 10
Vds [V]
0.0
0 2 4 6 8 10
Vds [V]
(b) 0.010 0.0025
Vds = 0.1 V
0.008 0.0020
1.0 0.3
Ids μA

0.8
Ids [mA]

gm μ S

gm [mS]
0.006 0.6 0.2 0.0015 -2
0.4 10

Log Ids [mA]

0.1
0.2 Vth = -4.5 V
0.004 0.0 0.0 0.0010 10
-3
-4 -2 0
Vgs [V] -4
0.002 0.0005 10
Vth = 2 V -5
Vds = 0.1 V
0.000 0.0000 10
-4 -2 0 2 4 6
-4 -2 0 2 4 6
Vgs [V] Vgs [V]

(c) 0.5 0.18

Vds = 3 V
0.4 0.15
25 8
Ids μA

20 6
gm μ S

0.12
Ids [mA]

15 4
0.3
gm [mS]

10 0
10
Log Ids [mA]

5 2 0.09
Vth = - 4.3 V -1
0.2 0 0 10
-5 -4 -3 -2 -1 0 -2
0.06 10
Vgs [V] -3
0.1 10
0.03 10
-4
Vth = 3 V -5
Vds = 3 V
0.0 0.00 10
-4 -2 0 2 4 6
-4 -2 0 2 4 6 Vgs [V]
Vgs [V]
(d) 0.5 0.18
Vds = 7 V
0.4 0.15
25 8
20 6 0.12
Ids [mA]

Ids μA

gm μS

15
gm [mS]

0.3 4
10 0
5 2 0.09 10-1
Log Ids [mA]

Vth = - 4.0 V 10-2

0.2 0 0
-5 -4 -3 -2 -1 0 0.06 10-3
10-4
0.1 Vgs [V] 10-5
0.03 10-6
Vth = 3.8 V
10-7 Vds = 7 V
0.0 0.00 10
-4 -2 0 2 4 6 -4 -2 0 24 6
Vgs [V]
Vgs [V]
Fig. 2. (a) Ids–Vds characteristics of the fabricated AlGaN/GaN FinFET. The inset shows the Ids–Vds curves at lower Vgs (from 5 to +2 V) which exhibit typical normally-on
HEMT operation. Figures (b)–(d) are transfer curves at Vds = 0.1 V, 3 V, and 7 V, respectively. The insets in figures (b)–(d) show magnified Ids–Vgs and transconductance
characteristics at negative Vgs (dominated by the 2DEG channel) and subthreshold drain current curves in logarithm scale. Lg = 1 lm, Wfin = 140 nm.
 K.-S. Im et al. / Solid-State Electronics 97 (2014) 66–75 69

Fig. 3. 3D simulation of AlGaN/GaN FinFET with 140 nm fin width. The 2D sketches correspond to the electron density in the middle of the fin plotted at four consecutive
front-gate voltages Vgs (see also Fig. 2). (a) Activation of the AlGaN/GaN 2DEG channel at Vgs = 5 V, (b) 2DEG saturation in the range 2 V < Vgs < 1 V, (c) onset of the lateral
channels at Al2O3/GaN interface for Vgs > 1 V, and (d) activation of the top Al2O3/AlGaN interface channels at Vgs > 4.5 V. The geometrical dimensions are all related to the
fabricated devices except the 100 nm channel length. The applied drain voltage is 0.1 V and the gate workfunction is 5.2 eV. The highly resistive-GaN layer is 1015 cm 3
n-doped. A positive fixed charge of 1011 cm 2 is assumed at the top and lateral Al2O3 gates.

drops, Fig. 2b) with gate voltage until Vgs  +2 V, which is typical
Table 1
for normally-on HEMT operation. Further increasing the gate volt- Characteristics of the AlGaN/GaN FinFET extracted from the results shown in Fig. 2.
age gives rise to a second gm peak, when the two sidewall GaN
Vds First Vth Second Vth Ratio of (second gm peak)/(first gm peak)
MOSFET channels start to conduct as well. The rapid increase in
current with gate voltage is representative for normally-off MOS- 0.1 V 4.5 V 2.0 V 11
3.0 V 4.3 V 3.0 V 21
FET operation. By defining the threshold voltage Vth as the gate-
7.0 V 4.0 V 3.8 V 34
bias intercept of the extrapolated drain current at the gm peaks,
the first (2DEG) and the second (lateral channel) threshold voltages
are determined to be about 4.5 and 2 V at Vds = 0.1 V.
The double conduction mechanism (sidewall channels and
0
2DEG) featured in Fig. 2b is confirmed by 3D numerical simulations 10
-1
with Synopsys TCAD tools [21]. Fig. 3 highlights the activation of 10
-2
the different channels in the AlGaN/GaN FinFET as a function of 10
increasing gate voltage values. Four distinct regions can be dis- -3
Log Ids [mA]

10
criminated and correspond to (a) the activation of the AlGaN/ -4
GaN 2DEG leading to the transconductance increase at Vgs = 5 V, 10 Wfin = 140 nm
-5
(b) the 2DEG pinning reflected by the transconductance drop 10 Vds =
-6
( 2 V < Vgs < 1 V), (c) the formation of the lateral channels at 10
-7 7.0 V
Al2O3/GaN interface, and eventually (d) the onset of the top
10 3.0 V
Al2O3/AlGaN channels. The simulations have also shown that the -8
10 0.1 V
threshold voltages of the 2DEG and lateral channels strongly -9
depend on the density of surface defects and oxide charges in the 10
-9 -6 -3 0 3 6
GaN and AlGaN regions of the fin. In particular cases, top and lat- Vgs [V]
eral channels can be activated firstly in the AlGaN regions (before
the GaN region). For example, a large positive oxide charge Fig. 4. Logarithmic scale of drain current as a function of gate voltage in the
(1013 cm 2) in the AlGaN section makes (i) the 2DEG to open fabricated AlGaN/GaN FinFET with gate length of 0.15 lm at Vds = 0.1, 3, 7 V.
70 K.-S. Im et al. / Solid-State Electronics 97 (2014) 66–75

0.05
Vgs = 6 ~ -10 V, Δ V = 1 V
0.04

Ids [mA]
0.03

0.02

0.01

0.00
0 2 4 6 8 10
Vds [V]
(a)
0.003 0.0005
Vds = 0.1 V
0.0004
0.002
Ids [mA]

gm [mS]
0.0003 -2

Log Ids [mA]

10-3
10-4
0.0002 10-5
0.001
10-6
0.0001 10-7
10-8
10-9 Vds = 0.1 V
0.000 0.0000 10
-4 -2 0 2 4 6 -4 -2 0 2 4 6
Vgs [V] Vgs [V]
(b)
0.035 0.015
Vds = 3 V
0.028 0.012
Ids [mA]

gm [mS]

0.021 0.009 -1
10-2
Log Ids [mA]

10-3 Vds = 3 V
0.014 0.006 10-4
10-5
0.007 0.003 10-6
10-7
10-8
0.000 0.000 10
-4 -2 0 2 4 6 -4 -2 0 2 4 6
Vgs [V]
Vgs [V]
(c)
0.04 0.020
Vds = 7 V
0.03 0.015
Ids [mA]

gm [mS]

-1
10 -2
Log Ids [mA]

0.02 0.010 10 -3 Vds = 7 V

10 -4
10 -5
0.01 0.005 10 -6
10 -7
10 -8
0.00 0.000 10
-4 -2 0 2 4 6
-4 -2 0 2 4 6
Vgs [V]
Vgs [V]
(d)
Fig. 5. (a) Experimental Ids–Vds characteristics of a narrower AlGaN/GaN FinFET (Lg = 1 lm, Wfin = 80 nm). Figures (b)–(d) are transfer curves at variable Vds. The insets show
the subthreshold curves.
 K.-S. Im et al. / Solid-State Electronics 97 (2014) 66–75 71

Gate oxide gate electrode

(a) Gate Al2 O3 : 20 nm (b)
GaN bulk
Source Drain channel

Si-doped GaN
(120 nm)
Lg Si-doped
GaN
HR-GaN / Sapphire
Al2 O3
(c) (d)
Gate metal Gate oxide
Gate oxide GaN GaN
Ni/Au Al2 O3
Al2 O3

Vbi
Vbi b
EC EC
EF EF

EV EV

W W

Fig. 6. (a) Illustration of the heterojunction-free GaN FinFET including dimensions and layer structure. (b) Schematic cross-section of the channel region showing the GaN
bulk channel. Corresponding energy band diagram (c) in the ungated region and (d) in the gated region.

earlier (at more negative Vgs) and (ii) the Al2O3/AlGaN channels to
be activated before the GaN sidewalls.
It is noticed from Fig. 2b–d that the lateral gate Vth increases
rapidly with drain voltage, whereas the increase in the 2DEG Vth
is rather slow. This effect is hardly observed in conventional
short-channel Si MOSFETs or AlGaN/GaN HFET [22], where the
Vth normally decreases as the drain voltage increases due to
short-channel effects (SCE) such as drain-induced barrier lowering
(DIBL). The increase in Vth with drain voltage for the device of
Lg = 1 lm is presumably due to the penetration of the fringing field
from drain through the semi-insulating GaN substrate, which is
similar to the back gating phenomena frequently observed in
MOSFETs fabricated on silicon-on-insulator (SOI) substrate [23–25].
This is the first observation of the drain-induced virtual substrate
biasing (DIVSB) in GaN-based FETs to the best of our knowledge.
When a large positive drain voltage is applied, the fringing electric
field from drain into the insulating substrate attracts electrons
from the sidewall GaN channels. The trapped electrons decrease
the density of the channel electrons to satisfy the charge neutrality.
Therefore, a more positive gate voltage must be applied to reach
the threshold electron concentration in the channel. It is also noted
that the ratio of (second gm peak)/(first gm peak) increases as drain
voltage increases. The remote top 2DEG channel is less affected by
the fringing field. The drain voltage dependent Vth and ratio
between the gm peaks are summarized in Table 1. While the cause
for DIVSB (field penetration) is similar in SOI and GaN FinFETs, the
consequences are different. In SOI MOSFETs, the fringing field
increases the potential at the interface between film and buried
oxide, lowering Vth and thus adding to the DIBL effect. In our
FinFETs, the DIVSB is assisted by electron trapping which tends
to increase Vth and oppose DIBL. As a matter of fact, the DIVSB is
hardly observed in devices with relatively short gate length
(Lg = 0.15 lm) where DIBL dominates. The Vth rather shifts to
smaller value by increasing the drain voltage (Fig. 4), which is
the typical signature of DIBL.
On the other hand, Fig. 5 shows that the device with Wfin of
80 nm exhibits only one gm peak and normally-off operation with
Vth = 1.7 V. Indeed, in very narrow fins (Wfin < 100 nm), the fringing
field between the sidewall gates can deplete the 2DEG channel
[8–11] and hence only two lateral MOS channels subsist. However,
the MOS channels have much lower current drive capability than
the 2DEG channel. Narrow FinFETs have the advantage of obtaining
normally-off operation at the expense of a decrease in drain cur-
rent due to the attenuated (or suppressed) contribution of the
2DEG channel. We conclude that the lateral gates act as normal
MOS gates for the sidewall channels and as JFET gates for the
2DEG channel.
Fig. 5a shows a current of 0.044 mA (measured Vgs = 6 V and
Vds = 10 V) which is one order of magnitude lower than in the
wider FinFET (Wfin = 140 nm, Fig. 2). The narrow FinFET also exhib-
its considerably higher subthreshold swing (416 mV/dec, Fig. 5b)
because a small amount of off-state current may still flow through
the subsisting part of the 2DEG channel (near the center of the fin),
where the fringing field cannot penetrate to completely deplete the
whole channel.
4. Heterojunction-free GaN FinFETs: characteristics and
discussion
In order to overcome the problems encountered in AlGaN/GaN
FinFETs, heterojunction-free GaN FinFETs have been fabricated.
The main processes for both devices are exactly identical, as
described in Section 2. The source and drain have not received
72 K.-S. Im et al. / Solid-State Electronics 97 (2014) 66–75

0.8
Vgs = 6 ~ -10 V, ΔV = 1 V
0.6

Ids [mA]
0.4

0.2

0.0
0 2 4 6 8 10
Vds [V]
(a)
0.012 0.0015

0.008 0.0010
Ids [mA]

gm [mS]
-1
10-2

Log Ids [mA]

10-3
10-4
10-5
0.004 0.0005 10-6
10-7
10-8
10-9
Vds = 0.1 V 10
0.000 10-10 Vds = 0.1 V
0.0000 10-11
-9 -6 -3 0 3 6 -9 -6 -3 0 3 6
Vgs [V] Vgs [V]
(b)
0.30 0.04
0.25 Vds = 3 V
0.03
Ids [mA]

0.20
gm [mS]

0.15 0.02 10 0
Log Ids [mA]

10 -1-2
0.10 10 -3
10 -4
0.01 10 -5
0.05 10 -6
10 -7
10 -8
0.00 0.00 10 -9 Vds = 3 V
-9 -6 -3 0 3 6 10
10 -10
-9 -6 -3 0 3 6
Vgs [V]
Vgs [V]
(c)
0.8 0.04
Vds = 7 V
0.6 0.03
gm [mS]
Ids [mA]

100
0.4 0.02 10-1
Log Ids [mA]

10-2
10-3
10-4
0.2 0.01 10-5
10-6
10-7
10-8
10-9 Vds = 7 V
0.0 0.00 10-10
-9 -6 -3 0 3 6 -9 -6 -3 0 3 6
Vgs [V] Vgs [V]
(d)
Fig. 7. (a) Experimental Ids–Vds characteristics of heterojunction-free GaN FinFET. Figures (b)–(d) are transfer curves at variable drain bias. The insets show the corresponding
subthreshold characteristics. Lg = 1 lm, Wfin = 100 nm, 5 parallel fins.
 K.-S. Im et al. / Solid-State Electronics 97 (2014) 66–75
Fig. 8. 3D simulation of a GaN FinFET with 100 nm fin width. The 2D cuts are taken at three different front gate voltages showing (a) the onset of volume conduction, (b) the
activated volume channel and (c) the electron accumulation at the Al2O3/GaN interface. The geometrical dimensions are all related to the fabricated devices except the
100 nm channel length (Fig. 6). The highly resistive-GaN layer is 1015 cm 3 n-doped. A workfunction of 5.2 eV and a positive fixed charge density 1011 cm 2 were assigned to
the top Al2O3 gate. Vds = 0.1 V.
additional doping. The schematic configuration of the proposed
junctionless transistor is shown in Fig. 6a. The fin height was
120 nm and the fin width varied from 60 to 100 nm. In order to
increase the drive current, 5 fins were connected in parallel.
Fig. 6c and d represent the band diagrams for the ungated and
gated regions of the device, showing that both regions can be more
or less depleted according to the surface potential. The potential
barrier in the gated region is higher due to the large work function
difference between the gate metal and GaN layer. This means that
the gated region of a sufficiently narrow fin can be fully depleted,
whereas a neutral channel subsists in the ungated extension
region. The surface depletion width is approximately 25 nm for
the gated region and 15 nm for the ungated region, respectively.
As a result, it is expected that a multiple-gate device with
Wfin = 50 nm will exhibit normally-off operation because the gated
region is fully depleted even at Vgs = 0 V.
Our GaN FinFET is similar with Si junctionless transistors in
view of concept and conduction mechanism of [16,26–28]. The
current flows through the volume of the heavily doped GaN fin
(Fig. 6b) rather than at the surface channel of the AlGaN/GaN
FinFET (Fig. 1b).
Despite the heavy doping, the device exhibits excellent
pinch-off and I–V characteristics (Fig. 7). The Id,max for the hetero-
junction-free GaN FinFET with Wfin of 100 nm is 0.67 mA at
Vgs = 6 V and Vds = 10 V and the output conductance in saturation
region is very low, as shown in Fig. 7a. The normalized Id,max,
divided by the total gate width (sum of width and two heights of
the nanowire multiplied by the number of fins, Wfin = (100 nm +
2  120 nm)  5)) is 650 mA/mm. Normalization by the top gate
width (100 nm) yields more than 2 A/mm. These values are far
higher than those of state-of-the-art planar AlGaN/GaN-based
MISHFETs [5,6,29,30] and MISFETs [3,4,31–33]. The on-resistance
of the GaN FinFET is as low as 3.2 mX cm2, due to (i) enhanced
triple-gate electrostatic control [8–11] and (ii) high n-type doping
which greatly decreases the series resistance.
The transfer curves for this relatively large FinFET indicate
normally-on operation (Fig. 7b–d). Since Wfin is wide (100 nm)
and the doping level high, a large negative gate bias is needed to
fully deplete the GaN channel.
In Fig. 7, the transconductance shows a broad maximum
explained with insight from 3D simulations. The first peak
73
(Fig. 7b, Vgs = 5 V) reflects the opening of the volume channel
when the neutral region starts forming in the bottom and middle
of the fin (Fig. 8a). The channel gradually expands in the whole
body (Fig. 8b). Then, a second peak (Fig. 7b, Vgs = + 3 V) appears
when the surface accumulation channel is buildup (Fig. 8c) provid-
ing extra current.
Fig. 9 shows the characteristics of a narrower GaN junctionless
FinFET. The potential barrier caused by the work function difference
between the gate metal and the GaN layer can easily deplete the
gated region of the GaN bulk channel, especially when the drain
voltage is high, which results in normally-off operation with posi-
tive Vth. This narrow device still offers high on-state current Id,max
of 1 mA (670 mA/mm or 3.4 A/mm according to the type of normal-
ization) at Vgs = 6 V and Vds = 10 V (Fig. 9a). This performance is
comparable or higher than in the wider FinFET (Fig. 7a), implying
that the saturation current is weakly dependent on the fin width.
In contrast, the saturation current in AlGaN/GaN FinFETs is domi-
nated by the 2DEG density which is proportional to the fin width.
The heterojunction-free GaN FinFETs investigated in this work
exhibit remarkable subthreshold behavior: very high ION/IOFF ratio
of 108–109 and extremely low off-state leakage current of 10 10–
10 11 mA, measured at Vds = 0.1 V (Figs. 7b and 9b). The subthresh-
old swing measured in the 60 nm wide FinFET is only 68 mV/dec
(Fig. 9b), the lowest value ever reported for GaN MISFETs
[3,4,27–29]. The swing is very close to the theoretical limit of
60 mV/dec at 300 K achieved in state-of-the art FinFETs and junc-
tionless MOSFETs on SOI. These excellent off-state characteristics
with very high ION/IOFF ratio result from the current flow through
the nanochannel volume rather than at the surface channel, being
less affected by the traps at the Al2O3/GaN interface.
The threshold voltage of the heterojunction-free GaN FinFET
with Lg = 1 lm shifts to positive value as the drain voltage
increases (Fig. 10a). Again, this is the consequence of the competi-
tion between DIVSB and DIBL effects, as described for AlGaN/GaN
FinFETs. The drain voltage dependent Vth is summarized in Table 2.
The Vth shift with drain bias is smaller in GaN than that in AlGaN/
GaN FinFET (Tables 1 and 2) due to the current flow through the
bulk of the fin rather than at the surface. Fig. 10b shows the trans-
fer curves for a short device with Lg = 0.15 lm. We now observe a
slightly negative shift in Vth with increasing Vds, which is typical
when DIBL prevails.
74 K.-S. Im et al. / Solid-State Electronics 97 (2014) 66–75

1.2
Vgs = 6 ~ -10 V,ΔV = 1 V
1.0
0.8

Ids [mA]
0.6
0.4
0.2
0.0
0 2 4 6 8 10
Vds [V]
(a)
0.03 0.005
Vds = 0.1 V
0.004
0.02
Ids [mA]

gm [mS]
0.003 10 -1
10 -2 Vds = 0.1 V

Log Ids [mA]

10 -3
0.002 10 -4
0.01 10 -5
10 -6
0.001 10 -7
10 -8
10 -9
0.00 0.000 10 -10
10 -11
-9 -6 -3 0 3 6 -9 -6 -3 0 3 6
Vgs [V] Vgs [V]
(b)
0.8 0.15
Vds = 3 V
0.6
Ids [mA]

0.10
gm [mS]

1
100
0.4 10-1 Vds = 3 V
Log Ids [mA]

10-2
10-3
0.05 10-4
0.2 10-5
10-6
10-7
0.0 0.00 10-8
10-9
-9 -6 -3 0 3 6 10
-9 -6 -3 0 3 6
Vgs [V]
(c) Vgs [V]
1.2 0.25
Vds = 7 V
0.20
0.9
Ids [mA]

g [mS]

0.15 1
0.6 10 0
10-1 Vds = 7 V
Log Ids [mA]
m

0.10 10 -2
10 -3
0.3 10 -4
0.05 10 -5
10 -6
10 -7
0.0 0.00 10 -8
10 -9
-9 -6 -3 0 3 6 10
-9 -6 -3 0 3 6
Vgs [V]
Vgs [V]
(d)
Fig. 9. (a) Ids–Vds characteristics of a narrow GaN junctionless FinFET. Figures (b)–(d) are transfer curves (drain current and transconductance) at Vds = 0.1 V, 3 V, and 7 V,
respectively. The insets in figures (b)–(d) show the subthreshold characteristics. Lg = 1 lm, Wfin = 60 nm, 5 parallel fins.
 K.-S. Im et al. / Solid-State Electronics 97 (2014) 66–75 75

100 (109). Both devices experience DIBL when the gate length is short
10-1 and DIVSB for longer gate. The heterojunction-free GaN FinFETs
10
-2 are less affected by interface defects because the current flows
through the bulk of the fin rather than at the surface. The two types
Log Ids [mA]

-3
10 Wfin = 60 nm, 5-fin,
10
-4 of FinFETs show promising potential for a variety of applications.
10-5 L g = 1 μm,
10-6 Acknowledgments
Vds =
-7
10
10
-8 7.0 V This work was supported by Kyungpook National University
10
-9
3.0 V Research Fund 2012, the BK21 Plus funded by the Ministry of
10-10 Education, the National Research Foundation of Korea grants funded
0.1 V
10-11 by MSIP (2008-0062617, 2011-0016222, 2013R1A6A3A04057719),
-4 -2 0 2 4 6 R&D program of MKE/KETEP (2011101050017B), and IT R&D
Vgs [V] program of MKE/KEIT (10038766).
(a)
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