Characterization of Traps and Trap-Related Effects in Recessed-Gate

Normally-off AlGaN/GaN-based MOSHEMT

Jong-Ho Bae, Injun Hwang1, Jong-Min Shin, Hyuck-In Kwon2, Chan Hyeong Park3, Jongbong Ha1, JaeWon Lee1,
Hyoji Choi1, Jongseob Kim1, Jong-Bong Park1, Jaejoon Oh1, Jaikwang Shin1, U-In Chung1, and Jong-Ho Lee
School of EECS and ISRC, Seoul National University, Seoul 151-742, Korea,
1
Samsung Advanced Institute of Technology, Samsung Electronics Co., Ltd, San 14, Nongseo-dong, Giheung-gu, Yongin-si, Gyeonggi-do, 446-712, Korea,
2
School of EEE, Chung-Ang University, Seoul 156-756, Korea, 3Dept. of ECE, Kwangwoon University, Seoul 139-701, Korea
Phone: +82-2-880-1727; Fax: +82-2-882-4658; E-mail: jhl@snu.ac.kr

Abstract
Traps and trap-related effects in recessed-gate normally-off
AlGaN/GaN-based MOSHEMT with SiO2 gate dielectric were
characterized. Hysteresis in ID-VG was observed at elevated
temperature (~120 oC) due to the traps. To understand the traps,
current transient in drain was investigated at given gate and
drain pulses with different temperatures. Two groups of time
constants were extracted: one is nearly constant and the other is
decreased with temperature. Extracted activation energies
from the drain current transients with temperature are 0.66 eV
and 0.73 eV, respectively, for given gate and drain pulses.
Using extracted exponential trap density profile from
frequency dependent conductance method [4], we could
understand C-V behavior with frequency. It was shown that
traps inside AlGaN layer are a main cause for the decrease of
capacitance at high frequency in inversion region. The pulsed
I-V characteristics also show frequency dependence.
etching the capping layer and AlGaN layer, and forming the 20
nm-thick SiO2 layer using the ALD method as shown in Fig. 2
(b). As expected, a lot of threading dislocations due to lattice
mismatch between Si substrate and GaN material are observed
in a TEM image (Fig. 2(c)). Fig. 3 shows the transfer and
output curves of the fabricated device having a channel width
of 100 μm, which well demonstrates a normally-off operation
with a turn-on voltage (Von) of 1 V. This device has a very
small gate leakage current of around 10 pA. The on-current
reaches up to 0.12 A/mm at given VGS of 4.5 V and VDS of 6 V.
Fig. 4 compares the drain current (ID) hysteresis of fabricated
recessed-gate AlGaN/GaN MOSHFETs at different
temperatures (27 and 120 oC). From the figure, the hysteresis is
observed clearly at a high temperature (120 oC), which
demonstrates the existence of the traps. The ID at 120 oC for a
given gate bias (VG) is smaller than that at 27 oC due to the
electron mobility decreased by phonon scattering.

Introduction Results and Discussion

The AlGaN/GaN high electron mobility transistor (HEMT)
is one of the strong candidates for next-generation power and
microwave devices [1]. Recently, the metal-oxide-semi
conductor heterostructure field-effect transistor (MOSHFET)
using the recessed-gate was proposed to reduce the gate current
and realize the normally-off characteristics [2]. However,
problems of dispersion effects and instabilities due to the
presence of traps still prevent the wide usage of this new
device. Previously, various methods have been used to study
the electrical traps in AlGaN/GaN HEMTs. However,
relatively few studies have been made about the traps and
trap-related effects in AlGaN/GaN MOSHFETs with a
recessed-gate. In this paper, we investigate the traps and
trap-related effects in recessed-gate AlGaN/GaN MOSHFETs
using various characterization methods including the current
transient spectroscopy, frequency dependent conductance
method, C-V, and pulsed I-V [3], [4].
Device Fabrication and DC I-V
Figs. 1 and 2 depict schematic cross sectional view and cross
sectional TEM images of the fabricated AlGaN/GaN
MOSHFETs with a recessed-gate, respectively. The devices
were fabricated at Samsung. The structure from the top of the
epi-layers has a 3 nm GaN capping layer, a 30 nm AlGaN, a 3
μm GaN, and buffer layers grown on 8-inch Si (111) substrate.
A recess structure was formed under a gate electrode by
A. Transient Response of Drain Current
To investigate the effect from the traps in a fabricated device,
we use the current transient method [3] by applying gate and
drain bias pulses shown in Fig. 5 at different temperatures. Fig.
6 shows the current transient response of the recessed-gate
AlGaN/GaN MOSHFET under different gate bias pulse
conditions at temperatures (T) of 27 oC and 50 oC. The drain
current decreases with time due to the trapping of electrons
when the current is monitored for a long time (> 100 s) with a
relatively long sampling time (tsampling = 4 ms). In Fig. 7, the
drain current transient behavior is shown with time when the
drain bias pulse is applied at different temperatures. When the
drain bias is small, the drain current decreases with time.
However, the current increases abnormally when drain bias is
large and T is relatively low. It seems that applied drain pulse
detraps in part the trapped electrons near the recessed-gate so
that the drain current increases. Fig. 8 shows behavior of
characteristics times (τ) obtained by fitting the drain current
transient with the gate step-up bias into stretched exponential
equation by controlling τ and amplitude (ai) [3]. Extracted τs
can be categorized into two groups depending on the T
dependence as shown in Fig. 8. The τ in group 1 hardly varies
with T, but the τ in group 2 significantly decreases with
increasing T. Interestingly, the traps extracted from the drain
bias transient as shown in Fig. 9 have T dependence only,

978-1-4673-4871-3/12/$31.00 ©2012 IEEE 13.2.1 IEDM12-303

 which is similar to the group 2 of the gate bias transient. It
seems that the traps related to the group 1 are located in the
GaN layer under the gate where the channel is formed and have
no dependency on T since trap energy (Et) is similar to the
Fermi energy (EF) of the channel electron. The traps related to
the group 2 seem to be located near the interface between the
gate oxide and the GaN, and AlGaN layer. From the Arrhenius
plot in Fig. 10, the activation energy (Ea) of the trap related to
the group 2 with the gate step-up bias is extracted to 0.66 eV
(Fig. 10 (a)). The Ea extracted from the drain step-up bias is
0.73 eV (Fig. 10 (b)). Both values are similar and also similar
to the reported value which is extracted from the traps in
AlGaN layer (0.72 eV) [3].
To see the transient of drain current just after applying gate
pulse, we prepared transient behavior with a very short
sampling time (tsampling = 0.1 μs) as shown in Fig. 11. Although
the pulse scheme is the same as those explained in Fig. 5, the
transient behavior is different from those in Figs. 6 and 7, and
needs to be studied further.
B. Frequency Dependent Conductance Method and C-V
Fig. 12 shows measured G/ω versus frequency (f) as
parameter of gate bias (VG). The frequency dependent
conductance method shows the frequency response of the trap
with various VGs [4]. Peak amplitude and peak f are related to
the density of trap states and the characteristic time of traps,
respectively. As the VG increases, the peak amplitude of f-G/ ω
curve increases and the peak moves to higher frequency. From
the data in Fig. 12, we extracted trap density (Dit) which is
shown in Fig. 13 by changing ET-EC extracted from the τ. The
Dit increases exponentially as close to the conduction band
(EC). At an ET-EC of -0.4 eV, the Dit is ~1×1012 cm-2eV-1.
Fig. 14 shows gate capacitance versus VG as a parameter of f.
As a control, dotted lines represent the C-V curves of the
MOSHEMT without the gate recess. Both devices show
significant difference in C-V with f due to the traps in the
AlGaN layer. The control device has a threshold voltage (Vth)
of ~ -11 V so that the gate capacitance (CG) starts to increase
near Vth. As VG increases more than Vth, the CG increases
slightly at 1 kHz, but the CG is nearly constant at 1 MHz, since
the channel electrons moves easily to a part of the AlGaN layer
for a given VG at 1 kHz. At the VG of ~0 V, the CG increases
rapidly due to full inversion up to the top of the AlGaN layer.
Then the CG at 1 kHz is constant for further increased VG
because the potential well is limited to the gate oxide. When
the f is 1 MHz, the capacitance decreases significantly, which
means there are the traps responsible for the decrease at high f
somewhere in the device. From device simulation, we found
that the taps in the AlGaN layer are the most responsible for the
decrease of the capacitance as explained in Fig. 15. Fig. 16
explains schematically the frequency behavior in the C-V. At
low f, the electrons moves to the gate oxide through the traps in
the AlGaN layer and respond to the gate bias variation when
the AlGaN layer is inverted. However, at high f, electrons in
the channel cannot move near the gate oxide to respond VG
variation due to slower charging/discharging times of traps,
IEDM12-304 13.2.2
which leads to reduced gate capacitance.
C. Pulsed I-V
The frequency dependence is also observed in pulsed I-V
characteristics. The drain currents are measured for pulsed gate
bias which is changed from -2 V to 4 V and get back to -2 V
without any break (a round-trip pulsed biasing). Note that ID
collapse due to the electron trapping from the gate into the
AlGaN surface is not occurred because high-quality gate oxide
was formed with a thickness of 20 nm. In Fig. 17 showing
pulsed I-V where a pulse width (tw) is changed at a fixed duty
of 50%, IDs for a tw range of 100 μs ~ 1 μs increases compared
to that of DC I-V since electron trapping to the traps near the
SiO2/GaN interface is decreased and Vth is decreased as a result.
For a shorter pulse width of 0.1 μs, the ID degrades appreciably
for VG larger than 2 V, although the Vth is lower than that in DC
I-V as shown in Fig. 17. It is not easy to explain the
phenomenon. There has been a report on the ID degradation in
the pulsed I-V of GaN HEMT [5]. In [5], when a pulse is
applied to the gate with a pulse width of 1 μs, the ID of pulsed
I-V decreased significantly compared to that of DC I-V, which
is attributed to the series resistance change from piezoelectric
effect [6]. The piezoelectric effect seems to be insufficient to
explain the ID degradation in our device. In returning from 4 V
to -2 V, ID increases slightly and then decreases with
decreasing VG. But the ID at a tw of 0.1 μs in the VG less than 3
V is the largest. It is interesting phenomenon and needs to be
studied further.
D. Noise Power Spectrum Density
Since the effect of traps is reflected on the property of the
low frequency noise, we measured low frequency noise by
changing VG from -0.5 V to 3.9 V at a fixed VD of 0.5 V as
shown in Fig. 18. Here, the VG covers the operation region
from subthreshold to turn-on. The device presents 1/
characteristics with ~1.1 as represented by dashed line.
Extracted Hooge parameter α is 10-3~10-2, which is in the
same order of reported α (~10-3) of the HEMT devices grown
on Si (111) substrate [7]. The normalized noise power
decreases with increasing VG. In Fig. 19, we plotted the
normalized noise power versus drain current as a parameter of
the distance (LGD) between the gate and the drain under the
same bias condition as that in Fig. 18. Regardless of the LGD,
the noise spectra are similar. It is interesting to see that the
noise power is decreased with increasing ID from the
subthreshold region and then increased around the ID of ~1 mA
since the noise from the S/D contact becomes dominant.
Conclusion
We characterized traps and trap-related effect in normally-
off AlGaN/GaN-based MOSHEMT with SiO2 gate oxide.
Transient drain current behavior with gate and drain bias pulse
was systematically investigated. Traps were extracted using
frequency dependent conductance method. Significant
capacitance decrease in inversion region of device at a
frequency of 1 MHz was attributed to the traps in AlGaN layer.
 Source Drain Fig. 2. TEM cross-sectional
Gate Source Gate Drain views of fabricated device.

(a) TEM images of

GaN recessed-gate AlGaN/GaN
(a) Channel GaN
MOSHEMT
AlGaN Recessed Gate
Buffer SiNx Passivation (b) Magnified TEM image of
SiO2 recessed-gate region
Gate
Si-wafer (c) TEM view showing
threading dislocations nearby
Fig. 1. Schematic cross-sectional view of GaN the channel region
SiO2 AlGaN
recess gate AlGaN/GaN MOS-HEMT built on
(b) (c)
silicon substrate 50 nm
-2
10
7
o
T = 27 C (a) T = 120oC (b)
VG = 4.5 V
12
TMeas
-4
10 6 VG= 3 V
VG= 3 V
TMeas
10
-6 5 VMeas
VD = 0.5 V VBase

Voltage
VG = 3.5 V

Voltage
8 VG= 2 V
ID (mA)

4
ID (mA)

10
-8 Hysteresis
I (A)

ID 3 VG= 2 V
-10
VG = 2.5 V
10 IG 4 2 VG= 1 V VBase VMeas
-12 VG = 1.5 V VG= 1 V
10 1
VG < 0.5 V VG= 0 V VG= 0 V
-14 0 0 (a) (b)
10
-3 -2 -1 0 1 2 3 40 1 2 3 4 5 6 0 1 2 3 4 0 1 2 3 4 5
VG (V) VD (V) VG (V) Time Time
Fig. 3. (a) ID-VG curves and the gate leakage at Fig. 4. ID-VD curves under different Fig. 5. Transient bias schemes for observing
VD = 0.5 V. (b) ID-VD curves with various gate temperatures (a) 27 oC and (b) 120 oC. A transient ID response. (a) step-up and (b)
biases (VG = 0.5, 1.5, 2.5, 3.5 and 4.5 V). hysteresis in the drain current is observed in step-down biases are applied to devices.
high temperature condition.

1.00 1.00 o
1.20 T = 27oC 1.05 T = 50 C
o VBase = 0.5 V
0.99 T = 27 C o
T = 50 C 1.15 VMeas = 4 V ~ 7 V 1.00
Normalized ID

Normalized ID

Normalized ID
0.96
Normalized ID

VBase = 0 V ΔVMeas = 1 V
0.98 1.10 0.95
VMeas = 2 V ~ 5 V VBase = 0 V VD Step Transient VBase = 0.5 V
VMeas = 2 V ~5 V 1.05 V = 2 V (Const) 0.90
0.97 ΔVMeas = 1 V VMeas = 4 V ~ 7 V
0.92 G
ΔVMeas = 1 V
ΔVMeas = 1 V
VG Step Transient 1.00 0.85
0.96 VG Step Transient VD Step Transient
VD = 0.5 V (Const)
(a) 0.88 VD = 0.5 V (Const) (b)
0.95 (a) 0.80 V = 2 V (Const) (b)
G
0.95 -1 0 1 2 -1 0 1 2 -1 0 1 2 -1 0 1 2
10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10
Time (sec) Time (sec) Time (sec) Time (sec)
Fig. 6. Slow transient responses under different temperatures, (a) 27 Fig. 7. Slow transient responses under different temperatures, (a) 27
o
o
C and (b) 50 oC. Step-up bias is applied to the gate electrode and VMeas C and (b) 50 oC. Step-up bias is applied to the drain electrode and
is varied from 2 V to 5 V with 1 V step. Drain bias is fixed at 0.5 V. ID VMeas is varied from 4 V to 7 V with 1V step. Gate bias is fixed at 2V.
is normalized to remove on-current difference with bias condition. ID is normalized to remove on-current difference with bias condition.
Open symbols are measured data and solid lines are fitted lines. Open symbols are measured data and solid lines are fitted lines.
T = 27 C
o
Group 2 Fig. 8. Behavior of Fig. 9. Behavior of
Group 1
characteristics times (τ) characteristics times (τ)
obtained from transient o obtained from transient
T = 27 C
responses with gate responses with drain
T = 50 C
o
step-up (Fig. 6) under step-up (Fig. 7) under
various temperatures, various temperatures,
ai (A.U.)

27, 50, 80, 120 oC. Each o 27, 50, 80, 120 oC. Each
ai (A.U.)

T = 50 C
point represents the point represents the
o
T = 80 C constant of exponentially constant of exponentially
decreasing function. decreasing function.
Group 1 represents the T = 80 C
o Each symbol is data from
points in the red solid line other VMeas condition.
o
T = 120 C and Group 2 includes the Y-axis implies the
VG= 5 V VG= 4 V points in the blue dashed VD= 7 V VD= 6 V weight of each time
VG= 3 V VG= 2 V line. Y-axis implies the T = 120 C
o
VD= 5 V VD= 4 V constant (τ).
-2 -1 0 1 2 3 weight of each time -2 -1 0 1 2 3
10 10 10 10 10 10 10 10 10 10 10 10
τ (sec) constant (τ). τ (sec)

13.2.3 IEDM12-305
 (a) VG step (b) VD step From 5 samples VG Step Transient 6 2.5
0.3
VD= 0.5 V (Const)
18 Average value of
Vmeas=4 V Vmeas=0 V 2.0
Group 1
ln(T τ ) (K sec)

G/ω (μF/cm )
2
VBase=0 V VBase=4 V
16 Group 2 4
2

1.5

ID (μA)
ID (mA)
0.2 VG = -1.4 V ~ 1 V
14 Ea = 0.66eV Ea = 0.73eV
1.0 ΔVG = 0.4 V
2

2
12
0.5
0.1
10 0.0
0
-7 -6 -5 -4 -7 -6 -5 -4 4 5 6
30 32 34 36 38 30 32 34 36 38 10 10 10 10 10 10 10 10 10 10 10
Tmeas (sec) Frequency (Hz)
1/kT (eV)
Fig. 10. Arrhenius plot of the characteristic Fig. 11. Fast (high-frequency) transient Fig. 12. Measured GP/ω versus frequency as a
times extracted from (a) gate step-up responses responses with (a) step-up (0 V to 4 V) parameter of gate bias. As VG increases, the
(b) drain step-up responses. The averaged value (b) step-down (4 V to 0 V) transient biases. peak of GP/ω moves to higher frequency and
in each group was used. becomes larger in magnitude.
400 W/ AlGaN bulk trap : f=1 kHz
13 1kHz 100 W/ AlGaN bulk trap : f=1 MHz
4x10
W/O trap : f=1 MHz
300
75

CG (A.U.)
Dit (cm eV )

13
3x10 1MHz
-1

CG (nF/cm )
2
-2

200
13 50
2x10 CV
M eter

~ exp(ET-EC) 100 25 S G D
1x10
13 AlGaN
SiO2 GaN

0 0
0 -12 -10 -8 -6 -4 -2 0 2 4 6 8 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
-0.40 -0.36 -0.32 -0.28 VG (V)
VG (V)
ET-EC (eV)
Fig. 14. C-V characteristics of two types of Fig. 15. Simulated C-V characteristics of
Fig. 13. Extracted trap density from frequency
devices with and without gate recess region gate-recessed MOSHFET at frequencies of 1
dependent conductance method. Dit nearby the
as a parameter of frequency. CG is measured kHz and 1 MHz. Dash-dot line represents C-V
conduction band fits well with exponential
while the source is floated. curve without trap at 1 MHz.
function.
-6
10
2.0 Pulsed I-V VD = 0.5 V
At low frequency, At high frequency, Pulse width split -7 ~1/f
1.1
10 VG = -0.5 ~ 3.9 V
VD = 0.5 V
1.5 ΔVG = 0.05 V
Gate Gate
SID/ID (Hz )

0.1 μs -8
-1

10
1 μs
ID (mA)

SiO2 AlGaN SiO2 AlGaN 1.0 10 μs -9

10
2

100 μs
DC -10
0.5 10
-11
10
GaN Empty trap GaN 0.0
Occupied trap -2 -1 0 1 2 3 4 10
-12
0 1 2 3
10 10 10 10
VG (V) Frequency (Hz)
Fig. 16. Low and high frequency responses of Fig. 17. Pulsed I-V curves of recessed-gate Fig. 18. Normalized power spectral density
the traps in AlGaN layer. In low frequency, MOSHFET with various pulse widths from with various gate biases from -0.5V to 3.9V.
electrons can move to the SiO2/AlGaN interface t=0.1 μs to 100 μs. In pulsed I-V, a period for The slope of the noise spectra is around 1/f1.1.
from the AlGaN/GaN interface. a bias was changed at a fixed 50% duty.

10
-7 Acknowledgement
This work was supported by Samsung in 2012.
10
-8
References
SID/ID (Hz )
-1

[1] Y. F. Wu, et al., “High-voltage Millimeter-Wave GaN HEMTs with 13.7 W/mm Power Density”, IEEE IEDM Tech,
LGD = 3μm
-9
Digest, pp. 405-407, 2007.
10
2

-1
~ID 2
~ID [2] N. Kaneko, et al., “Normally-off AlGaN/GaN HFETs using NiOx gate with recess”, IEEE ISPSD, pp.25-28, 2009.
[3] J. Joh, et al., “Impact of electrical degradation on trapping characteristics of GaN high electron mobility transistors”
10
-10
LGD = 3, 6, 9, 12 IEEE IEDM Tech, Digest, pp. 461-464, 2008.
15, 27, 30μm LGD = 30μm [4] Joseph J., et al., “Trap characterization of in-situ metal-organic chemical vapor deposition grown AlN/AlGaN/GaN
metal-insulator-semiconductor heterostructures by frequency dependent conductance technique”, Applied Physics
-11
10 -9 -8 -7 -6 -5 -4 -3 -2
Letters, pp. 033504-1~3, 2011.
10 10 10 10 10 10 10 10 [5] A. Tarakji, et al., “Mechanism of radio-frequency current collapse in GaN–AlGaN field-effect Transistors”, Applied
ID (A) Physics Letters, pp. 2169-2171, 2001.
Fig. 19. Normalized power spectral density [6] G. Simin, et al., “Induced strain mechanism of current collapse in AlGaN/GaN heterostructure field-effect
transistors”, Applied Physics Letters, pp. 2651-2653, 2001.
with drain current. In an on-current (ID) of [7] A. Curutchet, et al., “Low frequency drain noise comparison of AlGaN/GaN HEMT’s grown on silicon, SiC and
~10-3 A, contact noise becomes dominant. sapphire substrate”, Microelectronics Reliability, vol 43, pp. 1713-1718, 2003.

IEDM12-306 13.2.4