LG 47LW470S-ZB Chassis LD12P

Internal Use Only
North/Latin America http://aic.lgservice.com

Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com
LED LCD TV
SERVICE MANUAL
CHASSIS : LD12P
MODEL : 47LW470S 47LW470S-ZB
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
P/NO : MFL67002346 (1107-REV00) Printed in Korea

CONTENTS
CONTENTS .............................................................................................. 2
PRODUCT SAFETY ................................................................................. 3
SPECIFICATION ....................................................................................... 4
ADJUSTMENT INSTRUCTION .............................................................. 10
BLOCK DIAGRAM.................................................................................. 17
EXPLODED VIEW .................................................................................. 18
SCHEMATIC CIRCUIT DIAGRAM ..............................................................
Copyright © 2011 LG Electronics. Inc. All rights reserved. -2- LGE Internal Use Only
Only for training and service purposes
SAFETY PRECAUTIONS
IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC Do not use a line Isolation Transformer during this check.
power line. Use a transformer of adequate power rating as this Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
protects the technician from accidents resulting in personal injury between a known good earth ground (Water Pipe, Conduit, etc.)
from electrical shocks. and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
It will also protect the receiver and it's components from being with 1000 ohms/volt or more sensitivity.
damaged by accidental shorts of the circuitry that may be Reverse plug the AC cord into the AC outlet and repeat AC voltage
inadvertently introduced during the service operation. measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
If any fuse (or Fusible Resistor) in this TV receiver is blown, 0.5 mA.
replace it with the specified. In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
When replacing a high wattage resistor (Oxide Metal Film Resistor, repaired before it is returned to the customer.
over 1 W), keep the resistor 10 mm away from PCB.
Leakage Current Hot Check circuit
Keep wires away from high voltage or high temperature parts.
Before returning the receiver to the customer, AC Volt-meter
always perform an AC leakage current check on the exposed

metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical Good Earth Ground
shock. such as WATER PIPE,
To Instrument’s CONDUIT etc.
0.15 uF
Leakage Current Cold Check(Antenna Cold Check) exposed
With the instrument AC plug removed from AC source, connect an METALLIC PARTS
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC 1.5 Kohm/10W
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc. When 25A is impressed between Earth and 2nd Ground
If the exposed metallic part has a return path to the chassis, the for 1 second, Resistance must be less than 0.1 Ω
measured resistance should be between 1 MΩ and 5.2 MΩ.
*Base on Adjustment standard
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.
1. Application range 3. Test method

This specification is applied to the LCD TV used LD12P 1) Performance: LGE TV test method followed
chassis. 2) Demanded other specification
- Safety : CE, IEC specification
- EMC :CE, IEC
2. Requirement for Test
Each part is tested as below without special appointment.
1) Temperature: 25 ºC ± 5 ºC(77 ºF ± 9 ºF), CST: 40 ºC ± 5 ºC

2) Relative Humidity : 65 % ± 10 %
3) Power Voltage : Standard input voltage (AC 100-240 V~,
50 / 60 Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed
each drawing and specification by part number in
accordance with BOM.
5) The receiver must be operated for about 5 minutes prior to
the adjustment.
4. Model General Specification

No. Item Specification Remarks
1 Market EU(PAL Market-36Countries) DTV & Analog (Total 36 countries)
DTV (MPEG2/4, DVB-T) : 31 countries
(England/Italy/Germany/France/Spain/Sweden/Finland/Netherlands/Belgium/Luxemburg/
Greece/Denmark/Czech/Austria /Hungary/Swiss/Croatia/Turkey/Norway/Slovenia/Poland/
Ukraine/Portugal/Ireland/Moroco/Latvia/Estonia/Lithania/Rumania/Russia/Slovakia)
DTV (MPEG2/4, DVB-T2): 5 countries

(England/Sweden/Finland/Denmark/Norway)
DTV (MPEG2/4, DVB-C): 10 countries

(Sweden/Finland/Denmark/Norway/Austria/Swiss/Germany/Netherlands/Hungary/Slovenia)
DTV (MPEG2/4, DVB-S) : 31 countries

Albania/Austria/Belgium/Bosnia/Bulgaria/Croatia/Czech/Estonia/France/Germany/Greece/
Hungary/Ireland/Italy/Kazakhstan/Latvia/Lithuania/Luxembourg/Morocco/Netherlands/Poland/
Portugal/Romania/Russia/Serbia/Slovenia/Spain/Slovakia/Switzerland/Turkey/Ukraine
Analog Only - 5 countries

(Bosnia/Serbia/Bulgaria/Albania/Kazakhstan)
Supported satellite : 22 satellites

HISPASAT 1C/1D, ATLANTIC BIRD 2, NILESAT 101/102, ATLANTIC BIRD 3, AMOS 2/3,
THOR 5/6, IRIUS 4, EUTELSAT-W3A, EUROBIRD 9A, EUTELSAT-W2A, HOTBIRD 6/8/9,
EUTELSAT-SESAT, ASTRA 1L/H/M/KR, ASTRA 3A/3B, BADR 4/6, ASTRA 2D, EUROBIRD 3,
EUTELSAT-W7, HELLASSAT 2, EXPRESS AM1, TURKSAT 2A/3A, INTERSAT10
2 Broadcasting system 1) PAL-BG - DVB-T2/S is supported in specific models.
2) PAL-DK 1. DVB-T2 : Model name : xxxxxxxT
3) PAL-I/I’ 2. DVB-S : Model name : xxxxxxxS
4) SECAM DK,BG,I,L/L’ - SECAM L/L’ is not supported in DVB-T2 models.
5) DVB-T/C
6) DVB-T2
7) DVB-S
No. Item Specification Remarks
3 Receiving system Analog : Upper Heterodyne G DVB-T
Digital : COFDM , QAM - Guard Interval(Bitrate_Mbit/s)
1/4, 1/8, 1/16, 1/32
- Modulation : Code Rate
QPSK : 1/2, 2/3, 3/4, 5/6, 7/8
16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
G DVB-C
- Symbolrate : 4.0Msymbols/s to 7.2Msymbols/s
- Modulation : 16QAM, 64-QAM, 128-QAM and 256-QAM
G DVB-T2
- Guard Interval(Bitrate_Mbit/s)
1/4,1/8,1/16,1/32,1/128,19/128,19/256,
- Modulation : Code Rate
QPSK : 1/2, 2/5, 2/3, 3/4, 5/6
16-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
64-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
256-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
G DVB-S
- Symbolrate
DVB-S2 (8PSK / QPSK) : 2 ~ 45Msymbol/s
DVB-S (QPSK) : 2 ~ 45Msymbol/s
- viterbi
DVB-S mode : 1/2, 2/3, 3/4, 5/6, 7/8
DVB-S2 mode : 1/2, 2/3, 3/4, 3/5, 4/5, 5/6, 8/9, 9/10
4 Scart Jack (1EA) PAL, SECAM Scart Jack is Full scart and support RF-OUT(analog & DTV)
Not support DTV Auto AV.
5 Video Input RCA(1EA) PAL, SECAM, NTSC 4System : PAL, SECAM, NTSC, PAL60
6 Component Input(1EA) Y/Cb/Cr, Y/Pb/Pr
7 RGB Input RGB-PC Analog(D-SUB 15PIN)
8 HDMI Input (3EA) HDMI1-DTV (DVI) PC(HDMI version 1.3)
HDMI2-DTV Support HDCP
HDMI3-DTV
9 Audio Input (3EA) RGB/DVI Audio, Component, AV L/R Input
10 SDPIF out (1EA) SPDIF out
11 Earphone out (1EA) Antenna, AV1, AV2, AV3, Component,
RGB, HDMI1, HDMI2, HDMI3, USB
12 USB (1EA) EMF JPEG, MP3
For Service (download)
DivX HD
5. Component Video Input (Y, CB/PB, CR/PR)
Specification
No. Remark
Resolution H-freq(kHz) V-freq(Hz)
1. 720x480 15.73 60.00 SDTV,DVD 480i
2. 720x480 15.63 59.94 SDTV,DVD 480i
3. 720x480 31.47 59.94 480p
4. 720x480 31.50 60.00 480p
5. 720x576 15.625 50.00 SDTV,DVD 625 Line
6. 720x576 31.25 50.00 HDTV 576p
7. 1280x720 45.00 50.00 HDTV 720p
8. 1280x720 44.96 59.94 HDTV 720p
9. 1280x720 45.00 60.00 HDTV 720p
10. 1920x1080 31.25 50.00 HDTV 1080i
11. 1920x1080 33.75 60.00 HDTV 1080i
12. 1920x1080 33.72 59.94 HDTV 1080i
13. 1920x1080 56.250 50 HDTV 1080p
14. 1920x1080 67.5 60 HDTV 1080p
6. RGB Input (PC)

Specification
No. Proposed Remarks
Resolution H-freq(kHz) V-freq(Hz) Pixel Clock(MHz)
1. 720*400 31.468 70.08 28.321 For only DOS mode
2. 640*480 31.469 59.94 25.17 VESA Input 848*480 60 Hz, 852*480 60 Hz
-> 640*480 60 Hz Display
3. 800*600 37.879 60.31 40.00 VESA
4. 1024*768 48.363 60.00 65.00 VESA(XGA)
5. 1360*768 47.72 59.8 84.75 WXGA
6. 1920*1080 66.587 59.93 138.625 WUXGA FHD model
7. HDMI Input
(1) DTV Mode
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark
1. 720*480 31.469 / 31.5 59.94 / 60 27.00 / 27.03 SDTV 480P
2. 720*576 31.25 50 54 SDTV 576P
3. 1280*720 37.500 50 74.25 HDTV 720P
4. 1280*720 44.96 / 45 59.94 / 60 74.17 / 74.25 HDTV 720P
5. 1920*1080 33.72 / 33.75 59.94 / 60 74.17 / 74.25 HDTV 1080I
6. 1920*1080 28.125 50.00 74.25 HDTV 1080I
7. 1920*1080 26.97 / 27 23.97 / 24 74.17 / 74.25 HDTV 1080P
8. 1920*1080 33.716 / 33.75 29.976 / 30.00 74.25 HDTV 1080P
9. 1920*1080 56.250 50 148.5 HDTV 1080P
10. 1920*1080 67.43 / 67.5 59.94 / 60 148.35 / 148.50 HDTV 1080P
(2) PC Mode
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark
1. 720*400 31.468 70.08 28.321 HDCP
2. 640*480 31.469 59.94 25.17 VESA HDCP
3. 800*600 37.879 60.31 40.00 VESA HDCP
4. 1024*768 48.363 60.00 65.00 VESA(XGA) HDCP
5. 1360*768 47.72 59.8 84.75 WXGA HDCP
6. 1280*1024 63.595 60.0 108.875 SXGA HDCP/FHD model
7. 1920*1080 67.5 60.00 138.625 WUXGA HDCP/FHD model
8. 3D Mode
(1) HDMI Input (1.4a)
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode
1 1920*1080 53.95 / 54 23.98 / 24 148.35/148.5 HDTV 1080P Frame packing
2 1280*720 89.9 / 90 59.94/60 148.35/148.5 HDTV 720P Frame packing
3 1280*720 75 50 148.5 HDTV 720P Frame packing
4 1920*1080 67.5 60 148.5 HDTV 1080P Side by Side(half), Top and bottom
5 1920*1080 56.3 50 148.5 HDTV 1080P Side by Side(half), Top and bottom
6 1280*720 45 60 74.25 HDTV 720P Side by Side(half), Top and Bottom
7 1280*720 37.5 50 74.25 HDTV 720P Side by Side(half), Top and Bottom
8 1920*1080 33.7 60 74.25 HDTV 1080i Side by Side(half), Top and Bottom
9 1920*1080 28.1 50 74.25 HDTV 1080i Side by Side(half), Top and Bottom
10 1920*1080 27 24 74.25 HDTV 1080P Side by Side(half), Top and Bottom
11 1920*1080 33.7 30 89.1 HDTV 1080P Side by Side(half), Top and Bottom
(2) HDMI Input (1.3)

1 1280*720 45.00 60.00 74.25 HDTV 720P Side by Side, Top & Bottom
2 1280*720 37.500 50 74.25 HDTV 720P Side by Side, Top & Bottom
3 1920*1080 33.75 60.00 74.25 HDTV 1080I Side by Side, Top & Bottom
4 1920*1080 28.125 50.00 74.25 HDTV 1080I Side by Side, Top & Bottom
5 1920*1080 27.00 24.00 74.25 HDTV 1080P Side by Side, Top & Bottom,
Checkerboard
Checkerboard
Checkerboard, Single Frame Sequential
8 1920*1080 56.250 50 148.5 HDTV 1080P Side by Side, Top & Bottom,
Checkerboard, Single Frame Sequential
(3) RF 3D Input(DTV)
2 1920*1080 28.125 50 74.25 HDTV 1080I Side by Side, Top & Bottom
(4) USB Input

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode Proposed
1 1920*1080 33.75 30.000 74.25 Side by Side HDTV 1080P
Top & Bottom
Checkerboard
(5) RGB-PC Input
(6) DLNA
1 1920*1080 33.75 30 HDTV 1080P Side by Side, Top & Bottom,
Checkerboard
(7) 3D Input mode

No. Side by Side Top & Bottom Checkerboard Single Frame Sequential Frame Packing
1.
L R
L
ADJUSTMENT INSTRUCTION
1. Application Range
This specification sheet is applied to all of the LCD TV with
LD12P chassis.
2. Designation
(1) Because this is not a hot chassis, it is not necessary to use
an isolation transformer. However, the use of isolation
transformer will help protect test instrument.
(2) Adjustment must be done in the correct order.
(3) The adjustment must be performed in the circumstance of
25 ºC ± 5 ºC of temperature and 65 % ± 10 % of relative
humidity if there is no specific designation.
(4) The input voltage of the receiver must keep AC 100-240
V~, 50 / 60Hz.
(5) The receiver must be operated for about 5 minutes prior to
the adjustment when module is in the circumstance of over
15.
In case of keeping module is in the circumstance of 0 °C, it

should be placed in the circumstance of above 15 °C for 2
hours
In case of keeping module is in the circumstance of below -

20 °C, it should be placed in the circumstance of above 15 3.2. LAN Inspection
°C for 3 hours.
(1) Equipment & Condition
A Each other connection to LAN Port of IP Hub and Jig
[Caution]
When still image is displayed for a period of 20 minutes or
longer (especially where W/B scale is strong. Digital pattern
13ch and/or Cross hatch pattern 09ch), there can some
afterimage in the black level area.
3. Automatic Adjustment
3.1. MAC Address
(1) Equipment & Condition
(2) LAN inspection solution
- Play file: Serial.exe
A LAN Port connection with PCB
- MAC Address edit
A Network setting at MENU Mode of TV
- Input Start / End MAC address
A setting automatic IP
A Setting state confirmation
(2) Download method
-> If automatic setting is finished, you confirm IP and
1) Communication Prot connection
MAC Address.
PCBA PC(RS-232C)
RS-232C Po rt
Connect: PCBA Jig-> RS-232C Port== PC-> RS-232C Port
2) MAC Address & CI+ key & Widevine key download

- Com 1,2,3,4 and 115200(Baud rate)
- Mode check : Online Only
- Check the test process: DETECT -> MAC -> CI -> Widevine
- Play : START
- Result : Ready, Test, OK or NG
- Printer Out (MAC Address Label)
Copyright © 2011 LG Electronics. Inc. All rights reserved. - 10 - LGE Internal Use Only
3.3. Widevine Key Inspection 3.5. Model name & serial number download
- Confirm key input Data at the “IN START” MENU Mode. (1) Model name & Serial number D/L
A Press “Power on” key of service remote control.
(Baud rate : 115200 bps)
A Connect RS232 Signal Cable to RS-232 Jack.
A Write Serial number by use RS-232.
A Must check the serial number at Instart menu.
(2) Method & notice

A. Serial number D/L is using of scan equipment.
B. Setting of scan equipment operated by Manufacturing
Technology Group.
C. Serial number D/L must be conformed when it is produced
in production line, because serial number D/L is mandatory
by D-book 4.0.
3.4. LAN PORT INSPECTION(PING TEST) * Manual Download (Model Name and Serial Number)
Connect SET -> LAN port == PC -> LAN Port. If the TV set is downloaded by OTA or service man, sometimes
model name or serial number is initialized.(Not always)
SET PC There is impossible to download by bar code scan, so It
(1) Equipment setting need Manual download.
1) Play the LAN Port Test PROGRAM. a. Press the ‘instart’ key of ADJ remote control.
2) Input IP set up for an inspection to Test Program. b. Go to the menu ‘5.Model Number D/L’ like below photo.
*IP Number : 12.12.2.2 c. Input the Factory model name(ex 42LD450-ZA) or Serial
number like photo.
(2) LAN PORT inspection (PING TEST)
1) Play the LAN Port Test Program.
2) Connect each other LAN Port Jack.
3) Play Test (F9) button and confirm OK Message.
4) Remove LAN cable.
d. Check the model name Instart menu. -> Factory name

displayed. (ex 32LV3700-ZA)
e. Check the Diagnostics.(DTV country only) -> Buyer model
displayed. (ex 32LV3700)
3.7. CI+ Key checking method 4. Manual Adjustment
Check whether the key was downloaded or not at ‘In Start’
menu. (Refer to below).
4.1. EDID(The Extended Display Identification
Data)/DDC(Display Data Channel) download
(1) Overview
It is a VESA regulation. A PC or a MNT will display an
optimal resolution through information sharing without any
necessity of user input. It is a realization of “Plug and Play”.
=> Check the Download to CI+ key value in LGset.
(2) Equipment
3.7.1. Check the method of CI+ Key value - Adjustment remote control
(1) Check the method on Instart menu. - Since embedded EDID data is used, EDID download JIG,
(2) Check the method of RS232C Command. HDMI cable and D-sub cable are not need.
1) Into the main assembly mode (RS232 : aa 00 00)
CMD 1 CMD 2 Data 0 (3)Download method
1) Press ADJ key on the Adjustment remote control, then
A A 0 0 select “12.EDID D/L”, by pressing Enter key, enter EDID
D/L menu.
2) Check the key download for transmitted command. 2) Select [Start] button by pressing Enter key, HDMI1/
(RS232 : ci 00 10) HDMI2/ HDMI3/ RGB are Writing and display OK or NG.
CMD 1 CMD 2 Data 0
(4) EDID DATA
C I 1 0 A HDMI
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
3) Result value 0x00 00 FF FF FF FF FF FF 00 1E 6D ⓐ ⓑ
- Normally status for download : OKx 0x01 ⓒ 01 03 80 10 09 78 0A EE 91 A3 54 4C 99 26
- Abnormally status for download : NGx 0x02 0F 50 54 A1 08 00 71 40 81 C0 81 00 81 80 95 00
0x03 90 40 A9 C0 B3 00 02 3A 80 18 71 38 2D 40 58 2C
3.7.2. Check the method of CI+ Key value (RS232) 0x04 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30
1) Into the main assembly mode (RS232 : aa 00 00) 0x05 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 39
0x06 3F 1F 52 10 00 0A 20 20 20 20 20 20 ⓓ
CMD 1 CMD 2 Data 0
0x07 ⓓ 01 ⓔ1
A A 0 0 0x00 02 03 26 F1 4E 10 1F 84 13 05 14 03 02 12 20 21
0x01 22 15 01 26 15 07 50 09 57 07 67 ⓕ
2) Check the method of CI+ key by command. 0x02 ⓕ E3 05 03 01 01 1D 80 18 71 1C 16 20 58 2C
(RS232 : ci 00 20) 0x03 25 00 A0 5A 00 00 00 9E 01 1D 00 80 51 D0 1A 20
0x04 6E 88 55 00 A0 5A 00 00 00 1A 02 3A 80 18 71 38
CMD 1 CMD 2 Data 0
0x05 2D 40 58 2C 45 00 A0 5A 00 00 00 1E 66 21 50 B0
C I 2 0 0x06 51 00 1B 30 40 70 36 00 A0 5A 00 00 00 1E 00 00
0x07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ⓔ2
3) Result value
i 01 OK 1d1852d21c1ed5dcx A RGB
CI+ key Value 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
0x00 00 FF FF FF FF FF FF 00 1E 6D ⓐ ⓑ
0x01 ⓒ 01 03 68 10 09 78 0A EE 91 A3 54 4C 99 26
3.8. WIFI MAC ADDRESS CHECK 0x02 0F 50 54 A1 08 00 71 4F 01 01 01 01 01 01 95 00
(1) Using RS232 0x03 90 40 A9 C0 B3 00 02 3A 80 18 71 38 2D 40 58 2C

0x04 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30
H-freq(kHz) V-freq.(Hz) 0x05 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 3A
Transmission [A][I][ ][Set ID][ ][20][Cr] [O][K][X] or [NG] 0x06 3E 1E 53 10 00 0A 20 20 20 20 20 20 ⓓ

0x07 ⓓ 01 ⓔ3
(2) Check the menu on in-start.
AReference 4.2.3. Equipment connection MAP
- HDMI1 ~ HDMI3 / RGB
- In the data of EDID, bellows may be different by S/W or Co lo r Analyzer
Input mode. Probe RS -232C
Co m p ut er
RS -232C
ⓐ Product ID RS -232C
Pat t ern Generat o r

Model Name HEX EDID Table DDC Function Signal Source
ALL 0001 0100 Analog * If TV internal pattern is used, not needed
0001 0100 Digital

4.2.4. Adj. Command (Protocol)
ⓑ Serial No. : Controlled on product line
<Command Format>
MODEL MODEL NAME(HEX) LEN CMD VAL CS
all 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20
- LEN: Number of Data Byte to be sent
ⓒ Month, Year: Controlled on production line: - CMD: Command
ex) Monthly : ‘01’ -> ‘01’ - VAL: FOS Data value
Year : ‘2010’ -> ‘14’ - CS: Checksum of sent data
ⓓ Model Name(Hex): - A: Acknowledge
Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX]
ⓔ Checksum: Changeable by total EDID data.
INPUT ⓔ1 ⓔ2 ⓔ3 A RS-232C Command used during auto-adj.
HDMI1 7F CB X RS-232C COMMAND Explanation
HDMI2 7F BB X [CMD ID DATA]
HDMI3 7F AB X wb 00 00 Begin White Balance adj.
RGB X X 98 wb 00 10 Gain adj.(internal white pattern)
ⓕ Vendor Specific(HDMI) wb 00 1f Gain adj. completed
INPUT MODEL NAME(HEX) wb 00 20 Offset adj.(internal white pattern)
HDMI1 78 03 0C 00 10 00 B8 2D 20 C0 0E 01 40 0A 3C 08 10 18 10 98 10 58 10 38 10
wb 00 2f Offset adj. completed
HDMI2 78 03 0C 00 20 00 B8 2D 20 C0 0E 01 40 0A 3C 08 10 18 10 98 10 58 10 38 10
wb 00 ff End White Balance adj.(Internal pattern disappears)
HDMI3 78 03 0C 00 30 00 B8 2D 20 C0 0E 01 40 0A 3C 08 10 18 10 98 10 58 10 38 10
RGB 78 03 0C 00 40 00 B8 2D 20 C0 0E 01 40 0A 3C 08 10 18 10 98 10 58 10 38 10 Ex) wb 00 00 -> Begin white balance auto-adj.
wb 00 10 -> Gain adj.
ja 00 ff -> Adj. data
4.2. White Balance Adjustment jb 00 c0
...
4.2.1. Overview
...
(1) W/B adj. Objective & How-it-works
wb 00 1f -> Gain adj. completed
(2) Objective: To reduce each Panel’s W/B deviation
*(wb 00 20(Start), wb 00 2f(completed)) -> Off-set adj.
(3) How-it-works : When R/G/B gain in the OSD is at 192, it
wb 00 ff -> End white balance auto-adj.
means the panel is at its Full Dynamic Range. In order to
prevent saturation of Full Dynamic range and data, one of
A Adj. Map
R/G/B is fixed at 192, and the other two is lowered to find
the desired value. ITEM Command Data Range(Hex.) Default(Decimal)
(4) Adj. condition : normal temperature Cmd 1 Cmd 2 Min Max
1) Surrounding Temperature : 25 ºC ± 5 ºC Cool R-Gain j g 00 C0
2) Warm-up time: About 5 Min G-Gain j h 00 C0
3) Surrounding Humidity : 20 % ~ 80 %
B-Gain j i 00 C0
R-Cut
4.2.2 Equipment
1) Color Analyzer: CA-210 (LED Module : CH 14) G-Cut
2) Adjustment Computer(During auto adj., RS-232C protocol is B-Cut
needed) Medium R-Gain j a 00 C0
3) Adjustment remote control G-Gain j b 00 C0
4) Video Signal Generator MSPG-925F 720p/204-Gray
B-Gain j c 00 C0
(Model:217, Pattern:49)
R-Cut
-> Only when internal pattern is not available
G-Cut
A Color Analyzer Matrix should be calibrated using CS-1000. B-Cut
Warm R-Gain j d 00 C0
G-Gain j e 00 C0
B-Gain j f 00 C0
R-Cut
G-Cut
A 3 Command White Balance Adj. Map 4.2.6. Reference (White Balance Adj. coordinate
Command SetID R Gain(HEX) G Gain(HEX) B Gain(HEX) and temperature)
(lower case ASCII) A Luminance : 204 Gray
CMD1 CMD2 MIN MAX MIN MAX MIN MAX A Standard color coordinate and temperature using CS-1000
(over 26 inch)
Cool j j 00 00 C0 00 C0 00 C0
Medium j k 00 00 C0 00 C0 00 C0 Mode Color Coordination Temp ∆UV
Warm j l 00 00 C0 00 C0 00 C0 x y
COOL 0.269 0.273 13000 K 0.0000
A Infrared Sensor Adj. Map MEDIUM 0.285 0.293 9300 K 0.0000
Command R Gain(HEX) G Gain(HEX) B Gain(HEX) WARM 0.313 0.329 6500 K 0.0000
(lower case ASCII)
CMD1 CMD2 MIN MAX MIN MAX MIN MAX
A Standard color coordinate and temperature using CA-210
Cool 1 C 00 C0 00 C0 00 C0
(CH 14)
Medium 1 D 00 C0 00 C0 00 C0
Warm 1 E 00 C0 00 C0 00 C0 Mode Color Coordination Temp ∆UV
x y
COOL 0.269 ± 0.002 0.273 ± 0.002 13000 K 0.0000
4.2.5. Adj. method
(1) Auto adj. method MEDIUM 0.285 ± 0.002 0.293 ± 0.002 9300 K 0.0000
1) Set TV in adj. mode using POWER ON key. WARM 0.313 ± 0.002 0.329 ± 0.002 6500 K 0.0000
2) Zero calibrate probe then place it on the center of the
Display.
3) Connect Cable (RS-232C) 4.2.7. Edge LED White balance table
4) Select mode in adj. Program and begin adjustment. A IOP & Edge LED module change color coordinate because
5) When adj. is completed(OK Sign), check adj. status pre of aging time.
mode. (Warm, Medium, Cool) A Apply under the color coordinate table, for compensated
6) Remove probe and RS-232C cable to complete adj.. aging time.
- EDGE LED(LW47XX)
A W/B Adj. must begin as start command “wb 00 00” , and
GP2 Aging Time Cool Medium Warm
finish as end command “wb 00 ff”, and Adj. offset if need.
(Min.) X Y X Y X Y
(2) Manual adj. method 269 273 285 293 313 329
1) Set TV in Adj. mode using POWER ON. 1 0-2 280 291 296 311 319 340
2) Zero Calibrate the probe of Color Analyzer, then place it 2 3-5 278 288 294 308 317 338
on the center of LCD module within 10cm of the surface.
3 6-9 276 285 292 305 315 335
3) Press ADJ key -> EZ adjust using adjustment remote
control -> 9.White-Balance then press the cursor to the 4 10-15 274 282 290 302 313 332
right key (G).(When key(G) is pressed 216 Gray internal 5 20-35 273 279 289 299 312 329
pattern will be displayed.) 6 36-49 270 276 287 296 310 326
4) One of R Gain / G Gain / B Gain should be fixed at 192, 7 50-79 269 273 286 293 308 323
and the rest will be lowered to meet the desired value. 8 Over 80 269 273 285 293 308 323
5) Adjustment is performed in COOL, MEDIUM, WARM 3
modes of color temperature.
A If internal pattern is not available, use RF input. In EZ

Adj. menu 9.White Balance, you can select one of 2 Test
-pattern: ON, OFF. Default is inner(ON). By selecting
OFF, you can adjust using RF signal in 216 gray pattern.
A Adj. condition and cautionary items

1) Lighting condition in surrounding area
Surrounding lighting should be lower 10 lux. Try to
isolate adj. area into dark surrounding.
2) Probe location
: Color Analyzer(CA-210) probe should be within 10 cm
and perpendicular of the module surface.(80°~100°)
3) Aging time
- After Aging Start, keep the Power ON status during
5 Minutes.
- In case of LCD, Back-light on should be checked
using no signal or Full-white pattern.
4.3. Wireless function check 4.5. 3D function test
Step 1) Connect set and Dongle of Wireless to Cable of HDMI 4.5.1. HDMI 3D
& TTA 20Pin. (Pattern Generator MSHG-600, MSPG-6100 [Support HDMI 1.4])
Step 2) At OSD of SET, check the message like Fig.3. * HDMI mode No. 872, pattern No. 83)
Step 3) Detach Cable of Wireless Dongle. 1) Please input 3D test pattern like below
Connect
Fig . 1 Fig . 2
< Do ng le> < Wireless Read y Set >
2) When 3D OSD appear automatically, then select green key.
Fig . 3 Connect the Dongle

( Do ng le Co nnec t io n Disp lay)
4.4. EYE-Q function check

Step 1) Turn on TV.
Step 2) Press EYE key of Adjustment remote control.
Step 3) Cover the Eye Q II sensor on the front of the using 3) Don’t wear a 3D Glasses, Check the picture like below.
your hand and wait for 6 seconds.
Step 4) Confirm that R/G/B value is lower than 10 of the “Raw
Data (Sensor data, Back light)”. If after 6 seconds,
R/G/B value is not lower than 10, replace Eye Q II
sensor.
Step 5) Remove your hand from the Eye Q II sensor and wait
for 6 seconds.
Step 6) Confirm that “ok” pop up. If change is not seen,
replace Eye Q II sensor.
4.5.2. RF emitter inspection

(1) Start 3D pattern inspection
<IR Emitter inspection>
<IR Tester Lamp turned off(NG)> <IR Tester Lamp turned on(OK)>
(2) If RF emitter signal is correctly received to RF receiver, the

lamp of RF tester turn on.
4.6. Option selection per country 6. USB S/W download(option, service only)
(1) Overview 1) Put the USB Stick to the USB socket.
- Option selection is only done for models in Non-EU. 2) Automatically detecting update file in USB Stick
- Applied model: LD12P Chassis applied EU model. - If your downloaded program version in USB Stick is Low,
it didn’t work. But your downloaded version is High, USB
(2) Method data is automatically detecting.
1) Press ADJ key on the Adjustment Remote Control, then 3) Show the message “Copying files from memory”.
select Country Group Menu.
2) Depending on destination, select Country Group Code
04 or Country Group EU then on the lower Country
option, select US, CA, MX. Selection is done using +, -
or GF key.
5. Tool Option selection

- Method : Press ADJ key on the Adjustment remote control,
then select Tool option.
5.1. Ship-out mode check(In-stop)

After final inspection, press IN-STOP key of the Adjustment
remote control and check that the unit goes to Stand-by mode.
4) Updating is starting.
5.2. GND and Internal Pressure check
5.2.1. Method
1) GND & Internal Pressure auto-check preparation
- Check that Power Cord is fully inserted to the SET.
(If loose, re-insert)
2) Perform GND & Internal Pressure auto-check
- Unit fully inserted Power cord, Antenna cable and A/V
arrive to the auto-check process.
- Connect D-terminal to AV JACK TESTER.
- Auto CONTROLLER(GWS103-4) ON
5) Updating Completed, the TV will restart automatically.
- Perform GND TEST.
6) If your TV is turned on, check your updated version and
- If NG, Buzzer will sound to inform the operator.
Tool option. (explain the Tool option, next stage)
- If OK, changeover to I/P check automatically.
* If downloading version is more high than your TV have,
(Remove CORD, A/V form AV JACK BOX.)
TV can lost all channel data. In this case, you have to
- Perform I/P test.
channel recover. if all channel data is cleared, you didn’t
- If NG, Buzzer will sound to inform the operator.
have a DTV/ATV test on production line.
- If OK, Good lamp will lit up and the stopper will allow the
pallet to move on to next process.
* After downloading, have to adjust TOOL OPTION again.
1) Push “IN-START” key in service remote control.
5.2.2. Checkpoint 2) Select “Tool Option 1” and Push “OK” key.
• TEST voltage 3) Punch in the number. (Each model has their number.)
- GND: 1.5 KV/min at 100 mA
- SIGNAL: 3 KV/min at 100 mA
• TEST time: 1 second
• TEST POINT
- GND TEST = POWER CORD GND & SIGNAL CABLE
METAL GND
- Internal Pressure TEST = POWER CORD GND & LIVE &
NEUTRAL
• LEAKAGE CURRENT: At 0.5 mArms
SYSTEM
NAND DDR3 X 16 X 2
Air/ ANALOG
CI slot Flash(8Gb) (2Gb)
Cable DEMOD
TUNER
(T/C) DIGITAL SYSTEM EEPROM X 1
DEMOD P_TS
P_TS (1Mb)
(T/C) DVB-
DIF(+/ -) T/C

CVBS(M) Demod SPI
DIGITAL
DVB-S TUNER
CVBS Flash(2Mb)
DEMOD
(S2) (S2)
TS_S/P
H/P L/R Out
51P
50Hz
USB1 LVDS.
LNB USB URSA5
Copyright © 2011 LG Electronics. Inc. All rights reserved.

41P
Side
HDMI1 (HDCP
SYSTEM
HDMI HDMI EEPROM) DDR3 X 16 X 1
HDMI2
- 17 -
HUB IC S/W (1Gb)
HDMI3
A/V1 CVBS
BCM Audio
I2S Out AMP
35230
BLOCK DIAGRAM
COMP COMP
Audio
AMP
SCART RGB In/CVBS In Out CVBS
PC- RGB Rear I2C Sub Micom

RGB,H/V
(NEC)
PC- AUDIO L/R In
I2C
OPTIC SPDIF OUT
UART
LAN Ethernet
RS-232C
LGE Internal Use Only

EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
710
700
400
910
900
521
540
AG2
530
LV2
AG1
LV1
800
810
A10
200
A5
A2
A21
120
511
510
300
Copyright LG Electronics. Inc. All rights reserved. - 18 - LGE Internal Use Only
NAND FLASH MEMORY 8Gbit 16Gbit Boot ROM Device Select - (FA4,FAD7,FAD2,FAD1) Strap Setting
+3.3V_Normal
+3.3V_Normal
+3.3V_Normal 0000: ST Micro M25P or compatible Serial Flash
IC102-*1
TH58DVG4S0ETA20 0010: 8-bit 512Mbit 512B page SLC NAND Flash devices
IC102 0100: 8-bit 128, 256Mbit 512B page SLC NAND Flash devices
TC58DVG3S0ETA00 0110: 8-bit 1Gbit 2KB page SLC NAND Flash devices
R113 R117 R122 R127 R154 R157 R160 R164 R167 R170 R175 R177 R179 R181 R183 R187 R192
10K 10K 10K 10K 1000: 8-bit 2Gbit, 4Gbit, 8Gbit 2KB page SLC NAND Flash devices 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K
NC_1 NC_26 OPT OPT 1010: 8-bit 16Gbit, 32Gbit 4KB page SLC NAND Flash devices (O) OPT OPT OPT OPT OPT OPT OPT OPT OPT OPT
1 DEV_NAND_16Gbit 48 CI_ADDR[4]
NC_1 NC_28 0001: 8-bit 8/16/32Gbit 2KB page MLC NAND Flash devices
1 NAND_8Gbit 48 NC_2 NC_25 NAND_DATA[7] 0011: 8-bit 16/32Gbit 4KB page MLC NAND Flash devices NAND_DATA[0]
2 47
NC_2 NC_27 NAND_DATA[2] 0101: 8-bit 32Gbit 8KB page MLC NAND Flash devices
2.7K
2 47 NC_3 NC_24 CI_ADDR[7]

0111: 3B dual IO Serial Flash
3 46 NAND_DATA[1] 1001: NAND_DATA[6]
NC_3 NC_26 BB dual IO Serial Flash
3 46 NC_4 NC_23 R114 R118 R123 R128 1011: fast Serail Flash > 50Mhz
4 45 10K 10K 10K 10K CI_ADDR[6]
NC_4 NC_25 NAND_DATA[0-7] OPT OPT 1100: OneNAND Flash (always 16-bit)
4 45 NC_5 I/O8 NAND_CLE
1110: Reserved
R107
5 44 NAND_DATA[4]
NC_5 I/O8 1101, 1111: Reserved
5 44 NAND_DATA[7] RY/BY2 I/O7 CI_ADDR[9]
16Gbit 6 43
R149 0 NC_6 I/O7 CI_ADDR[11]
6 43 NAND_DATA[6] RY/BY1 I/O6
7 42 CI_ADDR[12]
RY/BY I/O6
NAND_RBb 7 42 NAND_DATA[5] RE I/O5 CI_ADDR[13]
8 41
RE I/O5 CI_ADDR[8]
NAND_REb 8 41 NAND_DATA[4] CE1 NC_22
CE NC_24
9 40 NAND ECC (FA3, FA2, FALE) NAND_DATA[3]
NAND_CEb 9 40 CE2 PSL NAND_DATA[5]
16Gbit 16Gbit 10 39 +3.3V_Normal
NC_7 PSL 0
NAND_CEb2 R148 0 10 39 R151 NC_6 NC_21 R155 R158 R161 R165 R168 R171 R176 R178 R180 R182 R184 R188 R193
11 38 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K
NC_8 NC_23
C102 11 38 VCC_1 VCC_2 OPT OPT OPT
4700pF 12 37 R111 R115 R119
VCC_1 VCC_2 +3.3V_Normal 10K 10K 10K
12 37 VSS_1 VSS_2 OPT 000 = ECC disabled
C101 13 36 OPT
VSS_1 VSS_2 C104 10uF CI_ADDR[3] 001 = ECC 1-bit repair
0.1uF 13 36 NC_7 NC_20
10V 010 = ECC 4-bit BCH (O)
14 35 CI_ADDR[2]
NC_9 NC_22 011 = ECC 8-bit BCH, 27 byte spare
14 35 C103 NC_8 NC_19 NAND_ALE 100 = ECC 12-bit BCH, 27 byte spare
0.1uF 15 34
NC_10 NC_21 R112 R116 R120 101 = ECC 8-bit BCH, 16 byte spare NAND_DATA[0]:
15 34 CLE NC_18 10K 10K 10K 110, 111 = Reservedd 0: System is LITTLE endian (O) CI_ADDR[9],CI_ADDR[11],CI_ADDR[12],CI_ADDR[13]
16 33 OPT TVM Crystal oscillator bias/gain control
CLE NC_20 1: System is BIG endian
NAND_CLE 16 33 ALE I/O4 0000: 210uA
17 32
ALE I/O4 CI_ADDR[7]: 0001: 390uA
NAND_ALE 17 32 NAND_DATA[3] WE I/O3 0: Disable EDID automatic Downloading from Flash (O) 0010: 570uA
18 31
WE I/O3 1: Enable EDID automatic Downloading from Flash 0011: 730uA
NAND_WEb 18 31 NAND_DATA[2] WP I/O2 0100: 890uA (O)
19 30
WP I/O2 NAND_DATA[6] : 0111: 1290uA
Write Protection +3.3V_Normal 19 30 NAND_DATA[1] NC_9 I/O1 0: Disable OSC clock output on chip Pin (O) 1000: 1416uA
20 29
NC_11 I/O1 1: Enable OSC clock output on chip pin. 1111: 2196uA
- High : Normal Operation 20 29 NAND_DATA[0] NC_10 NC_17 DUAL COMPONENT 0101, 0110, 1001, 1010, 1011, 1100, 1101, 1110: Reserved
R103
4.7K
- Low : Write Protection 21 28

OPT
NC_12 NC_19 CI_ADDR[6]:

21 28 NC_11 NC_16 0: Host MIPS run at 500 MHz (O) CI_ADDR[8]:
NC_13 NC_18
22 27 IC102 1ST : EAN61000101 2ND : T-TH58DVG4S0ETA20 1: Host MIPS run at 250 MHz 0: RESETOUTb (in On/Off only) stay asserted until software releases them.
22 27 NC_12 NC_15 1: Fix amount of delay for de-assertion on RESETOUTb (in On/IOff only)
FLASH_WP 23 26
NC_14 NC_17 NAND_CLE: at end of RESETb pulse (O)
23 26 NC_13
24 25
NC_14 IC102-*1 0: Differential Oscillators TVM not bypassed (O)
NC_15 NC_16 1: Differential Oscillators TVM bypassed NAND_DATA[3]:
24 25 0: MIPS will boot from external flash (O)
NAND_DATA[4]: 1: MIPS will boot from ROM
0: 27MHz TVM Crystal Frequency
1: 54MHz TVM Crystal Frequency (O) NAND_DATA[5]:
0: FLASH MODE (O)
1: BSC_SLAVE(BBS) MODE
BCM_NVM_256K
IC103-*1
+3.3V_Normal
NVRAM AT24C256C-SSHL-T
A0
1 8
VCC
A1 WP
R196 2 7
IC101 10K A2 SCL
LGE35230(BCM35230KFSBG) +3.3V_Normal 3 6
RGB_DDC_SDA GND SDA

4 5
S
B
D
NON_BCM_CAP
B5 AE27 BCM_NVM_1M
HDMI_CLK- HDMI0_CLKN TXOUT0_L0N TXB4P Q101 IC101
4.7K
4.7K
IC103 +3.3V_Normal
OPT
R173
R174
C5 AE28
HDMI_CLK+ HDMI0_CLKP TXOUT0_L0P TXB4N BSS83 LGE35230(BCM35230KFSBG) M24M01-HRMN6TP
G
AF27
TXOUT0_L1N TXB3P NAND_DATA[0-7]
A4 AF28
HDMI_RX0- HDMI0_D0N TXOUT0_L1P TXB3N C118 NC VCC
B4 AG27 NON_BCM_CAP 1 8 Write Protection
HDMI_RX0+ HDMI0_D0P TXOUT0_L2N TXBCLKP 0.1uF AG6 AB1 NAND_DATA[7]
AG28 16V 54MHz_XTAL_P TVM_XTALIN FAD_7 R169
TXOUT0_L2P TXBCLKN AB3 NAND_DATA[6] 0 E1 WP - Low : Normal Operation
+3.3V_Normal A3 AE26 FAD_6 2 7
HDMI_RX1- HDMI0_D1N TXCLK_LN TXB2P AF6 AC1 NAND_DATA[5] A8’h - High : Write Protection
B3 AF26 54MHz_XTAL_N TVM_XTALOUT FAD_5
HDMI_RX1+ HDMI0_D1P TXCLK_LP TXB2N AC2 NAND_DATA[4] E2 SCL
AH27 +3.3V_Normal FAD_4 3 6 R190 33
TXB1P AC3 SCL3_3.3V
TXOUT0_L3N
4.7K
NAND_DATA[3]
OPT
R172
A2 AG26 FAD_3
R101 R105 R104 R195 HDMI_RX2- HDMI0_D2N TXOUT0_L3P TXB1N V5 AD2 NAND_DATA[2] VSS SDA
B2 AF25 LNB_INT IRRXDA FAD_2 4 5 R191 33
4.7K 4.7K 4.7K 4.7K HDMI_RX2+ TXB0P AD3 SDA3_3.3V
HDMI0_D2P TXOUT0_L4N NAND_DATA[1]
AE25 R198 FAD_1
TXOUT0_L4P TXB0N 10K AE2 NAND_DATA[0]
FAD_0
AB4
W2 FP_IN0
CEC RGB_DDC_SCL Y4
AH26
S
B
D
FP_IN1
TXOUT0_U0N TXA4P AG1
V4 AG25 FALE NAND_ALE
DDC0_SCL TXOUT0_U0P TXA4N Q102 AA4 AF1
W4 AE24 SPARE_ADC1 FCEB_0 NAND_CEb
DDC0_SDA TXOUT0_U1N TXA3P BSS83 Y5 AC5
AD24 SPARE_ADC2 FCEB_1 NAND_CEb2 X101-*2
G
TXOUT0_U1P TXA3N AE6

V3
V2
HDMI0_HTPLG_IN TXOUT0_U2N
AH25
AF24
TXACLKP
TXACLKN
C119 SC_ID
AB2
FS_IN1
FCEB_2
FCEB_3
AG5
/CI_CE1
/CI_CE2
54MHz X-TAL X-TAL_1
1
54MHz
4
GND_2
HDMI0_HTPLG_OUT TXOUT0_U2P 0.1uF AB5 GND_1 X-TAL_2

AE23 16V FS_IN2
TXCLK_UN TXA2P 2 3
D13 AD23 C113
HDMI_ARC HDMI0_ARC TXCLK_UP TXA2N AF3 12pF CRYSTAL_BCM_KDS
E6 AG24 NFWPB FLASH_WP R185 0 EAW58239604
HDMI0_RESREF TXOUT0_U3N TXA1P U3 AG2 54MHz_XTAL_N
AF23 VGA_SDA FWE NAND_WEb DAISHINKU CORPORATION.
TXA1N +3.3V_Normal U2 AE3 50V
R106 TXOUT0_U3P 3 2
AC22 VGA_SCL FRD NAND_REb X-TAL_2 GND_1 X101-*1
3K TXOUT0_U4N TXA0P AA5 R189 54MHz
AD22 FRDYB /PCM_WAIT 4 1 X-TAL_1 GND_2
TXOUT0_U4P TXA0N GND_2 X-TAL_1 1M
1 4
Y2 54MHz OPT
BCM_RX RDA X101 GND_1 X-TAL_2
BBS CONNECT R121 R126 R129 R131 Y1 AF2 R186 0 2 3
CI_ADDR[2-14] 54MHz_XTAL_P
AG23 1.2K 1.2K 1.2K 1.2K BCM_TX TDA FA_0 NAND_CLE C114 CRYSTAL_BCM_Sunny
TXOUT1_L0N TXD4P +3.3V_Normal AE1 12pF CRYSTAL_BCM_Lihom
AH23 P101 FA_1 NAND_RBb EAW58812611 EAW60763703
TXD4N 33 AA3 AC4 50V
TXOUT1_L0P SDA0_3.3V R135 CI_ADDR[2] SUNNY ELECTRONICS CORPORATION LIHOM CO., LTD.
AE22 TJC2508-4A BSCDATAA FA_2
TXOUT1_L1N TXD3P R136 33 AA2 AD5 CI_ADDR[3]
AE21 SCL0_3.3V BSCCLKA FA_3
TXOUT1_L1P TXD3N AD4 CI_ADDR[4]
AF22 FA_4
TXOUT1_L2N TXDCLKP VCC H3 AE4 CI_ADDR[5]
AH22 1 SCL2_3.3V RDB/GPIO FA_5
TXOUT1_L2P TXDCLKN C106 R109 R110 H2 AE5 CI_ADDR[6]
AG22 1.5K 1.5K SDA2_3.3V TDB/GPIO FA_6
TXCLK1_LN TXD2P 4.7uF AD6
AF21 CI_ADDR[7]
SCL R199 22 FA_7
TXCLK1_LP TXD2N 2 H4 AH3 CI_ADDR[8]
AG21 R197 22 BSC_S_SCL FA_8
TXOUT1_L3N TXD1P H5 AF4 CI_ADDR[9]
AF20 BSC_S_SDA FA_9
TXOUT1_L3P TXD1N SDA AH4 CI_ADDR[10]
AD21 3 +3.3V_Normal FA_10
TXOUT1_L4N TXD0P C107 C108 C109 C110 AG4 CI_ADDR[11]
AC21 33pF 33pF 33pF 33pF FA_11
TXOUT1_L4P TXD0N R141 4.7K F25 AF5 CI_ADDR[12]
GND 50V 50V 50V 50V NMIB FA_12
4 DVB_S DVB_S AG3 CI_ADDR[13] +3.3V_Normal
FA_13
W5 AH2 CI_ADDR[14]
AG20 DVB_S Option: apply EU Satellite model PCM_5V_CTL POWER_CTRL FA_14
TXOUT1_U0N TXC4P AH5
AH20 5V_HDMI_1 OPT FA_15
TXOUT1_U0P TXC4N R142 22 U5 R146 10K R147 R150 R153 R156 R159 R162 R166
AD19 AON_HSYNC 1K 1K 1K 1K 1K 1K 1K
TXOUT1_U1N TXC3P 5V_HDMI_2 U4
AE19 R143 22
AON_VSYNC
TXOUT1_U1P TXC3N OPT AD15
AF19 FOR HDMI STANDARD 5V_HDMI_3 TRSTB
TXOUT1_U2N TXCCLKP APPLY ONLY WHEN CONNECT TO PULL-UP GPIO OPT W3 AF14
AH19 R144 22
AON_GPIO_36 TDI/GPIO
TXOUT1_U2P TXCCLKN R130 5V_HDMI_4 R145 22 W1 AH14
AE18 OPT 2K AON_GPIO_37 TDO R163
TXCLK1_UN TXC2P OPT AD14 1K
AD18 +3.3V_Normal TMS/GPIO
TXCLK1_UP TXC2N AB6 AG14
AG19 AON_RESETOUTB TCK/GPIO
TXOUT1_U3N TXC1P R132 4.7K Y6 AC16
AF18 TVM_BYPASS DINT/GPIO L/R_SYNC_DINT
TXOUT1_U3P TXC1N
AG18 R139 0 L/R_SYNC_DINT
TXOUT1_U4N TXC0P SRST
AF17
TXOUT1_U4P TXC0N +3.3V_Normal +3.3V_Normal Y3 AH7
SOC_RESET RESETB AVS_VFB For L/R sync GPIO
G24 AG7
RESETOUTB AVS_VSENSE
AD7 SRST
AC18 R194 R124 AVS_RESETB
LT0VCAL_MONITOR 2.7K 1K J6 AF7
AH16 OPT TMODE AVS_NDRIVE_1
GPIO_BL_ON W6 AH8
AG16 R108 10K TESTEN AVS_PDRIVE_1
BL_PWM/GPIO A_DIM +3.3V_Normal
R125
C105 1K
2.2uF C111 0.01uF F7 C6
10V VDAC_VREG VDAC_1 DTV/MNT_V_OUT
E7 D7
C112 0.1uF VDAC_RBIAS VDAC_2
R140
560
1%
BCM REFRENCE is 562ohm
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM35230 2010.09.18
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN & NAND FLASH 1
Copyright © 2011 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
POWER 2.5V
+2.5V_BCM35230 ADAC_AVDD25 CORE 0.9V
+2.5V_BCM35230 AADC_AVDD25
+0.9V_CORE HDMI_AVDD +0.9V_CORE USB_AVDD +0.9V_CORE VAFE2_DVDD
L202 L205 L209
BLM18PG121SN1D BLM18PG121SN1D L214 L219
+3.3V_Normal
BLM18PG121SN1D BLM18PG121SN1D BLM18PG121SN1D
+0.9V_CORE +0.9V_CORE
NFM18PS105R0J NFM18PS105R0J C249 C253 C256 C258
C233 C204 10uF 10uF 0.1uF 0.1uF C280 C284 C285 C288 C292 C296 C299
C261 C263 C267 C271 C274 22uF 22uF 4.7uF 0.1uF
6.3V 6.3V 10V 10V 10uF 4.7uF 0.1uF 0.01uF 22uF 0.1uF 4.7uF 0.1uF
C225 C221 C223 C247 10V
BCM_FRC/URSA5
0.22uF 0.1uF 0.01uF IN OUT IN OUT 22uF

6.3V
S_TUNER
T2_TUNER
FRC2/URSA5
GND GND
R254
R256
R257
R253
R255
PHM
R251
R252
OLED
R250
FHD
1K
1K
1K
1K
1K
1K
1K
1K
+2.5V_BCM35230 EPHY_VDD25 +2.5V_BCM35230

+0.9V_CORE PLL_AUD_AVDD +0.9V_CORE VAFE3_DVDD +0.9V_CORE PLL_MAIN_AVDD
L203
BLM18PG121SN1D L210 L215 L217
NFM18PS105R0J +3.3V_Normal BLM18PG121SN1D BLM18PG121SN1D BLM18PG121SN1D
MODEL_OPT_0 C244 C259 C260 C262 C266 C270 C272
6.3V C251 C252 C255
0.1uF 4.7uF 0.1uF 10uF 4.7uF 10uF 4.7uF 0.1uF 0.01uF C277 C281 C294 C297
MODEL_OPT_1 16V 10V 10V 4.7uF 0.1uF C287 C290 4.7uF 0.1uF
C232 C234 C236 C238 IN OUT C248 4.7uF 0.1uF
MODEL_OPT_2 4.7uF 0.1uF 0.1uF 4.7uF 10uF
10V 10V GND 10V
MODEL_OPT_3
MODEL_OPT_4
+2.5V_BCM35230 VAFE2_VDD25
MODEL_OPT_5 +0.9V_CORE PLL_MIPS_AVDD
L206 +0.9V_CORE PLL_VAFE_AVDD
+1.5V_DDR
MODEL_OPT_6 BLM18PG121SN1D L211 L218
BLM18PG121SN1D BLM18PG121SN1D
MODEL_OPT_7
NO_FRC/BCM_FRC
NO_FRC/FRC2
NO_T2_TUNER
NO_S_TUNNER
C295 C298
C203 C205 C207 C209 C211 C213 C215 C220 C222 C265 C269 C279 C282 4.7uF 0.1uF
NO_PHM
R260
R265
R261
10uF 10uF 4.7uF 4.7uF 0.1uF 0.1uF 0.01uF 0.1uF 0.01uF 4.7uF 0.1uF 4.7uF 0.1uF
R262
R263
R264
R266
R267
LCD
OPT
HD
10V 10V
1K
1K
10V 10V
1K
1K
1K
1K
1K
1K
+2.5V_BCM35230 VAFE3_VDD25 +2.5V_BCM35230 PLL_VAFE_AVDD25

L204 L207
BLM18PG121SN1D BLM18PG121SN1D
C254 C257 C264 C268 POWER 3.3V

C250
4.7uF 4.7uF 0.1uF 4.7uF 0.1uF
MODEL OPTION 10V +3.3V_Normal USB_AVDD33 +3.3V_Normal HDMI_AVDD33
BCM L212 L216
external
NO_FRC internal LG FRC2 BLM18PG121SN1D BLM18PG121SN1D
URSA5
FRC
C283
MODEL_OPT_0 0 0 1 1 C291 C293
0.1uF
4.7uF 0.1uF
MODEL_OPT_1 0 1 0 1
HIGH LOW IC101

+0.9V_CORE LGE35230(BCM35230KFSBG)
MODEL_OPT_2 FHD HD
+3.3V_Normal VDAC_AVDD33
MODEL_OPT_3 OLED LCD NON_BCM_CAP
L213
V12 K10 BLM18PG121SN1D
MODEL_OPT_4 DDR speed 1333 1600 VDDC_1 VSS_1
V7 K11
VDDC_2 VSS_2
MODEL_OPT_5 T2 Tuner Support Not Support M10 K12
VDDC_3 VSS_3 C286 C289
N10 L12 4.7uF 0.1uF
MODEL_OPT_6 S Tuner Support Not Support VDDC_4 VSS_4
P10 M12
VDDC_5 VSS_5
MODEL_OPT_7 PHM Enable Disable R10 N12
VDDC_6 VSS_6
T10 P12
VDDC_7 VSS_7
U10 R12
VDDC_8 VSS_8
V10 T12
close to soc VDDC_9 VSS_9
W10 U12
IC101 C217 V13
VDDC_10 VSS_10
W12
LGE35230(BCM35230KFSBG) 16V
L11
VDDC_11 VSS_11
K13
0.1uF 100
Non_CHB R241 +3.3V_Normal VDDC_12 VSS_12
M11 L13
IF_P VDDC_13 VSS_13 IC101
NON_BCM_CAP R212 L201 N11 M13
F26 C17 1K C218
100 P11
VDDC_14 VSS_14
N13
LGE35230(BCM35230KFSBG)
EPHY_VREF VI_IFP0 0.1uF R242 BLM18PG121SN1D
D26 B17 16V VDDC_15 VSS_15 AADC_AVDD25
EPHY_RDAC VI_IFM0 IF_N R11 P13
R211 D15 VDDC_16 VSS_16 NON_BCM_CAP
VDDR_AGC +3.3V_Normal T11 R13
6.04K F27 VDDC_17 VSS_17 F19 F20
EPHY_TDP EPHY_TDP C229 U11 T13 AADC_AVDD25 AADC_AVSS
F28 B16 closed to soc VDDC_18 VSS_18 ADAC_AVDD25
0.1uF V11 U13
EPHY_TDN EPHY_TDN AGC_SDM_2
E27 A16 R213 2K VDDC_19 VSS_19 D25 G22
EPHY_RDP EPHY_RDP AGC_SDM_1 IF_AGC R233 R234 W11 W16 ADACA_AVDD25 ADACA_AVSS
E26 C216 0.01uF 1.2K 1.2K VDDC_20 VSS_20 D24 G21
EPHY_RDN EPHY_RDN V14 K14 ADACC_AVDD25 ADACC_AVSS
A15 VDDC_21 VSS_21 E24 F22
GPIO_0 SDA1_3.3V L18 L14 ADACD_AVDD25 ADACD_AVSS
C16 VDDC_22 VSS_22 EPHY_VDD25
GPIO_1 SCL1_3.3V M18 M14
F5 G28 VDDC_23 VSS_23 F24 F23
USB_MONCDR GPIO_2 3D_SYNC C227 C231 N18 N14 EPHY_BVDD25 EPHY_AVSS
+3.3V_Normal E5 G26 33pF 33pF NON_NTP VDDC_24 VSS_24 E25
USB_RREF GPIO_3 NON_NTP P18 P14 EPHY_AVDD25
C201 R210 50V 50V VDDC_25 VSS_25
100pF 4.87K +3.3V_Normal R18 R14
1% C2 VDDC_26 VSS_26 HDMI_AVDD
OPT SIDE_USB_DM USB_PORT1DN T18 T14
R287 D1 W14 VDDC_27 VSS_27
10K SIDE_USB_DP USB_PORT1DP PCI_VIO_0 U18 U14 HDMI_AVDD33
W15 VDDC_28 VSS_28 D5 F6
WIFI PCI_VIO_1 V18 K15 HDMI0_AVDD HDMI0_AVSS_1
E1 W13 VDDC_29 VSS_29 D4 G6
SIDE_USB_OCD1 USB_PWRFLT_1/GPIO PCI_VIO_2 W18 L15 +2.5V_BCM35230 HDMI0_AVDD33 HDMI0_AVSS_2
D2 VDDC_30 VSS_30
SIDE_USB_CTL1 USB_PWRON_1/GPIO V15 M15
VDDC_31 VSS_31 AE20 AB22
R286 L19 N15 LT0VDD25_1 LT0VSS_1
10K B1 J5 R280 VDDC_32 VSS_32 AD20 AB21
WIFI_DM USB_PORT2DN GPIO_4 M_REMOTE_RX M19 P15 LT0VDD25_2 LT0VSS_2
WIFI C1 R5 22 VDDC_33 VSS_33 AC20 AB19
WIFI_DP USB_PORT2DP GPIO_5 MODEL_OPT_0 N19 R15 +2.5V_BCM35230 LT0VDD25_3 LT0VSS_3
V6 VDDC_34 VSS_34 AB20 AC19
GPIO_6 CI_DET P19 T15 LT0VDD25_4 LT0VSS_4
C3 H6 VDDC_35 VSS_35 AB18
SIDE_USB_OCD2 USB_PWRFLT_2/GPIO GPIO_7 M_RFModule_RESET R19 U15 LT0VSS_5
C4 AE15 VDDC_36 VSS_36 C275 AB17
SIDE_USB_CTL2 USB_PWRON_2/GPIO GPIO_70 EPHY_ACTIVITY T19 K16 LT0VSS_6
AF15 VDDC_37 VSS_37 0.1uF AC17
GPIO_71 EPHY_LINK U19 L16 OPT LT0VSS_7
PCM_TS_DATA[0-7] AG15 R214 22 +3.3V_Normal VDDC_38 VSS_38
GPIO_72 DTV_ATV_SELECT V19 M16
M4 AF16 R215 22 VDDC_39 VSS_39 USB_AVDD D14 SPDIF_IN_AVDD25 F15
PCM_TS_CLK TCLKA/GPIO GPIO_73 RF_SWITCH_CTL_2 +1.5V_DDR W19 N16
L5 AD16 R281 22 VDDC_40 VSS_40 SPDIF_IN_AVSS
PCM_TS_DATA[0] R240 V16 P16
TDATA_0/GPIO GPIO_74 MODEL_OPT_1 USB_AVDD33
PCM_TS_DATA[1] M5 AE16 R282 22 2.7K VDDC_41 VSS_41 E4 G7
TDATA_1/GPIO GPIO_75 MODEL_OPT_2 V17 R16 USB_AVDD USB_AVSS_1
PCM_TS_DATA[2] L6 AG17 R216 22 Place Cap VDDC_42 VSS_42 VDAC_AVDD33 D3 G8
TDATA_2/GPIO GPIO_76 MODEL_OPT_3 Very close to R22 Ball T16 USB_AVDD33 USB_AVSS_2
PCM_TS_DATA[3] N3 AH17 R228 22 VSS_43
TDATA_3/GPIO GPIO_77 PWM_DIM L10 U16
PCM_TS_DATA[4] N1 AE17 R230 22 MLG1005S22NJT POR_VDD VSS_44 VAFE2_DVDD D6 G9
TDATA_4/GPIO GPIO_78 L/DIM0_VS K17 VDAC_AVDD33 VDAC_AVSS
PCM_TS_DATA[5] N2 AD17 BCM_L/DIM C224 C226 VSS_45 VAFE2_VDD25
OPT TDATA_5/GPIO GPIO_79 INSTANT_MODE L220 L17
R201 0 PCM_TS_DATA[6] M3 1uF 0.1uF VSS_46 D18 G20
TDATA_6/GPIO L22 M17 VAFE2_DVDD VAFE2_VSS_1
M2 25V 16V VDDR1_1 VSS_47 E17 E18
PCM_TS_DATA[7] OPT OPT AA28 N17
TDATA_7/GPIO Place as close as possible to the pad VAFE2_AVDD25_1 VAFE2_VSS_2
L4 AB13 +3.3V_Normal VDDR1_2 VSS_48 C212 C214 D16 G18
PCM_TS_SYNC TSTRTA/GPIO PCI_AD05 V28 P17 VAFE2_AVDD25_2 VAFE2_VSS_3
N4 AC15 VDDR1_3 VSS_49 VAFE3_DVDD 390pF 390pF D17 G17
R28 R17
URSA_RESET
FRC2_RESET
PCM_TS_VAL TVLDA/GPIO PCI_AD06 50V 50V VAFE2_DVDD25 VAFE2_VSS_4

AB12 VDDR1_4 VSS_50 F18
R232-*1
FE_TS_DATA[0-7] F/NIM_EU_CN PCI_AD07 M28 T17 VAFE3_VDD25 VAFE2_VSS_5

R202 K6 AB11 VDDR1_5 VSS_51 D9 G16
J28 U17
4.7K
TU_TS_CLK
4.7K
R232
0 TCLKD/GPIO PCI_AD08 VAFE3_DVDD VAFE2_VSS_6

FE_TS_DATA[0] J4 AE14 R231-*1 0 VDDR1_6 VSS_52 D8 F16
TDATD_0/GPIO PCI_AD09/GPIO SC_DET/COMP2_DET K23 W17 VAFE3_AVDD25_1 VAFE2_VSS_7
FE_TS_DATA[1] R203 0 F/NIM_EU_CN K5 AG13 VDDR1_7 VSS_53 E8
TDATD_1/GPIO PCI_AD10/GPIO CHB_RESET FRC2_RESET M22 K18 C208 C210 VAFE3_AVDD25_2
F/NIM_EU_CN J2 AH13 VDDR1_8 VSS_54 use only for A0/B0 chip F9 G13
FE_TS_DATA[2] R204 0 R231 100 FRC_RESET T22 K19 390pF 390pF
TDATD_2/GPIO PCI_AD11/GPIO VAFE3_AVDD25_3 VAFE3_VSS_1
FE_TS_DATA[3] R205 0 F/NIM_EU_CN J3 AF13 VDDR1_9 VSS_55 C210-*1 50V 50V E9 G12
TDATD_3/GPIO PCI_AD12/GPIO TW9910_RESET URSA_RESET T23 H7 VAFE3_DVDD25 VAFE3_VSS_2
VDDR1_10 VSS_56 220pF BCM_C0
FE_TS_DATA[4] R206 0 F/NIM_EU_CN K2 AE13 F8 F12
TDATD_4/GPIO PCI_AD13/GPIO AV2_CVBS_DET Place Cap U22 G14 50V POR_VDD25 VAFE3_VSS_3
FE_TS_DATA[5] R207 0 F/NIM_EU_CN K1 AD12 R218 22 Very close to R22 Ball VDDR1_11 VSS_57 PLL_AUD_AVDD G11
TDATD_5/GPIO PCI_AD14/GPIO RF_BOOSTER_CTL Y22 AB16 BCM_A0/B0 VAFE3_VSS_4
F/NIM_EU_CN K3 AF12 VDDR1_12 VSS_58 Place as close as possible to the pad G10
FE_TS_DATA[6] R208 0 DSUB_DET C242 R7 PLL_MAIN_AVDD
TDATD_6/GPIO PCI_AD15/GPIO VAFE3_VSS_5
FE_TS_DATA[7] R209 0 F/NIM_EU_CN L1 AG10 0.1uF VSS_59 G25 F10
TDATD_7/GPIO PCI_AD16/GPIO PCM_RST R22 M6 PLL_AUD_AVDD VAFE3_VSS_6
CHBO_TS_CLK L3 AF10 DDR_LDO_VDDO VSS_60 PLL_MIPS_AVDD K4
TU_TS_SYNC R220 22 MODEL_OPT_4 AB23 PLL_VAFE_AVDD
CHBO_TS_SERIAL TSTRTD/GPIO PCI_AD17/GPIO PLL_MAIN_AVDD
L2 AE10 +3.3V_Normal VSS_61 AD25
TS_VAL_ERR TVLDD/GPIO PCI_AD18/GPIO DC_MREMOTE P7 PLL_MIPS_AVDD
CHBO_TS_SYNC AD10 VSS_62 PLL_VAFE_AVDD25 D11 AD26
PCI_AD19/GPIO DD_MREMOTE G15 W7 PLL_MIPS_AVSS
CHBO_TS_VAL_ERR AE9 VDDR3_1 VSS_63 D12 PLL_VAFE_AVDD
PCM_MDI[0-7] R221 22 BCM_L/DIM L/DIM0_MOSI H22 J7
PCI_AD20/GPIO +0.9V_CORE PLL_VAFE_AVDD25
P4 AE8 R222 22 BCM_L/DIM VDDR3_2 VSS_64
PCM_MCLKI MPEG_CLK/GPIO PCI_AD21/GPIO L/DIM0_SCLK G23 N7
PCM_MDI[0] T2 AC10 VDDR3_3 VSS_65 AE7 AC7
MPEG_D_0/GPIO PCI_AD22 AB9 AB10 TVM_OSC_AVDD TVM_OSC_AVSS
PCM_MDI[1] R3 AC11 VDDR3_4 VSS_66 C273
MPEG_D_1/GPIO PCI_AD23 K7 AC23 C276 +3.3V_Normal
PCM_MDI[2] R2 AC8 VDDR3_5 VSS_67 C202 C206 0.1uF 0.01uF U6
MPEG_D_2/GPIO PCI_AD24 AB15 AC6 AUX_AVDD33
P3 AB8 VDDR3_6 VSS_68 390pF 390pF OPT
PCM_MDI[3] L7 G19 50V 50V
MPEG_D_3/GPIO PCI_AD25
PCM_MDI[4] P2 VDDR3_7 VSS_69
MPEG_D_4/GPIO AB14 AA22
PCM_MDI[5] P1 AC14 VDDR3_8 VSS_70 C278
MPEG_D_5/GPIO PCI_CBE00 M7 J23
R6 AG12 VDDR3_9 VSS_71 0.1uF
PCM_MDI[6] R283 COMP1_DET N6 J22
MPEG_D_6/GPIO PCI_CBE01/GPIO 22
PCM_MDI[7] N5 AH10 VDDR3_10 VSS_72
MPEG_D_7/GPIO PCI_CBE02/GPIO MODEL_OPT_5 P6 K22
T4 AB7 VDDR3_11 VSS_73
PCM_MISTRT MPEG_SYNC/GPIO PCI_CBE03 +0.9V_CORE J25 Place as close as possible to the pad
P5 VSS_74
PCM_MIVAL_ERR MPEG_DATA_EN/GPIO N22
AG11 R223 22 VSS_75
PCI_DEVSELB/GPIO 3D_GPIO_0 +3.3V_Normal AA6 N23
AD11 R284 22 AON_VDDC_1 VSS_76
PCI_FRAMEB/GPIO MODEL_OPT_6 AA7 M25
R4 AE11 R224 22 AON_VDDC_2 VSS_77
MCIF_RESET/GPIO PCI_IRDYB/GPIO MODEL_OPT_7 Y7 P22
U1 AD13 AON_POR_VDD VSS_78
MCIF_SCLK/GPIO PCI_PAR/GPIO R25
T3 AE12 R235 100 VSS_79
MCIF_SCTL/GPIO PCI_PERRB/GPIO ERROR_OUT U7 V22
T1 AC12 R225 0 OPT AON_VDDR3 VSS_80
/PCM_IRQA MCIF_SDI/GPIO PCI_REQ1B W22
T5 AC13 R226 22 VSS_81
MCIF_SDO/GPIO PCI_SERRB/GPIO RF_SWITCH_CTL T7 W23
AH11 R285 22 AON_VDDR10_1 VSS_82
PCI_STOPB/GPIO 3D_GPIO_1 T6 V25
AF11 R227 22 AON_VDDR10_2 VSS_83
PCI_TRDYB/GPIO 3D_GPIO_2 AA25
VSS_84

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM35230
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN POWER 2 50
DSUB_R+ C320 0.1uF
INCM_R C321 0.1uF
R311
36 IC101
DSUB_G+ C327 0.1uF
C328 0.1uF NON_BCM_CAP
INCM_G B6
R317 VI_R
36 A6
VI_INCM_R
C7
VI_G
A7
DSUB_B+ C322 0.1uF B7

C8
VI_INCM_G
VI_B
BCM35230_with_CAP_220pF
INCM_B C323 0.1uF
VI_INCM_B
R312 IC101-*1
36 C13
DSUB_HSYNC HSYNC_IN
LGE35230
A13
DSUB_VSYNC VSYNC_IN
COMP1_Y
C9
COMP1_Pr C329
C330
0.1uF
0.1uF A9
VI_Y1 VIDEO INCM B6
BCM_CAP
A6
VI_R
COMP1_Pb VI_PR1
B9 VI_INCM_R
C331 0.1uF C7
VI_PB1 VI_G
C332 0.1uF B8 A7
VI_INCM_COMP1 VI_INCM_G
B7
Run Along DSUB_R Trace VI_B
C333 0.1uF C11 Near P801 INCM_R C8
VI_SC_R1 VI_INCM_B
C334 0.1uF A10
VI_SC_G1 Run Along DSUB_G Trace
C335 0.1uF B10 Near P801 INCM_G C13
VI_SC_B1 HSYNC_IN
C336 0.1uF C10 A13
VI_INCM_SC1 Run Along DSUB_B Trace VSYNC_IN
INCM_VID_COMP1 Near P801 INCM_B
R310 D10
0 SC_FB C9
VI_FB_1/GPIO Run Along COMP_Y_IN,COMP_Pr_IN,COMP_Pb_IN Trace VI_Y1
F13 Near JK1101 INCM_VID_COMP1 A9
VI_FS1 VI_PR1
B9
Run Along AV2_CVBS Trace VI_PB1
A12 Near JK1104 INCM_VID_AV2 B8
SC_R/COMP2_Pr VI_SC_R2 VI_INCM_COMP1
C12
SC_G/COMP2_Y VI_SC_G2 Run Along TUNER_CVBS_IF_P Trace
B12 Near TU2101/2
TU2201/2/3
INCM_TUNER C11
SC_B/COMP2_Pb VI_SC_B2 VI_SC_R1
B11 A10
VI_INCM_SC2 Run Along AV1_CVBS Trace VI_SC_G1
Near JK1102 INCM_VID_AV1 B10
E12 VI_SC_B1
JK1103 Run Along COMP_Y_IN,COMP_Pr_IN,COMP_Pb_IN/SC R,G,B Trace C10
VI_FB_2/GPIO Near INCM_VID_SC/COMP2 VI_INCM_SC1
E14 JK2501
VI_FS2
D10
E15 VI_FB_1/GPIO
F13
INCM_VID_SC/COMP2 VI_L1 VI_FS1
R318 F17
0 VI_C1_1
E16 A12
VI_INCM_LC1_1 VI_SC_R2
SC_CVBS_IN F14 C12
VI_C1_2 VI_SC_G2
INCM_VID_SC E11 B12
C303 0.1uF VI_INCM_LC1_2 VI_SC_B2
AV2_CVBS_IN B11
INCM_VID_AV2 C304 0.1uF C18 VI_INCM_SC2
NON_EU VI_CVBS1
R303 R325 0 B18
36 TU_CVBS C325 0.1uF E12
VI_INCM_CVBS1 VI_FB_2/GPIO
C326 0.1uF A18 E14
EU INCM_TUNER VI_CVBS2 VI_FS2
R306 R316 C19
R325-*1 VI_INCM_CVBS2
75 36 A19
10 1% E15
OPT VI_CVBS3 VI_L1
B19 F17
VI_INCM_CVBS3 VI_C1_1
C317 0.1uF C20 E16
AV1_CVBS_IN VI_CVBS4 VI_INCM_LC1_1
C318 0.1uF B20 F14
INCM_VID_AV1 VI_INCM_CVBS4 VI_C1_2
R304 +2.5V_BCM35230 E11
36 E19 VI_INCM_LC1_2
VI_SIF1_1
D19 C18
R313 VI_INCM_SIF1_1 VI_CVBS1
10K E10 B18
VI_SIF1_2 VI_INCM_CVBS1
C319 0.1uF F11 A18
TU_SIF VI_INCM_SIF1_2 VI_CVBS2
C19
R305 R314 +2.5V_BCM35230 VI_INCM_CVBS2
240 12K A19
OPT VI_CVBS3
B19
R319 VI_INCM_CVBS3
10K C20
OPT VI_CVBS4
B20
C324 0.1uF VI_INCM_CVBS4
INCM_SIF
R315 R320 E19
120 12K VI_SIF1_1
OPT OPT D19
VI_INCM_SIF1_1
E10
VI_SIF1_2
F11
VI_INCM_SIF1_2
IC101
NON_BCM_CAP
B15 AF8 R326 100
SPDIF_INC_P I2SSCK_OUTA/GPIO AUD_SCK
C15 AF9 R327 100
+3.3V_Normal SPDIF_INC_N I2SWS_OUTA/GPIO AUD_LRCK
AG9 R328 100
I2SSD_OUTA0/GPIO AUD_LRCH
C14 AC9 R329 100
SPDIF_IND_P I2SSOSCK_OUTA/GPIO AUD_MASTER_CLK
B14 AD8
SPDIF_IND_N I2SSD_OUTA1/GPIO TU_RESET_SUB C337 C338 C339 C340
R301 R302 AD9 22pF 22pF
I2SSD_OUTA2/GPIO 22pF 33pF
1.2K 1.2K G4
M_REMOTE_TX OPT OPT OPT OPT
I2SSCK_IN/GPIO
F4 E2
SCL3_3.3V I2SWS_IN I2SSCK_OUTC/GPIO HP_DET
G5 F2
SDA3_3.3V I2SSD_IN/GPIO I2SWS_OUTC/GPIO AV1_CVBS_DET
C301 C302 E3
I2SSD_OUTC/GPIO TU_RESET
33pF 33pF F3
50V 50V I2SSOSCK_OUTC/GPIO
C305 1uF 10V C25
PC_L_IN AADC_LINE_L1
C306 1uF 10V B24 G2
PC_R_IN AADC_LINE_R1 I2SSCK_OUTD/GPIO SC_RE1
C307 1uF 10V A24 G3
INCM_AUD_PC AADC_INCM1 I2SWS_OUTD/GPIO SC_RE2
I2SSD_OUTD/GPIO
G1
/RST_HUB AUDIO INCM
C308 1uF 10V E22 H1
PHONE JACK AV1_L_IN AADC_LINE_L2 I2SSOSCK_OUTD/GPIO S2_RESET
C309 1uF 10V E23
AV1_R_IN AADC_LINE_R2
C310 1uF 10V D23
INCM_AUD_AV1 AADC_INCM2
B13 Route Between AV1_L_IN & AV1_R_IN Trace
C24
SPDIF_OUTA/GPIO SPDIF_OUT Near JK1102 R321 0 INCM_AUD_AV1
AV2_L_IN C311 1uF 10V
AADC_LINE_L3
C312 1uF 10V C23 AG8 Route Between SC/COMP2_L_IN & SC/COMP2_R_IN Trace
AV2_R_IN AADC_LINE_R3 AUDMUTE_0/GPIO Near JK1103 R322 0
B23 E13 INCM_AUD_SC/COMP2
C313 1uF 10V JK2501
INCM_AUD_AV2 AADC_INCM3 AUDMUTE_1
R323 0 Route Between AV2_L_IN & AV2_R_IN Trace
E21 C28 Near JK1104 INCM_AUD_AV2
SC/COMP2_L_IN C314 1uF 10V HP_LOUT_N
AADC_LINE_L4 ADAC_AL_N
C315 1uF 10V D21 C27 Route Between PC_L_IN & PC_R_IN Trace
SC/COMP2_R_IN
D22
AADC_LINE_R4 ADAC_AL_P HP_LOUT_P Near JK801 R324 0 INCM_AUD_PC
INCM_AUD_SC/COMP2 C316 1uF 10V
AADC_INCM4
D28
ADAC_AR_N HP_ROUT_N
B22 D27
AADC_LINE_L5 ADAC_AR_P HP_ROUT_P
C22
AADC_LINE_R5
A22 C26
AADC_INCM5 ADAC_CL_N SCART1_Lout_N Near TU2101/2
TU2201/2/3
Route Along With TUNER_SIF_IF_N
INCM_SIF
A27
ADAC_CL_P SCART1_Lout_P
F21
AADC_LINE_L6
D20 B27
AADC_LINE_R6 ADAC_CR_N SCART1_Rout_N
E20 B28
AADC_INCM6 ADAC_CR_P SCART1_Rout_P
A21 B25
AADC_LINE_L7 ADAC_DL_N
C21 A25
AADC_LINE_R7 ADAC_DL_P
B21
AADC_INCM7
A26
ADAC_DR_N
B26
ADAC_DR_P

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN AUDIO/VIDEO 3 50
DUAL COMPONENT
IC401,IC402 1ST : EAN61667501, 2ND : EAN61570701
IC401-*1
1ST : T-K4B2G1646B_HCK0, 2ND : T-H5TQ2G63BFR-PBC
IC402-*1
DDR STRAP
DDR_DQ[0]
DDR_DQ[1]
DDR_DQ[2]
DDR_DQ[3]
DDR_DQ[4]
+1.5V_DDR +1.5V_DDR
NFM18PS105R0J
NFM18PS105R0J
JEDEC Types : DDR_DQ[0:4] C410 C432
R401 R403 R405 R407 R409 6.3V 6.3V
4.7K 4.7K 4.7K 4.7K 4.7K 00001 : DDR3-1333H (CasL=9)
OPT 10101 : DDR3-1600K (CasL=11) (O) C403 C405 C407 C417 C421 C423 C425
DDR_1333 DDR_1333 IN OUT IN OUT
2.2uF 10uF 2.2uF 470pF 2.2uF 10uF 10uF
GND GND
DDR_DQ[10] +1.5V_DDR +1.5V_DDR

DDR_DQ[9] NFM18PS105R0J NFM18PS105R0J
DDR_DQ[7] C402 C433
+1.5V_DDR 6.3V 6.3V
DDR_DQ[8]
DDR_DQ[6] C412 C426
IN OUT 1uF IN OUT 1uF
DDR_DQ[5]
GND GND
R402 R432 R404 R406 R408 R410 C453 C454 C455

4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 1uF 1uF 1uF
OPT OPT OPT OPT OPT 6.3V
Bus Width : DDR_DQ[10] 6.3V 6.3V
0 - 16b
1 - 32b (O)
Chip Width : DDR_DQ[8]
0 - 8b
1 - 16b (O)
Chip Size : DDR_DQ[6:5]
00 - 4Gbit
01 - 2Gbit (O)
+1.5V_DDR
10 - 1Gbit +1.5V_DDR
11 - 512Mbit +1.5V_DDR
IC401 IC402
R422 R430
K4B2G1646C R416 K4B2G1646C 4.99K 4.7K
4.99K 1% OPT
1% R429
82
DDR_RESETb
N3 DDR_1333_SS M8 N3 DDR_1333_SS M8 R423
DDR_AA0 A0 VREFCA C415 R417 DDR_AA0 A0 VREFCA C435 4.99K C442
IC101 P7 4.99K P7 0.01uF 1% 100pF
DDR_AA1 A1 0.01uF 1% DDR_AA1 A1
LGE35230(BCM35230KFSBG) P3 P3
DDR_AA2 A2 DDR_AA2 A2 R428
N2 H1 N2 H1 82
DDR_DQ[0-7] NON_BCM_CAP DDR_AA3 A3 VREFDQ DDR_VREFA DDR_AA3 A3 VREFDQ C436 DDR_VREFA
P8 C416 P8 DDR_CKE
DDR01_AA4 A4 0.01uF DDR23_AA4 A4 0.01uF C437 R431
DDR_DQ[0] U26 V23 P2 P2 4.7K
DDR_DQA_0 DDR_ADA_0 DDR_AA0 DDR01_AA5 A5 DDR23_AA5 A5 100pF
R26 AB27 R8 L8 OPT
DDR_DQ[1] DDR_DQA_1 DDR_AA1 R8 L8 R415 240 DDR23_AA6 R421 240
DDR_ADA_1 DDR01_AA6 A6 ZQ A6 ZQ
DDR_DQ[2] U27 Y23 R2 R2 1% +1.5V_DDR
DDR_DQA_2 DDR_ADA_2 DDR_AA2 DDR_AA7 A7 1% +1.5V_DDR DDR_AA7 A7
DDR_DQ[3] R27 Y26 T8 T8
DDR_DQA_3 DDR_ADA_3 DDR_AA3 DDR_AA8 A8 DDR_AA8 A8
DDR_DQ[4] V27 R3 B2 R3 B2
DDR_DQA_4 DDR_AA9 A9 VDD_1 DDR_AA9 A9 VDD_1 DDR_AA13 R424 56
DDR_DQ[5] P26 AB26 L7 D9 L7 D9
DDR_DQA_5 DDR_ADA_4 DDR01_AA4 DDR_AA10 A10/AP VDD_2 DDR_AA10 A10/AP VDD_2 DDR_AA14 R425 56 OPT
DDR_DQ[6] U25 Y24 R7 G7 R7 G7
DDR_DQ[8-15] DDR_DQA_6 DDR_ADA_5 DDR01_AA5 DDR_AA11 A11 VDD_3 C438 1uF
P27 AC26 DDR_AA11 A11 VDD_3 N7 K2
DDR_DQ[7] DDR01_AA6 N7 K2 DDR_AA12 AR401 56
DDR_DQA_7 DDR_ADA_6 DDR_AA12 A12/BC VDD_4 A12/BC VDD_4 DDR_AA2
DDR_DQ[8] R24 T3 K8 T3 K8
DDR_DQA_8 DDR_AA13 A13 VDD_5 C404 0.1uF
N24 AB24 DDR_AA13 A13 VDD_5 N1 DDR_AA11
DDR_DQ[9] DDR23_AA4 N1
DDR_DQA_9 DDR_ADA_ALT_4 VDD_6 VDD_6 DDR_AA3
DDR_DQ[10] T25 AC25 M7 N9 M7 N9
DDR_DQA_10 DDR_ADA_ALT_5 DDR23_AA5 NC_5 VDD_7 DDR_AA7 C406 0.1uF
M23 AC24 NC_5 VDD_7 R1
DDR_DQ[11] DDR23_AA6 R1 AR402 56
DDR_DQA_11 DDR_ADA_ALT_6 VDD_8 VDD_8
DDR_DQ[12] R23 M2 R9 M2 R9
DDR_DQA_12 DDR_BAA0 BA0 VDD_9 DDR_BAA0 BA0 VDD_9 DDR_AA9
DDR_DQ[13] N25 AB25 N8 N8 C450 0.1uF
DDR_DQA_13 DDR_ADA_7 DDR_AA7 DDR_BAA1 BA1 DDR_BAA1 BA1 DDR_AA8
DDR_DQ[14] T24 AD28 M3 M3
DDR_DQ[16-23] DDR_DQA_14 DDR_ADA_8 DDR_AA8 DDR_BAA2 BA2 C408 0.1uF
N26 Y25 DDR_BAA2 BA2 A1 DDR_AA0
DDR_DQ[15] DDR_AA9 A1 AR403 56
DDR_DQA_15 DDR_ADA_9 VDDQ_1 VDDQ_1 DDR_AA1
DDR_DQ[16] L26 AA27 J7 A8 J7 A8 C439
DDR_DQA_16 DDR_ADA_10 DDR_AA10 DDR01_CLK DDR23_CLK CK VDDQ_2 DDR_BAA0 1uF
H27 AC27 CK VDDQ_2 K7 C1
DDR_DQ[17] DDR_AA11 K7 C1 DDR23_CLKb
DDR_DQA_17 DDR_ADA_11 DDR01_CLKb CK VDDQ_3 CK VDDQ_3 DDR_BAA2
DDR_DQ[18] L27 AA26 K9 C9 K9 C9
DDR_DQA_18 DDR_ADA_12 DDR_AA12 DDR_CKE R418 R419 DDR_CKE CKE VDDQ_4 DDR_BAA1 C409 0.1uF
J26 AA24 R412 R413 CKE VDDQ_4 D2
DDR_DQ[19] DDR_AA13 56 56 D2 56 56 AR404 56
DDR_DQA_19 DDR_ADA_13 VDDQ_5 1% 1% VDDQ_5 DDR_AA10
DDR_DQ[20] M27 AD27 1% 1% +1.5V_DDR L2 E9 +1.5V_DDR L2 E9 C451 0.1uF
DDR_DQA_20 DDR_ADA_14 DDR_AA14 CS VDDQ_6 CS VDDQ_6 DDR_AA12
DDR_DQ[21] G27 K1 F1 R420 10K K1 F1
DDR_DQA_21 C401 R414 10K ODT VDDQ_7 C419 ODT VDDQ_7 DDR_WEb
DDR_DQ[22] M26 Y27 J3 H2 1000pF J3 H2
DDR_DQ[24-31] DDR_DQA_22 DDR_BAA_0 DDR_BAA0 1000pF DDR_RASb RAS VDDQ_8 C411 0.1uF
H26 AB28 DDR_RASb RAS VDDQ_8 K3 H9
DDR_DQ[23] DDR_BAA1 K3 H9 DDR_CASb AR405 56
DDR_DQA_23 DDR_BAA_1 DDR_CASb CAS VDDQ_9 CAS VDDQ_9 DDR23_AA6
DDR_DQ[24] L23 W24 L3 L3 C440
DDR_DQA_24 DDR_BAA_2 DDR_BAA2 DDR_WEb DDR_WEb WE DDR23_AA4 1uF
H25 WE J1
DDR_DQ[25] J1
DDR_DQA_25 NC_1 NC_1 DDR23_AA5
DDR_DQ[26] L24 V24 T2 J9 T2 J9
DDR_DQA_26 DDR_RASA_N DDR_RASb DDR_RESETb RESET NC_2 DDR_RESETb RESET NC_2
DDR_DQ[27] J24 W25 L1 L1 AR406 56 C452 0.1uF
DDR_DQA_27 DDR_CASA_N DDR_CASb NC_3 NC_3 DDR01_AA6
DDR_DQ[28] M24 V26 L9 L9
DDR_DQA_28 DDR_WEA_N DDR_WEb NC_4 NC_4 DDR01_AA4
DDR_DQ[29] H23 F3 T7 F3 T7
DDR_DQA_29 DDR_QS0 DQSL NC_6 DDR_AA14 DDR_QS2 DQSL NC_6 DDR_AA14 DDR01_AA5
DDR_DQ[30] L25 U24 G3 G3
DDR_DQA_30 DDR_CKEA DDR_CKE DDR_QS0b DQSL DDR_QS2b DQSL R426 56
DDR_DQ[31] H24 DDR_CASb
DDR_DQA_31 R427 56 C441 1uF
W27 C7 A9 C7 A9 DDR_RASb
DDR_DM[0-3] DDR_CKA01_P DDR01_CLK DDR_QS1 DQSU VSS_1 DDR_QS3 DQSU VSS_1
W28 B7 B3 B7 B3
DDR_CKA01_N DDR01_CLKb DDR_QS1b DQSU VSS_2 DDR_QS3b DQSU VSS_2
DDR_DM[0] T26 E1 E1
DDR_DMA_0 VSS_3 VSS_3
DDR_DM[1] P25 N28 E7 G8 E7 G8
DDR_DMA_1 DDR_CKA23_P DDR23_CLK DDR_DM[0] DML VSS_4 DDR_DM[2] DML VSS_4
DDR_DM[2] J27 N27 D3 J2 D3 J2
DDR_DMA_2 DDR_CKA23_N DDR23_CLKb DDR_DQ[0-7] DDR_DM[1] DMU VSS_5 DDR_DQ[16-23] DDR_DM[3] DMU VSS_5
DDR_DM[3] K24 J8 J8
DDR_DMA_3 VSS_6 VSS_6
U23 E3 M1 DDR_DQ[16] E3 M1
DDR_VREFA DDR_VREFA DDR_DQ[0] DQL0 DQL0 VSS_7
VSS_7 F7 M9
DDR_DQ[1] F7 M9 DDR_DQ[17] DQL1
DQL1 VSS_8 VSS_8
T27 AA23 F2 P1 DDR_DQ[18] F2 P1
DDR_QS0 DDR_DQSA_P_0 DDR_RST_N DDR_RESETb DDR_DQ[2] DQL2 VSS_9
T28 DQL2 VSS_9 F8 P9
DDR_QS0b DDR_DQ[3] F8 P9 DDR_DQ[19]
DQL3
DDR_DQSA_N_0 DQL3 VSS_10 VSS_10
W26 R411 240 H3 T1 DDR_DQ[20] H3 T1 IC401-*1 IC402-*1
DDR_ZQ DDR_DQ[4] DQL4 VSS_11 K4B2G1646C-HCK0
P24 DQL4 VSS_11 H8 T9 K4B2G1646C-HCK0
DDR_QS1 1% DDR_DQ[5] H8 T9 DDR_DQ[21]
DQL5
DDR_DQSA_P_1 DQL5 VSS_12 VSS_12 DDR_1600_SS
P23 G2 DDR_DQ[22] G2 N3 DDR_1600_SS M8
N3
A0 VREFCA
M8
DDR_QS1b DDR_DQSA_N_1 DDR_DQ[6] DQL6 A0 VREFCA P7
DQL6 H7 P7
A1 P3
A1
DDR_DQ[7] H7 DDR_DQ[24-31] DDR_DQ[23]

DQL7
P3
A2 N2
A2
H1
K27 DDR_DQ[8-15] DQL7 B1 N2
A3 VREFDQ
H1
P8
A3 VREFDQ
DDR_QS2 DDR_DQSA_P_2 B1 VSSQ_1

P8
A4 P2
A4
K28 VSSQ_1 D7 B9 P2
A5 R8
A5
L8
DDR_QS2b DDR_DQ[8] D7 B9 DDR_DQ[24]
DQU0
R8 L8 A6 ZQ
DDR_DQSA_N_2 DQU0 VSSQ_2 VSSQ_2 R2
A6 ZQ R2
A7
C3 D1 DDR_DQ[30] C3 D1 T8
A7 T8
A8
DDR_DQ[14] DQU1 VSSQ_3 A8 R3 B2
K25 DQU1 VSSQ_3 C8 D8 R3
A9 VDD_1
B2
L7
A9 VDD_1
D9
DDR_QS3 DDR_DQ[13] C8 D8 DDR_DQ[29]
DQU2
L7 D9 A10/AP VDD_2
DDR_DQSA_P_3 DQU2 VSSQ_4 VSSQ_4 R7
A10/AP VDD_2
G7
R7
A11 VDD_3
G7
K26 C2 E2 DDR_DQ[28] C2 E2 N7
A11 VDD_3
K2
N7
A12/BC VDD_4
K2
DDR_QS3b DDR_DQSA_N_3 DDR_DQ[12] DQU3 VSSQ_5 A12/BC VDD_4 T3 K8
DQU3 VSSQ_5 A7 E8 T3
A13 VDD_5
K8 A13 VDD_5
N1
DDR_DQ[9] A7 E8 DDR_DQ[25]
DQU4
N1 VDD_6
DQU4 VSSQ_6 VSSQ_6 M7
VDD_6
N9
M7
NC_5 VDD_7
N9
A2 F9 DDR_DQ[26] A2 F9 NC_5 VDD_7

R1 VDD_8
R1
DDR_DQ[10] DQU5 VSSQ_7 VDD_8 M2 R9
DQU5 VSSQ_7 B8 G1 M2
BA0 VDD_9
R9
N8
BA0 VDD_9
DDR_DQ[15] B8 G1 DDR_DQ[31]
DQU6
N8 BA1
IC401-*2 IC401-*3 DQU6 VSSQ_8 VSSQ_8 M3
BA1 M3
BA2
IC402-*2 IC402-*3 A3 G9 DDR_DQ[27] A3 G9 BA2 A1
NT5CB128M16BP-CG NT5CB128M16BP-CG NT5CB128M16BP-DI NT5CB128M16BP-DI DDR_DQ[11] DQU7 VSSQ_9 VDDQ_1
A1
J7
VDDQ_1
A8
DQU7 VSSQ_9 J7
CK VDDQ_2
A8
K7
CK VDDQ_2
C1
K7 C1 CK VDDQ_3
DDR_1333_NANYA DDR_1333_NANYA DDR_1600_NANYA CK VDDQ_3 K9 C9
N3 M8 N3 M8 DDR_1600_NANYA K9 C9 CKE VDDQ_4
N3 M8 N3 M8 CKE VDDQ_4 D2
A0 VREFCA A0 VREFCA A0 VREFCA D2 VDDQ_5
P7 P7 P7 A0 VREFCA L2 E9
A1 A1 P7 VDDQ_5
P3 A1 P3 A1 L2 E9 CS VDDQ_6
P3 P3 CS VDDQ_6 K1 F1
A2 A2 A2 K1 F1 ODT VDDQ_7
N2 H1 N2 H1 N2 H1 A2 J3 H2
A3 VREFDQ A3 VREFDQ N2 H1 ODT VDDQ_7
P8 A3 VREFDQ P8 A3 VREFDQ J3 H2 RAS VDDQ_8
P8 P8 RAS VDDQ_8 K3 H9
A4 A4 A4 K3 H9 CAS VDDQ_9
P2 P2 P2 A4 L3
A5 A5 P2 CAS VDDQ_9
R8 L8 A5 R8 L8 A5 L3 WE
R8 L8 R8 L8 WE J1
A6 ZQ A6 ZQ A6 ZQ J1 NC_1
R2 R2 R2 A6 ZQ T2 J9
A7 A7 R2 NC_1
T8 A7 T8 A7 T2 J9 RESET NC_2
T8 T8 RESET NC_2 L1
A8 A8 A8 L1 NC_3
R3 B2 R3 B2 R3 B2 A8 L9
A9 VDD_1 A9 VDD_1 R3 B2 NC_3
L7 D9 A9 VDD_1 L7 D9 A9 VDD_1 L9 NC_4
L7 D9 L7 D9 NC_4 F3 T7
A10/AP VDD_2 A10/AP VDD_2 A10/AP VDD_2 F3 T7 DQSL NC_6
R7 G7 R7 G7 R7 G7 A10/AP VDD_2 G3
A11 VDD_3 A11 VDD_3 R7 G7 DQSL NC_6
N7 K2 A11 VDD_3 N7 K2 A11 VDD_3 G3 DQSL
N7 K2 N7 K2 DQSL
A12 VDD_4 A12 VDD_4 A12 VDD_4
T3 K8 T3 K8 T3 K8 A12 VDD_4 C7 A9
NC_6 VDD_5 NC_6 VDD_5 T3 K8
N1 NC_6 VDD_5 N1 NC_6 VDD_5 C7 A9 DQSU VSS_1
N1 N1 DQSU VSS_1 B7 B3
VDD_6 VDD_6 VDD_6 B7 B3 DQSU VSS_2
M7 N9 M7 N9 M7 N9 VDD_6 E1
NC_5 VDD_7 NC_5 VDD_7 M7 N9 DQSU VSS_2
R1 NC_5 VDD_7 R1 NC_5 VDD_7 E1 VSS_3
R1 R1 VSS_3 E7 G8
VDD_8 VDD_8 VDD_8 E7 G8 DML VSS_4
M2 R9 M2 R9 M2 R9 VDD_8 D3 J2
BA0 VDD_9 BA0 VDD_9 M2 R9 DML VSS_4
N8 BA0 VDD_9 N8 BA0 VDD_9 D3 J2 DMU VSS_5
N8 N8 DMU VSS_5 J8
BA1 BA1 BA1 J8 VSS_6
M3 M3 M3 BA1 E3 M1
BA2 BA2 M3 VSS_6
A1 BA2 A1 BA2 E3 M1 DQL0 VSS_7
A1 A1 DQL0 VSS_7 F7 M9
VDDQ_1 VDDQ_1 VDDQ_1 F7 M9 DQL1 VSS_8
J7 A8 J7 A8 J7 A8 VDDQ_1 F2 P1
CK VDDQ_2 CK VDDQ_2 J7 A8 DQL1 VSS_8
K7 C1 CK VDDQ_2 K7 C1 CK VDDQ_2 F2 P1 DQL2 VSS_9
K7 C1 K7 C1 DQL2 VSS_9 F8 P9
CK VDDQ_3 CK VDDQ_3 CK VDDQ_3 F8 P9 DQL3 VSS_10
K9 C9 K9 C9 K9 C9 CK VDDQ_3 H3 T1
CKE VDDQ_4 CKE VDDQ_4 K9 C9 DQL3 VSS_10
D2 CKE VDDQ_4 D2 CKE VDDQ_4 H3 T1 DQL4 VSS_11
D2 D2 DQL4 VSS_11 H8 T9
VDDQ_5 VDDQ_5 VDDQ_5 H8 T9 DQL5 VSS_12
L2 E9 L2 E9 L2 E9 VDDQ_5 G2
CS VDDQ_6 CS VDDQ_6 L2 E9 DQL5 VSS_12
K1 F1 CS VDDQ_6 K1 F1 CS VDDQ_6 G2 DQL6
K1 F1 K1 F1 DQL6 H7
ODT VDDQ_7 ODT VDDQ_7 ODT VDDQ_7 H7 DQL7
J3 H2 J3 H2 J3 H2 ODT VDDQ_7 B1
RAS VDDQ_8 RAS VDDQ_8 J3 H2 DQL7
K3 H9 RAS VDDQ_8 K3 H9 RAS VDDQ_8 B1 VSSQ_1
K3 H9 K3 H9 VSSQ_1 D7 B9
CAS VDDQ_9 CAS VDDQ_9 CAS VDDQ_9 D7 B9 DQU0 VSSQ_2
L3 L3 L3 CAS VDDQ_9 C3 D1
WE WE L3 DQU0 VSSQ_2
J1 WE J1 WE C3 D1 DQU1 VSSQ_3
J1 J1 DQU1 VSSQ_3 C8 D8
NC_1 NC_1 NC_1 C8 D8 DQU2 VSSQ_4
T2 J9 T2 J9 T2 J9 NC_1 C2 E2
RESET NC_2 RESET NC_2 T2 J9 DQU2 VSSQ_4
L1 RESET NC_2 L1 RESET NC_2 C2 E2 DQU3 VSSQ_5
L1 L1 DQU3 VSSQ_5 A7 E8
NC_3 NC_3 NC_3 A7 E8 DQU4 VSSQ_6
L9 L9 L9 NC_3 A2 F9
NC_4 NC_4 L9 DQU4 VSSQ_6
F3 T7 NC_4 F3 T7 NC_4 A2 F9 DQU5 VSSQ_7
F3 T7 F3 T7 DQU5 VSSQ_7 B8 G1
DQSL NC_7 DQSL NC_7 DQSL NC_7 B8 G1 DQU6 VSSQ_8
G3 G3 G3 DQSL NC_7 A3 G9
DQSL DQSL G3 DQU6 VSSQ_8
DQSL DQSL A3 G9 DQU7 VSSQ_9
DQU7 VSSQ_9
C7 A9 C7 A9 C7 A9
DQSU VSS_1 DQSU VSS_1 C7 A9
B7 B3 DQSU VSS_1 B7 B3 DQSU VSS_1
B7 B3 B7 B3
DQSU VSS_2 DQSU VSS_2 DQSU VSS_2
E1 E1 E1 DQSU VSS_2
VSS_3 VSS_3 E1
E7 G8 VSS_3 E7 G8 VSS_3
E7 G8 E7 G8
DML VSS_4 DML VSS_4 DML VSS_4
D3 J2 D3 J2 D3 J2 DML VSS_4
DMU VSS_5 DMU VSS_5 D3 J2
J8 DMU VSS_5 J8 DMU VSS_5
J8 J8
VSS_6 VSS_6 VSS_6
E3 M1 E3 M1 E3 M1 VSS_6
DQL0 VSS_7 DQL0 VSS_7 E3 M1
F7 M9 DQL0 VSS_7 F7 M9 DQL0 VSS_7
F7 M9 F7 M9
DQL1 VSS_8 DQL1 VSS_8 DQL1 VSS_8
F2 P1 F2 P1 F2 P1 DQL1 VSS_8
DQL2 VSS_9 DQL2 VSS_9 F2 P1
F8 P9 DQL2 VSS_9 F8 P9 DQL2 VSS_9
F8 P9 F8 P9
H3 T1 H3 T1 H3 T1 DQL3 VSS_10
DQL4 VSS_11 DQL4 VSS_11 H3 T1
H8 T9 DQL4 VSS_11 H8 T9 DQL4 VSS_11
H8 T9 H8 T9
G2 G2 G2 DQL5 VSS_12
DQL6 DQL6 G2
H7 DQL6 H7 DQL6
H7 H7
DQL7 DQL7 DQL7
B1 B1 B1 DQL7
VSSQ_1 VSSQ_1 B1
D7 B9 VSSQ_1 D7 B9 VSSQ_1
D7 B9 D7 B9
DQU0 VSSQ_2 DQU0 VSSQ_2 DQU0 VSSQ_2
C3 D1 C3 D1 C3 D1 DQU0 VSSQ_2
DQU1 VSSQ_3 DQU1 VSSQ_3 C3 D1
C8 D8 DQU1 VSSQ_3 C8 D8 DQU1 VSSQ_3
C8 D8 C8 D8
C2 E2 C2 E2 C2 E2 DQU2 VSSQ_4
DQU3 VSSQ_5 DQU3 VSSQ_5 C2 E2
A7 E8 DQU3 VSSQ_5 A7 E8 DQU3 VSSQ_5
A7 E8 A7 E8
A2 F9 A2 F9 A2 F9 DQU4 VSSQ_6
DQU5 VSSQ_7 DQU5 VSSQ_7 A2 F9
B8 G1 DQU5 VSSQ_7 B8 G1 DQU5 VSSQ_7
B8 G1 B8 G1
A3 G9 A3 G9 A3 G9 DQU6 VSSQ_8
DQU7 VSSQ_9 DQU7 VSSQ_9 A3 G9
DQU7 VSSQ_9 DQU7 VSSQ_9

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN DDR 4 50
DUAL COMPONENT +12V
FROM LIPS & POWER B/D Q501,Q504,

Q505,Q506 1ST : 0TRIY80001A 2ND : 0TR387500AA L511
PANEL_POWER TYP 1450mA
+3.5V_ST 12V_PANEL
RT1P141C-T112 MLB-201209-0120P-N2
Q502 1ST : 0TRIH80004A, 2ND : EBK61012501, 3RD : 0TR102009AM
Q502
C551 PANEL_VCC
Q507 C550 0.1uF
R508 1 3 1ST : EBK60752501, 2ND : EBK61011501 0.01uF 50V
4.7K NORMAL_26~55 50V
R502 C Q507
2 P502
+24V AO3407A
RL_ON 10K
B Q501
FW20020-24S IC502,IC503 1ST : EAN61151001, 2ND : EAN60670101
D
2SC3052
5V_PANEL
PANEL_DISCHARGE_REG
R558-*1
12V_PANEL12V_PANEL
R558
PANEL_DISCHARGE_REG
C560
10K
C552
OPT 1uF
25V
E L504
PWR ON 1 2 24V 10uF
MLB-201209-0120P-N2
22K
G
1/8W
1/8W
24V 24V 25V C563
R575
R576
2K
2K
3 4
GND GND 0.1uF
+3.5V_ST 5 6
L503 C519
OS Module OPT R555 50V
5V_PANEL
R559-*1
R559
1.8K
GND 7 8 GND 0.1uF
MLB-201209-0120P-N2 22K
3.5V 3.5V 50V
2.7K
9 10
21:9_PANEL_DISCHARGE_REG
21:9_PANEL_DISCHARGE_REG
3.5V 11 12 3.5V
C508 POWER_16_URSA_SCAN OPT
GND GND R574 0 C
0.1uF 13 14 L_VS R532 R554
GND GND/V-sync R573 0 100 POWER_18_INV_CTL 10K B Q506
16V 15 16 L/DIM0_VS
INV_CTL_18
R576-*1
12V INV ON 2SC3052
R575-*1
17 18 POWER_16_BCM_SCAN INV_CTL_18 R533 POWER_18_A_DIM
12V A.DIM A_DIM C
1/8W
3K
19 20 A_DIM_20 R553 E
1/8W
3K
0 R557
+12V 12V 21 22 P.DIM1 47K B Q505 22K
PWM_DIM_22 POWER_20_A_DIM PANEL_CTL
L501 GND/P.DIM2 Err OUT 2SC3052
MLB-201209-0120P-N2 23 24 ERROR_OUT_24 R531 0 A_DIM
A_DIM_20
SLIM_32~55 POWER_20_PWM_DIM E
POWER_16_GND
C506 R538 0 PWM_DIM

25
R518
0.1uF +3.3V_Normal
50V SMAW200-H24S2
0
P501 R523
4.7K
ERROR_OUT_PULL_UP
R529 0 ERROR_OUT
+3.5V_ST
POWER_20_ERROR_OUT +3.3V_Normal
#16/#20/#23
LD - GND OR USE
R546
1K
R551
OPT
+1.5V_DDR Max 800mA
POWER_22_A_DIM 10K
LE(N.L.D.) - OPEN R535 0 A_DIM
PWM_DIM_22
LE(L.D.) - USE POWER_22_PWM_DIM R543
C
R547 +3.5V_ST
PWM_DIM INV_CTL
R526 0 R540 0 6.8K B 10K IC508
NON_OPC/NON_IOP +1.5V_DDR
R527 0 OPT Q504 AP7173-SPG-13 HF(DIODES)
2SC3052 L517
E R552
BLM18PG121SN1D [EP]
POWER_24_PWM_DIM 10K
OPT
Power_DET ERROR_OUT_24
POWER_24_INV_CTL IN
1 8
OUT
POWER_24_GND
100 R537
THERMAL
0
PG FB
9
+12V +3.5V_ST 2 7
R517 ERROR_OUT
100K +3.5V_ST R541 0
R595
R524
POWER_24_ERROR_OUT
VCC SS 4.3K R1
PD_+12V PD_+3.5V R522 3 6 1%
R512 R515 10K C594 C591
2.7K
1%
0
5%
IC503
NCP803SN293
OPT
POWER_ON/OFF1
R591
1.5A 22uF 0.1uF
10K EN GND C593 10V 16V
4 5 R593
R520 POWER_DET 560pF 3.9K
VCC 3 2 RESET 100 <OS MODULE PIN MAP> 50V 1% R2
C590 R592
C580 1 10uF 1K
NON_PD_+3.5V 0.1uF GND PIN No LGD CMO(09) AUO SHARP 10V 1%
R513 16V
1.21K ESD
1% C520
0.1uF 18 INV_ON A-DIM INV_ON INV_ON
16V
V4:VBR-A
20 V5:NC NC Err_out Err_out
NON_PD_+3.5V
+24V R516
100K
22 PWM_DIM PWM_DIM A-DIM PWM_DIM
NON_PD_+3.5V
not to RESET at 8kV ESD Vout=0.8*(1+R1/R2)
PD_+20V PD_+18.5V Err_out
R510-*4 R510-*3 PD_24V IC502 24 LED:GND INV_ON PWM_DIM GND
5.6K 4.7K R510 NCP803SN293
1% 1% 8.2K
1% R519
VCC 3 2 RESET 100 15V-->3.6V CHECK PWR/MODULE PIN MAP
20V-->3.5V
PD_+20V PD_+18.5V 1 NON_PD_+3.5V
R511-*4 R511-*3
PD_24V C581 24V-->3.48V
1.3K
1%
1.21K
1%
R511
1.5K
1%
0.1uF
16V
GND
NON_PD_+3.5V
12V-->3.58V
ST_3.5V-->3.5V
+5V_Normal MAX 1A
Vout=0.8*(1+R1/R2)
+12V
+3.3V_NORMAL MAX 2.8A +12V IC507
+5V_Normal
AOZ1073AIL-3
R542
POWER_ON/OFF2_2
VIN
L516
+0.9V_CORE_BCM35230 OPT
C532
0.1uF
10K
L514
BLM18PG121SN1D
PGND
1 8
LX_2 3.6uH
2
16V +3.3V_Normal NR8040T3R6N
EN VIN LX_1
L507 6
R570
+12V 2 7
1%
51K
BLM18PG121SN1D
IC505-*1
FB LX Placed on SMD-TOP AGND 3A EN POWER_ON/OFF2_1
C568 C570
1/16W
4 AOZ1024DI(SORTING) 7 3 6 R1
R571
3.6K
L509 22uF 22uF
L502 C546 R566
2200pF C557
1%
VIN 3.6uH DCDC_NEW 10K 10V 10V
BLM18PG121SN1D Max 7350 mA COMP 10uF
FB COMP
R1 5 16V 4 5 OPT
2
C559 OPT
EN 6 4A R564
12K
0.1uF C565
R548
EAN60660602 16V 100pF
1
Placed on SMD-TOP
1%
27K
C534 C535 50V
FB IC505 LX 22uF 22uF
AGND
PGND
4 7
10V 10V C537
4.7K
C528 COMP AOZ1024DI OPT
1%
R549
10uF 5 50V
C505 16V DCDC_OLD
C503 R525
3
10uF 10uF 13K EAN60660601
R572
1%
10K
16V 16V
AGND
PGND
R2
C530
3300pF
50V
Vout=0.8*(1+R1/R2)
R550
POWER_ON/OFF2_2 Q503 Switching freq: 500K

1%
10K
AON7430
R2
D 5 4 G
R503
1K
IC501
3 S_3
+5V_USB+WIFI MAX 1.9A
TPS40192DRCR EP_GND
2 S_2
Vout=0.8*(1+R1/R2) Switching freq: 500K
C504
100pF +0.9V_CORE
50V ENABLE HDRV 1 S_1 +5V_USB
1 10 R577 4.7 L505
+12V IC506
AOZ1073AIL-3
+2.5V_BCM35230
THERMAL
0.9V_CORE_FB +2.5V_BCM35230
Max 960 mA
11
FB SW
0.47uF
2 9 1uH OPT L515

OPT
C515
R504 C510 3.6uH

C522 C524 C525 L513 PGND LX_2
25V
C523
2K 0.01uF 22uF 22uF 47uF 10uF IC504 1 8
50V COMP BOOT BLM18PG121SN1D
3 8 10V 10V 10V 10V AP2132MP-2.5TRG1 [EP] NR8040T3R6N
C509 50V VIN LX_1
220pF G 4 5 D +3.5V_ST
R567
2 7
1%
51K
VDD LDRV
+3.3V_Normal 4 7 R578 4.7
4.7uF
1 8
3A
C516
S_3 3 POWER_ON/OFF2_1
Placed on SMD-TOP AGND EN
10V
OPT C567 C571

THERMAL
TEST PG GND R544 3 6

R507 R1
1.5K
120-ohm
R528 18K R2 22uF 22uF
1%
PGD BP5
R568
10K OPT POWER_ON/OFF2_1 C545 R565
2700pF C555
5 6 10K 10V 16V
L506
S_2 2 2 7 1% 10K
10uF
C513 FB COMP OPT
C507 0.1uF EN ADJ R545 16V 4 5 OPT
1000pF 16V 56K R1 C558 OPT
S_1 1 R563
50V R506 3 6 1% 0.1uF C564
330 12K 100pF
16V
R536
10K
AON7200 VIN VOUT 50V

C533
R505
Q508
C527 0.1uF
OPT
4 2A 5
10uF +5V_Normal NC C538 C539
VCTRL
6.8K 6.3V 47uF 10uF
R501
R1 EAN61387601
10V 6.3V
0.9V_CORE_FB
R569
12K
1%
10K
1/16W R2
1% R2
Vout=0.591*(1+R1/R2) Switching freq: 600K C531
1uF
Vout=0.8*(1+R1/R2)
OPT
Switching freq: 500K
Vout=0.6*(1+R1/R2)
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. POWER 5 58
NEC MICOM
FLMD0
GND
+3.5V_ST
10K
47K
C602 C603 R641
50V 50V MICOM_DOWNLOAD
OPT
R639
13pF 13pF 0
R637
X601
For Debug 10MHz
15pF
15pF
WIRELESS_PWR_EN
C606
C607
P601 +3.5V_ST
WIRELESS_DET
12505WS-12A00
MICOM_RESET
1 X602
+3.5V_ST
2
MICOM_RESET 32.768KHz
3 R615 22
NEC_ISP_Tx R642 +3.5V_ST
10Mhz Crystal
4 4.7M
R617 22 OPT
5 NEC_ISP_Rx
47K
6
7
OCD1A
8
P122/X2/EXCLK/OCD0B
R644
9
OCD1B GND SW1
+3.5V_ST
10
JTP-1127WEM
2 1
22
P120/INTP0/EXLVI
R621 22
270K
11
FLMD0
OPT
C608
R645
P124/XT2/EXCLKS
0.1uF
0.1uF
12
4 3
R606 10K 16V
P121/X1/OCD0A
13
R643
C604
0.1uF
C605
P123/XT1
R607 10K +3.5V_ST R647 20K
NEC_ISP_Rx
R610 10K 1/16W
FLMD0
RESET
NEC_ISP_Tx 1%
REGC
1/16W
R646
VDD
VSS
P40
P41
20K
1%
R626 4.7K
R628 4.7K
48
47
46
45
44
43
42
41
40
39
38
37
R629 22
P60/SCL0 1 36 P140/PCL/INTP6 RL_ON
SCL2_3.3V
R630 22
P61/SDA0 2 35 P00/TI000
SDA2_3.3V SCART_MUTE
P62/EXSCL0 3 34 P01/TI010/TO00 R648 10K C
EDID_WP
EEPROM for Micom EEPROM_SCL
P63 P130 B Q601

4 33 2SC3052
EEPROM_SDA
P33/TI51/TO51/INTP4 IC602 P20/ANI0 E
+3.5V_ST HDMI_CEC
R631 22
5 32 R649 0
OPT
P75 6 uPD78F0514 31 ANI1/P21
POWER_ON/OFF2_1 MODEL1_OPT_3
IC601 P74 ANI2/P22
M24C16-WMN6T AMP_MUTE 7 30 MODEL1_OPT_2
P73/KR3 NEC_MICOM ANI3/P23
MODEL1_OPT_0 8 29 POWER_ON/OFF1
NC/E0 VCC
1 8 R632 22 P72/KR2 9 28 ANI4/P24
R601
SOC_RESET MICOM_DOWNLOAD
47K
NC/E1
2 7
WC P71/KR1 10 27 ANI5/P25
INV_CTL SIDE_HP_MUTE
NC/E2 SCL R619

P70/KR0 11 26 ANI6/P26
3 6 EEPROM_SCL MODEL1_OPT_1 KEY2
R633
22
22 P32/INTP3/OCD1B 12 25 ANI7/P27
VSS SDA R616 OCD1B KEY1
4 5 EEPROM_SDA OPT
22
13
14
15
16
17
18
19
20
21
22
23
24
S/T_SCL
R627
4.7K
P31/INTP2/OCD1A
P30/INTP1
P17/TI50/TO50
P16/TOH1/INTP5
P15/TOH0
P14/RXD6
P13/TXD6
P12/SO10
P11/SL10/RXD0
P10/SCK10/TXD0
AVREF
AVSS
+3.5V_ST
+3.5V_ST
MODEL OPTION
PIN NAME
C609 1uF
PIN NO. HIGH LOW
MICOM MODEL OPTION MODEL_OPT_0 8
10YEAR_TOOL
(10 SENSOR)
11YEAR_TOOL
(11 SENSOR)
MODEL_OPT_1 11 I2C_LED PWM_LED

+3.5V_ST
MODEL_OPT_2 30 TOUCH_KEY TACT_KEY
MODEL_OPT_3
10K
10K
10K
10K
31 PDP/3D LCD/OLED
10YEAR_TOOL
TOUCH_KEY
I2C LED
PDP/3D
OPT
R611
R613
R622
R624
LCD PDP OLED 3D

R604 100
AMP_RESET_N
10K
MODEL1_OPT_0 MODEL_OPT_3
22
R605 100 0 1 0 1 +3.5V_ST

PANEL_CTL MODEL1_OPT_1
R602 100
INSTANT_MODE MODEL1_OPT_2
R603 100
MODEL1_OPT_3
R638
R640
LOW LOW_SMALL TBD HIGH

10K
10K
10K
10K
11YEAR_TOOL
R636
LCD/OLED
TACT_KEY
PWM_LED
4.7K
MODEL_OPT_1 0 0 1 1
R612
R614
R623
R625
MODEL_OPT_2 0 1 0 1
LED_R/BUZZ
LED_B/LG_LOGO
POWER_DET
IR
NEC_ISP_Tx
NEC_TXD
NEC_ISP_Rx
POWER_ON/OFF2_2
NEC_RXD
OCD1A
S/T_SDA

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MICOM 6 50
DUAL COMPONENT
Q1901 1ST : 0TRIY80001A 2ND : 0TR387500AA
Q1902 1ST : EBK60752501, 2ND : EBK61011501
IC1904 1ST : 0ISTLPH062A, 2ND : EAN40055001

PCM_MDI[0-7] CI_MDI[0-7]
Close to BCM35230
PCM_MDI[0] R1909 22 OPT CI_MDI[0]
R1910 CI_MDI[1]
PCM_MDI[1] 22 OPT
BCM INT Demod PCM_MDI[2] AR1903 22 OPT CI_MDI[2]

PCM_MDI[3] CI_MDI[3] +5V_CI_ON
PCM_MDI[4] CI_MDI[4]
CI_MDI[5]
PCM_MDI[5]
R1915 22 OPT CI_MDI[6]
PCM_MDI[6]
R1916 22 OPT CI_MDI[7] C1904 C1905
PCM_MDI[7] R1932 R1933 CI_DATA[0-7]
0.1uF 10uF
10V 10K 10K
CI P1901
FE_TS_DATA[0-7] CI CI OPT
10067972-000LF CI R1946
10K
FE_TS_DATA[0] GND GND /PCM_CE1
R1901 22 CI 35 1 OPT
FE_TS_DATA[1] +5V_CI_ON R1937 62 /CI_DET1 36 2 DAT3 CI_DATA[3]
R1902 22 CI /CI_CD1
CI TS_OUT3 37 3 DAT4 CI_DATA[4]
FE_TS_DATA[2] CI_TS_DATA[3]
R1903 22 CI TS_OUT4 DAT5 CI_DATA[5]
CI_TS_DATA[4] 38 4
FE_TS_DATA[3] TS_OUT5 DAT6 +5V_CI_ON
R1904 22 CI R1971 R1972 39 5 CI_DATA[6]
CI_TS_DATA[5]
FE_TS_DATA[4] 10K 10K TS_OUT6 40 6 DAT6 CI_DATA[7]
R1905 22 CI CI_TS_DATA[6]
CI CI TS_OUT7 /CARD_EN1 CI R1956 22 R1973
FE_TS_DATA[5] 22 CI CI_TS_DATA[7] 41 7
R1906 10K
R1976 22 CI CARD_EN2 42 8 ADDR10 CI R1962 22 CI_ADDR[10]
FE_TS_DATA[6] R1907 22 CI /PCM_IORD CI_ADDR[10] CI
R1974 22 CI VS1 43 9 /O_EN CI R1963 22
FE_TS_DATA[7] /PCM_IOWR /PCM_OE
R1908 22 CI IORD 44 10 ADDR11 CI R1957 22 PCM_ADDR[11]
PCM_ADDR[11] +5V_CI_ON
CI_MDI[0-7] IOWR 45 11 ADDR10 CI R1958 22 PCM_ADDR[9]
PCM_ADDR[9]
TS_IN_SYN 46 12 ADDR8 CI R1959 22 CI_ADDR[8]
BCM INT Demod Close to BCM35230 22
CI_ADDR[8]
R1968 R1975
CI_MDI[0] TS_IN0 47 13 ADDR13 CI R1960 PCM_ADDR[13]
R1917 22 OPT PCM_ADDR[13] 10K 10K
PCM_MISTRT CI_MISTRT CI_MDI[1] TS_IN1 ADDR14 CI R1961 22 CI_ADDR[14]
48 14 CI_ADDR[14] CI CI CI
R1918 22 OPT CI_MDI[2] TS_IN2 R1964 22
PCM_MIVAL_ERR CI_MIVAL_ERR 49 15 /WR_EN
/PCM_WE
PCM_MCLKI R1919 22 OPT CI_MDI[3] TS_IN3 50 16 /IRQA R1967 22 CI
CI_MCLKI /PCM_IRQA
VCC 51 17 VCC C1910 0.1uF C1913
CI
0 VPP R1944 0 CI 0.1uF
R1977 +5V_CI_ON R1936 52 18 VPP 16V
Close to Tuner CI_MDI[4] OPT TS_IN4 OPT
10K 53 19 TS_IN_VAL
R1920 22 CI OPT CI_MDI[5] TS_IN5 54 20 TS_IN_CLK
NIM_TS_SYNC
CI_MDI[6] TS_IN6 ADDR12 CI R1947 22 PCM_ADDR[12]
R1921 22 CI R1929 R1930 55 21 PCM_ADDR[12]
NIM_VAL_ERR CI R1948
10K 10K CI_MDI[7] TS_IN7 56 22 ADDR7 22 PCM_ADDR[7]
R1922 22 CI PCM_ADDR[7]
NIM_TS_CLK OPT OPT TS_OUT_CLK ADDR6 CI R1949 22 CI_ADDR[6]
CI_TS_CLK 57 23 CI_ADDR[6]
R1927 22 CI CI_RESET ADDR5 CI R1950 22 CI_ADDR[5]
PCM_RST 58 24 CI_ADDR[5]
R1928 22 CI CI_WAIT ADDR4 CI R1951 22 PCM_ADDR[4]
/PCM_WAIT 59 25 PCM_ADDR[4]
R1934 10K OPT INPACK ADDR3 CI R1952 22 PCM_ADDR[3]
60 26 PCM_ADDR[3]
REG CI R1953 22
CI TS INPUT R1935 0 CI 61 27 ADDR2 PCM_ADDR[2]
PCM_ADDR[2]
TS_OUT_VAL ADDR1 CI R1954 22 CI_ADDR[1]
CI_TS_VAL 62 28 CI_ADDR[1]
TS_OUT_SYN ADDR0 CI R1955 22 CI_ADDR[0]
CI_TS_SYNC 63 29 CI_ADDR[0]
TS_OUT0 64 30 DAT0 CI_DATA[0]
CI_TS_DATA[0]
TS_OUT1 65 31 DAT1 CI_DATA[1] +5V_CI_ON
CI_TS_DATA[1]
TS_OUT2 66 32 DAT2 CI_DATA[2]
CI_TS_DATA[2]
PCM_TS_DATA[0-7] Close to CI Slot CI_TS_DATA[0-7]
/CI_CD2 R1938 CI 62 /CI_DET2 67 33 /IO_BIT R1945 10K
PCM_TS_DATA[0] AR1901 100 CI GND 68 34 GND OPT
CI_TS_DATA[0]
PCM_TS_DATA[1]
CI_TS_DATA[1] G2 69 G1
PCM_TS_DATA[2]
CI_TS_DATA[2]
PCM_TS_DATA[3]
CI_TS_DATA[3]
PCM_TS_DATA[4] AR1902 100 CI CI_TS_DATA[4]

PCM_TS_DATA[5] CI_TS_DATA[5] CI_MIVAL_ERR
PCM_TS_DATA[6] CI_TS_DATA[6] CI_MCLKI
PCM_TS_DATA[7] CI_MISTRT
CI_TS_DATA[7]
Close to CI Slot
R1923 220 CI
PCM_TS_CLK CI_TS_CLK
R1924 100 CI
PCM_TS_VAL CI_TS_VAL
R1925 100 CI CI POWER ENABLE CONTROL
PCM_TS_SYNC CI_TS_SYNC OE DIR CI_DATA NAND_DATA +3.3V_CI
C1916
12pF L L OUTPUT INPUT +5V_CI_ON
+5V_Normal
50V L H INPUT OUTPUT Q1902 L1902
OPT H X Z Z 0.1uF AO3407A BLM18PG121SN1D
CI TS OUTPUT OPT C1903
D
CI
16V
IC1903 R1931 22 CI C1906 CI CI
NAND_REb R1969
R1926 22 CI 74LVC245A OPT 0.1uF C1912 CI C1914 10K
/CI_EN1
G
NAND_DATA[0-7] 16V 0.1uF
R1943 C1909 0.1uF CI
VCC
20 1
DIR CI 16V
CI 22K 4.7uF 16V
CI_DATA[0-7] R1940
OE
19 2
A0 NAND_DATA[0] 16V
AR1904 100 CI 10K OPT
CI_DATA[0] B0
18 3
A1 NAND_DATA[1] OPT
CI_DATA[1]
B1
17 4
A2 NAND_DATA[2]
CI_DATA[2]
B2 A3 NAND_DATA[3] R1987
16 5
2.2K
B3
15 6
A4 NAND_DATA[4] CI
CI_DATA[3] R1980 100 CI C
B4
14 7
A5 NAND_DATA[5] R1942
CI_DATA[4] AR1905 100 CI 4.7K B Q1901
B5 A6 NAND_DATA[6] PCM_5V_CTL
CI_DATA[5] 13 8 2SC3052
CI CI
CI_DATA[6] B6
12 9
A7 NAND_DATA[7] E
CI_DATA[7] B7
11 10
GND
+5V_CI_ON
+3.3V_CI
+3.3V_CI
CI R1970 NAND F/M Data
22
IC1901
CI 74LVC125APW
C1901
1OE VCC 0.1uFOPT IC1902 3,3V_CI POWER
/CI_CE1 1 14 74AHC08PW +3.3V_CI
16V OPT
C1902
1A 4OE 0.1uF
NAND_REb 2 13 1A VCC
/CI_CE2 /CI_CE1 1 CI 14 16V
C1915 R1985 +3.3V_Normal +3.3V_CI
CI 9
1Y 4A OPT IC1905
/PCM_OE 3 12 NAND_WEb 1B 4B
0.1uF 10K
/CI_CE2 2 13 NAND_RBb 74LVC245A
16V CI
CI
2OE 4Y CI 45
4 11 1Y 4A VCC DIR
/PCM_IOWR /CI_EN1 3 12 20 1
L1901
R1986 22 OE
19 2
A0
BLM18PG121SN1D
2A 3OE /CI_EN1 CI_ADDR[2]
NAND_WEb 5 10 2A 4Y CI
/CI_EN1 4 11 CI_ADDR[1] B0
18 3
A1
PCM_ADDR[2] CI_ADDR[3] CI
2Y 3A B1 A2
CI 15 6 9 2B 3B PCM_ADDR[3] 17 4
CI_ADDR[4]
/PCM_WE NAND_REb 5 10 NAND_CLE B2 A3
CI C1907 CI C1908
16 5
GND 3Y PCM_ADDR[4] CI_ADDR[7] 0.1uF 0.1uF
7 8 CI 44 /PCM_IORD 2Y 3A
/PCM_CE1 CI 7 6 9 PCM_ADDR[7]
B3
15 6
A4
CI_ADDR[9]
B4 A5
14 7
GND 3Y PCM_ADDR[9] CI_ADDR[11]
7 8 CI_ADDR[0] B5 A6
13 8
PCM_ADDR[11] CI_ADDR[12]
B6 A7
12 9
PCM_ADDR[12] CI_ADDR[13]
B7 GND
11 10
PCM_ADDR[13]
CI DETECT
+3.3V_CI
+3.3V_CI +3.3V_CI
R1939 R1941
10K 10K IC1904
CI CI 74LVC1G32GW
B 1 5 VCC
CI CONTROL INTERFACE /CI_CD2 CI
A 2 C1911 R1966
/CI_CD1 OPT 0.1uF CI 10K
GND 3 4 Y
16V
CI
GND
R1965
CI_DET
47

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM35230 2010.11.11
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. CI 19 58
DVB-S2 LNB Part Allegro
(Option:LNB)
D2301
LNB SMAB34 D2304
SMAB34
2A 40V 40V
LNB
3A
+12V_LNB
C2307 C2302 C2324 C2305
0.01uF 1uF 68uF 68uF
50V 50V 35V 35V LNB
LNB LNB LNB LNB L2301
33UH
SP-7850_33 C2311 C2312 DCDC_GND and A_GND are connected
close to Boost pin(#1)
10uF 0.1uF
2.4A
25V 50V DCDC_GND and A_GND are connected in pin#27
close to VIN pin(#25)
LNB LNB
DCDC_GND DCDC_GND PCB_GND and A_GND are connected
D2302 DCDC_GND
US1M(suzhou) A_GND
LNB_OUT
1000V
C2303 D2303 Input trace widths should be sized to conduct at least 3A
LNB SMAB34
0.1uF 40V
LNB 50V LNB
C2301 Ouput trace widths should be sized to conduct at least 2A
0.22uF
25V
GNDLX
[EP]
NC_9
A_GND
LNB
VIN
BFI
BFO
LX
A_GND
28
27
26
25
24
23
22
A_GND
BOOST 1 21 NC_8
C2304 0.1uF THERMAL
VCP 2 29 20 NC_7
LNB C2306 22000pF TCAP BFC

3 19
LNB NC_1 IC2301 NC_6
4 18
A8290SETTR-T
TDO 5 LNB 17 NC_5 A_GND
A_GND
R2313 R2314
EXTM 6 16 NC_4 0 0
LNB_TX
TDI 7 15 NC_3
10
11
12
13
14
8
+3.3V_Normal
GND
VREG
SDA
ADD
SCL
NC_2
IRQ
DCDC_GND
A_GND A_GND
R2304
Max 1.3A
4.7K
R2301 33
R2302 33
LNB
R2303 0
+12V +12V_LNB
LNB
LNB
LNB
0.22uF
L2302
BLM18PG121SN1D
27pF
27pF
LNB
OPT
OPT
LNB
C2308
C2309
C2310
A_GND
LNB_INT
SDA1_3.3V
SCL1_3.3V

BCM35230 2010.11.02
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
LNB 23 57
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
NON CHB
TS Output
CHBO_TS_SERIAL
CHBO_TS_CLK
CHBO_TS_VAL_ERR
CHBO_TS_SYNC
CHB_RESET

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. NON CHB 28 50
LVDS LOCAL DIMMING
P3501
[51Pin LVDS OUTPUT Connector]
FI-RE51S-HFK-A [41Pin LVDS OUTPUT Connector]
NC [To LED DRIVER] +3.3V_FRC

1 R3512 33
2D/3D_CTL
NC LGD_2D/3D_CTRL
2
LVDS_SEL
NC P3503
3 +3.3V_Normal 12507WR-08L R3509
10K
NC +3.3V_Normal
4 OPT
NC R3511 1
5
3.3K PLACE SERIAL RESISTORS CLOSE TO URSA4
AUO_65_MIRROR R3501 R3510
6 AUO_65_MIRROR
3.3K 10K
LVDS_SEL P3502 2
7 LVDS_SEL_HIGH
FI-RE41S-HFK-A
NC
8 R3502 3 R3506 33
M0_SCLK
NC 10K
9 LVDS_SEL_LOW NC
L/DIM_ENABLE 1
10 4
NC
2 R3514 33
GND 2D/3D_CTL
11 NC AUO_2D/3D_CTRL
3 5 R3507 33
RA0N M0_MOSI
12 NC
LVDS_TXA0N
RA0P 4
13 NC 6 R3504 0
LVDS_TXA0P SCL2_3.3V
RA1N 5
14 LPB_42/47/55
LVDS_TXA1N NC
RA1P 6 R3505 0
15 7 SDA2_3.3V
LVDS_TXA1P NC
RA2N 7 LPB_42/47/55
16 NC
LVDS_TXA2N R3508 33
RA2P 8 8 L_VS
17 GND
LVDS_TXA2P
GND 9
18 9
RC0N R3513
RACLKN 10 LVDS_TXC0N 4.7K
19 RC0P
LVDS_TXACLKN
RACLKP 11 LVDS_TXC0P
20 RC1N
LVDS_TXACLKP
GND 12 LVDS_TXC1N
21 RC1P
RA3N 13 LVDS_TXC1P
22 RC2N
LVDS_TXA3N
RA3P 14 LVDS_TXC2N
23 RC2P
LVDS_TXA3P
RA4N 15 LVDS_TXC2P
24 GND
LVDS_TXA4N
RA4P 16
25 RCCLKN
LVDS_TXA4P
GND 17 LVDS_TXCCLKN
26 RCCLKP
BIT_SEL BIT_SEL 18 LVDS_TXCCLKP
27 GND
RB0N 19
28 R3503 RC3N
LVDS_TXB0N
RB0P 10K 20 LVDS_TXC3N
29 RC3P
LVDS_TXB0P BIT_SEL_LOW
RB1N 21 LVDS_TXC3P
30 RC4N
LVDS_TXB1N
RB1P 22 LVDS_TXC4N
31 RC4P
LVDS_TXB1P
RB2N 23 LVDS_TXC4P
32 GND
LVDS_TXB2N
RB2P 24
33
GND
LVDS_TXB2P
25
GND NON USED L/DIMMING
34
RBCLKN 26
RD0N
LVDS_TXD0N
(FOR EDGE_LED)
35 LVDS_TXBCLKN RD0P
RBCLKP 27 LVDS_TXD0P
36 RD1N
LVDS_TXBCLKP
GND 28 LVDS_TXD1N
37 RD1P
RB3N 29 LVDS_TXD1P L/DIM0_MOSI
38 LVDS_TXB3N RD2N
RB3P 30 LVDS_TXD2N L/DIM0_SCLK
39 LVDS_TXB3P RD2P
31 L/DIM0_VS
RB4N LVDS_TXD2P
40 LVDS_TXB4N GND
RB4P 32 M1_MOSI
41 LVDS_TXB4P RDCLKN M1_SCLK
GND 33 LVDS_TXDCLKN
42 M2_MOSI
RDCLKP
GND 34 LVDS_TXDCLKP M2_SCLK
43 GND M3_MOSI
GND 35
44 M3_SCLK
PANEL_VCC RD3N
GND 36 LVDS_TXD3N
45 RD3P
GND 37 LVDS_TXD3P
46 RD4N
L3501 38
NC LVDS_TXD4N
47 MLB-201209-0120P-N2 RD4P
VLCD 39 LVDS_TXD4P
48 GND
VLCD 40
49 GND
VLCD 41
50 C3501 C3502 C3503
VLCD 10uF 1000pF 0.1uF
51 25V 50V 50V 42
OPT
GND
52
GND

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM35230 2010. 10. 20
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Interface block 35 58
DUAL COMPONENT
5V_HDMI_1
HDMI_HPD_1 D3716 1ST : T-BAT54_SUZHO, 2ND : 0DSON00138A
OPT
C3726 OPT OPT
BODY_SHIELD 0.1uF VR3701 R3706
16V 10V
1K IC3702 1ST : EAN60991801, 2ND : T-AZ1117BH_1.8, 3RD : EAN54428201
20
HOT_PLUG_DETECT
19 GND
VDD[+5V] R3736 OPT0 DDC_SDA_1
18 OPT OPT
17
DDC/CEC_GND
R3737 VR3702
3.6K
DDC_SCL_1 * HDMI CEC
SDA 10V
16
SCL
HDMI_ARC
15
RESERVED
ARC
14
CEC R3707
CEC_REMOTE C3701 150
13 0.1uF
TMDS_CLK-
CK-_HDMI1 +3.5V_ST
12 R3708
TMDS_CLK_SHIELD +3.3V_Normal +3.3V_HDMI
11 63.4
TMDS_CLK+
CK+_HDMI1
10
TMDS_DATA0-
L3701
EAG62611201
D0-_HDMI1 R3717
9 BLM18PG121SN1D
TMDS_DATA0_SHIELD
G
27K
8
TMDS_DATA0+
120K
D0+_HDMI1
R3725
7
TMDS_DATA1-
Q3707
D
B
S
BSS83
D1-_HDMI1 D3716
6 C3727 C3728
TMDS_DATA1_SHIELD C3725
BAT54_SUZHO 0.1uF 10uF
5 16V 10uF
TMDS_DATA1+
D1+_HDMI1
4
TMDS_DATA2- CEC_REMOTE HDMI_CEC
D2-_HDMI1
3
TMDS_DATA2_SHIELD
2
TMDS_DATA2+
D2+_HDMI1
1
RSD-105156-100
JK3703
HDMI1
+3.3V_HDMI
+5V_Normal +5V_Normal
5V_HDMI_1 5V_HDMI_2
HDMI_HPD_2
5V_HDMI_2 OPT
C3702 OPT OPT
A2
A1
A2
A1
BODY_SHIELD 0.1uF VR3705 R3718 C3705 C3706 C3707 C3708 C3709 C3710
1K 10uF 10uF 10uF 0.1uF 0.1uF 0.1uF C3711
16V 10V D3713 D3715 0.1uF HDMI S/W OUTPUT
20
C
C
HOT_PLUG_DETECT
HDMI_CLK-
HDMI_RX0-
HDMI_RX0+
HDMI_RX1-
HDMI_RX1+
HDMI_RX2-
HDMI_RX2+
HDMI_CLK+
19 VDD[+5V] GND
R3704 OPT0 DDC_SDA_2
R3709 R3711 R3713 R3714
18 DDC/CEC_GND OPT OPT 4.7K 4.7K 4.7K 4.7K
R3701 VR3703 DDC_SCL_2
17 SDA 3.6K 10V
16 SCL DDC_SDA_1 DDC_SDA_2
15 RESERVED DDC_SCL_1 DDC_SCL_2
14 CEC
CEC_REMOTE
13 TMDS_CLK-
CK-_HDMI2
12 TMDS_CLK_SHIELD
EAG62611201
11 TMDS_CLK+
+5V_Normal
CK+_HDMI2 5V_HDMI_3
10 TMDS_DATA0-
D0-_HDMI2
9 TMDS_DATA0_SHIELD
A2
A1
TPWR_CI2CA
8 TMDS_DATA0+
D0+_HDMI2 D3714
7 TMDS_DATA1-
[EP]GND
VCC33_3
C
R3739
D1-_HDMI2 4.7K
6 TMDS_DATA1_SHIELD R3740 OPT
R0X2P
R0X2N
R0X1P
R0X1N
R0X0P
R0X0N
R0XCP
R0XCN
33
TXCN
TXCP
TX0N
TX0P
TX1N
TX1P
TX2N
TX2P
SCL1_3.3V
5 TMDS_DATA1+ R3710 R3712
D1+_HDMI2 4.7K 4.7K R3741 OPT 33
4 TMDS_DATA2- SDA1_3.3V
D2-_HDMI2
3 TMDS_DATA2_SHIELD
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
DDC_SDA_3
2 TMDS_DATA2+
R1XCN 1 54 CSCL R3742 33
D2+_HDMI2 DDC_SCL_3 SCL3_3.3V
1 CK-_HDMI1
R1XCP 2 53 CSDA R3743 33
SDA3_3.3V
CK+_HDMI1 THERMAL
R1X0N 3 52 INT
D0-_HDMI1
73
RSD-105156-100 R1X0P 4 51 CEC_D
JK3701
HDMI2 EDID Pull-up D0+_HDMI1
R1X1N 5 50 CEC_A +5V_Normal
D1-_HDMI1
R1X1P 6 49 R4PWR5V R3729
C3715
D1+_HDMI1
R1X2N DSCL4 0
D2-_HDMI1
7 IC3701 48 1uF
R1X2P DSDA4 10V 5V_HDMI_3
D2+_HDMI1
8 SII9287B 47
R3738
VCC33_1 9 46 R3PWR5V 10
HDMI1
5V_HDMI_3
RSVD_1 CBUS_HPD3
C3712
HDMI_HPD_3
OPT
10 45 HDMI_HPD_3
C3703 OPT OPT
1/16W
R3727
0.1uF VR3706 R3719
R2XCN 11 44 DSCL3
1%
1K CK-_HDMI2 DDC_SCL_3 5V_HDMI_2
1K
16V 10V
BODY_SHIELD R2XCP DSDA3
1uF
CK+_HDMI2
12 43
DDC_SDA_3 R3733
20 R2X0N 13 42 R2PWR5V 10
HOT_PLUG_DETECT GND D0-_HDMI2
C3716
R2X0P 14 41 CBUS_HPD2
19 VDD[+5V] HDMI_HPD_2
R3705 OPT0
1/16W
R3734
D0+_HDMI2
DDC_SDA_3 R2X1N DSCL2
15 40
1%
18 DDC/CEC_GND
1K
OPT OPT D1-_HDMI2 DDC_SCL_2
1uF
R3702 VR3704 DDC_SCL_3 R2X1P 16 DSDA2
39
17 SDA 3.6K 10V D1+_HDMI2 DDC_SDA_2
R2X2N 17 SBVCC
38
16 SCL
C3714
D2-_HDMI2
R2X2P 18 MICOM_VCC33
37
15 RESERVED D2+_HDMI2
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
14 CEC HDMI2
1uF
CEC_REMOTE
13 TMDS_CLK-
R3XCN
R3XCP
R3X0N
R3X0P
R3X1N
R3X1P
R3X2N
R3X2P
VCC33_2
RSVD_2
DSDA0
DSCL0
CBUS_HPD0
R0PWR5V
DSDA1
DSCL1
CBUS_HPD1
R1PWR5V
CK-_HDMI3
12 TMDS_CLK_SHIELD
5V_HDMI_1
EAG62611201
11 TMDS_CLK+
R3726
CK+_HDMI3 10
10 TMDS_DATA0-
C3713
D0-_HDMI3
9 TMDS_DATA0_SHIELD
1/16W
R3728
1%
8 TMDS_DATA0+ R3744
1K
100K
1uF
D0+_HDMI3
7 TMDS_DATA1-
D1-_HDMI3
6 TMDS_DATA1_SHIELD
5 TMDS_DATA1+
D1+_HDMI3
4 TMDS_DATA2-
D2-_HDMI3
3 TMDS_DATA2_SHIELD
2 TMDS_DATA2+
D2+_HDMI3
1
DDC_SDA_1
DDC_SCL_1
HDMI_HPD_1
CK-_HDMI3
CK+_HDMI3
D0-_HDMI3
D1-_HDMI3
D0+_HDMI3
D1+_HDMI3
D2+_HDMI3
D2-_HDMI3
RSD-105156-100
JK3702
HDMI3
HDMI3

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LV7 HDMI 37 50
Ethernet Block
+2.5V_BCM35230
L3901
MLB-201209-0120P-N2
JK3901
XRJV-01V-D12-180
1
EPHY_TDP
2 D3906
C3901 ADLC 5S 03 015
0.1uF 5.5V
16V
3
EPHY_TDN
4
EPHY_RDP
D3902 D3905
ADLC 5S 03 015 ADLC 5S 03 015
5 5.5V 5.5V
C3902
0.1uF
16V
6
EPHY_RDN
D3901
7 ADLC 5S 03 015
5.5V
8 +3.3V_Normal
D1 R3901 240
D2
EPHY_LINK
D3903
ADLC 5S 03 015
D3 R3902 240 5.5V
D4
EPHY_ACTIVITY
D3904
9 ADLC 5S 03 015
5.5V

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LV7 ETHERNET 39 50
COMP/AV JACK PACK
22 R4006
AV1_R_IN
1/10W
D4009 5%
AMOTECH R4018 C4013 C4022
5.6V 470K 560pF 560pF
50V 50V
22 R4007
AV1_L_IN
D4008 1/10W
AMOTECH R4019 5% C4023
JK4001 C4014
5.6V 470K 560pF
560pF
PPJ238-01 50V 50V
6C [RD1]E-LUG
+3.3V_Normal
5C [RD1]O-SPRING
R4017
2.7K
4C [RD1]CONTACT
AV1_CVBS_DET
R4023
[WH1]O-SPRING 1K
5B
D4007
[YL1]CONTACT 5.6V
4A
1%
5A [YL1]O-SPRING 10 R4030
AV1_CVBS_IN
ZD4009 C4012
6A [YL1]E-LUG R4016
5.1V 75 47pF
50V
ZD4010
6H [RD2]E-LUG
5.1V
BLM18PG121SN1D
5H [RD2]O-SPRING_2 L4006 22 R4032
AV2_R_IN COMP_AUDIO_R_IN
4H [RD2]CONTACT D4010 R4024
470K C4015
560pF C4020
5.6V
50V 560pF
5G [WH2]O-SPRING
50V
5F [RD2]O-SPRING_1
BLM18PG121SN1D
L4007 22 R4033
[RD2]E-LUG-S AV2_L_IN COMP_AUDIO_L_IN
7F
D4011 R4025 C4016
[BL2]O-SPRING 560pF C4021
5E 470K
5.6V 50V 560pF
50V
7E [BL2]E-LUG-S
L4001
R4020 1% CM2012FR27KT
4D [GN2]CONTACT 0 10 R4034
COMP1_Pr
ZD4011
5D [GN2]O-SPRING C4001 C4002
5.1V R4026
75 27pF 27pF
ZD4012 50V 50V
6D [GN2]E-LUG
5.1V
L4002
R4021 1% CM2012FR27KT
0 10 R4035
COMP1_Pb
ZD4013
5.1V R4027 C4003 C4004
75
27pF 27pF
ZD4014 50V 50V
5.1V
L4003
R4022 1% CM2012FR10KT
0 10 R4036
COMP1_Y
ZD4015 C4005 C4006
5.1V 47pF 47pF
R4028 50V 50V
ZD4016 75
5.1V
FOR EMI
+3.3V_Normal
R4029
2.7K
1K R4031
COMP1_DET
D4012
5.6V
CLOSE TO JUNCTION

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LV7 EU COMP/AV 40 50
DUAL COMPONENT
D4101,D4102 1ST : EAH42720601 2ND : EAH60994401
+3.3V_Normal
USB
IC4101
+5V_USB
AP2191DSG
R4101
L4101 NC GND 4.7K
8 1
MLB-201209-0120P-N2 OPT
OUT_2 IN_1
7 2
120-ohm OUT_1
6 3
IN_2
FLG EN
C4103
C4102 C4101 5 4
0.1uF
R4102
100uF 10uF 2.7K 16V
16V 10V
SIDE_USB_CTL1
SIDE_USB_OCD1
3AU04S-305-ZC-(LG)
P4101
1
USB DOWN STREAM
SIDE_USB_DM
RCLAMP0502BA
3
SIDE_USB_DP
OPT D4101 D4102

D4103
4
CDS3C05HDMI1 CDS3C05HDMI1
5.6V 5.6V
5

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LV7 EU USB 41 50
ERROR & VALID PIN
Option Table
H/NIM & F/NIM & T/C/S2 Combo Tuner <EU, China> R4445
0
Non_S: not use DVB-T/C/S2 combo Tuner(use H/NIM and F/NIM) T2

H/NIM DVB-T/C/S2
F/NIM_T/C DUAL COMPONENT
(EU) (Eu,Aisa) S: use DVB-T/C/S2 combo Tuner IC4404 +3.3V_TU
NL17SZ08DFT2G
Non_S Non_S S
H/NIM: use H/NIM(H/NIM, DVB-T/C/S2 combo Tuner) IC4401 1ST : T-TJ3940S_XX, 2ND : T-AP2114H_2.5TRG1
F/NIM: use F/NIM(EU_T/C, EU_DVB-T2, China) R4439
H/NIM F/NIM H/NIM TU_TS_VAL IN_B VCC
0
SCART: use Scart Jack 1 5
OPT
SCART SCART SCART NONE_T2 C4463
CN : use China F/NIM +5V_TU 0.1uF
TU_TS_ERR IN_A NONE_T2 16V
BOOSTER BOOSTER BOOSTER: use BOOSTER_CTL 2
EU_BR_F/NIM
RF_SW_CTL RF_SW_CTL: use RF_SWITCH_CTL R4446
GND OUT_Y 0
BOOSTER 3 4 TS_VAL_ERR
EU_F/NIM TC_F/NIM: use EU_DVB-T/C F/NIM L4406 NONE_T2
T2_CN_F/NIM_BR: use EU_DVB-T2, China F/NIM, BRZIL F/NIM BLM18PG121SN1D
TC_F/NIM
EU_F/NIM: use EU_F/NIM
* DVB-T/C/S2 combo Tuner: DVB-T/C is H/NIM, and DVB-S2 is F/NIM EU_BR_F/NIM: use EU_F/NIM and Brazil F/NIM
BOOSTER BOOSTER
R4419
R4425
0
BOOSTER 10K
Q4401
E MMBT3906(NXP)
C4401
OPT 0.1uF R4421 R4413
16V Tuner to CI Slot 0
B 2.2K TS_VAL_ERR NIM_VAL_ERR
BOOSTER C
C R4427 R4414
TU4401 TU4402
+5V_TU
Q4403
2SC3052
B 10K
RF_BOOSTER_CTL TU_TS_SYNC
0
NIM_TS_SYNC
C4425 BOOSTER
TDFR-G136D TDFQ-G001D L4410 0.01uF
50V
E R4415
0
Non_S Non_S TU_TS_CLK NIM_TS_CLK
1uH BOOSTER
HORIZONTAL_T HORIZONTAL_S C4411 C4417 Non_S
close to TUNER 100pF 0.1uF
NC_1 NC_1 50V 16V close to TUNER
1 1 +3.3V_S2_TU +5V_TU
BST_CNTL NC_2 BOOSTER
2 2 0
R4424
C4460 L4411-*1 L4412-*1
S
R4407 C4415 C4419 470 R4426
+B1[5V] NC_3 100pF 0.1uF
10uF S S 82 +5V_TU
3 3 50V 16V
6.3V 0 0
TU_SIF
0.1uF E
S S S C4426 S
NC_2[RF_AGC] S2_TU[3.3V]
R4408
S
0 close to TUNER
4 4 Non_S
L4411 270nH B Max 1.5A
C4431 SCL0_3.3V S
NC_3 NC_4 0.1uF R4422 Q4402
5 5 16V close to TUNER L4412
Non_S
270nH
C
4.7K MMBT3906(NXP)
NONE_S R4431
SDA0_3.3V R4428 1K R4433 R4434
OPT S S
0 220 220
SCLT TU_SCL +1.8V_TU C4421 C4422 OPT
62pF C4458 C4459 +1.25V_TU (EU)
6 6 62pF 20pF 20pF
50V
Non_S 50V 50V 50V OPT 0
SDAT TU_SDA Non_S Non_S Non_S TU_CVBS
7 7 C4407 R4429 E
C4414 +1.25V_TU
100pF 0 +3.3V_TU IC4403
NC_4 T_1.8V 0.1uF +5V_TU
8 8 50V 16V close to TUNER B AP2132MP-2.5TRG1 [EP]
S S R4430 Q4404
1K R4432 MMBT3906(NXP)
SIF T_SIF OPT
C R4416
9 9 R4435 R4436 1 8
20K R2
+1.25V_TU 200 200 1%
NC_5 NC_5 R4402 +3.3V_TU
THERMAL
75 PG GND
10 10 OPT POWER_ON/OFF2_1
R4411 R4417
10K
9
OPT OPT OPT OPT 2 7 11K
TU4401-*1 C4454
VIDEO T_CVBS C4416 C4461 C4455 C4420 C4456 ATV_OUT 1% R1
TDFR-G236D ADJ
10uF 100pF 1000pF 4700pF EN R4438
HORIZONTAL_T2
11 11 0.1uF 100uF
R4423 E 11K
NC_1 16V 50V 50V 50V 16V 16V +3.3V_TU
1 R4420 100K 3 6 1%
R4412
2
BST_CNTL GND GND_1 100
OPT 10K
+B1[5V] 12 12 TU_RESET VIN VOUT
3 B Q4405 C4432 C4438
4
5
NC_2[RF_AGC]
NC_3 +B2[1.2V] TD_1.2V

OPT
C4457 C4424
C4427
0.1uF MMBT3906(NXP)
C 10uF
0.1uF
OPT
4 2A 5
C4423 16V +5V_Normal
6
SCLT 13 13 10uF 0.1uF 16V VCTRL NC
SDAT 100pF
7 16V 50V 16V EAN61387601 C4453
8
NC_4 +B3[3.3V] T_3.3
9
SIF 14 14 10uF
NC_5
10 +2.5V_TU 16V
11
VIDEO RESET T_TU_RESET OPTION:SCART
12
GND 15 15 OPT
13
+B2[1.2V] C4428
C4434
14
+B3[3.3V] +B4[2.5V] NC_6 1uF
15
RESET 16 16
+B4[2.5V] 0.1uF
16
SCL SCL TD_SCL 16V
17
R4404 22
SDA 17 17 NONE_S
18
19
ERR
SYNC SDA TD_SDA

SCL1_3.3V
close to Tuner Vout=0.6*(1+R1/R2)
20 R4405 22
21
VALID 18 18 SDA1_3.3V
22
MCL C4402 C4404 +3.3V_S2_LNB
23
D0 ERR T/C/S2_ERROR 18pF 18pFclose to Tuner
24
D1 19 19 50V 50V
25
D2
+3.3V_TU
26
D3 SYNC T/C/S2_SYNC
27
D4 20 20 L4408
D5
28
MLB-201209-0120P-N2
29
D6 VALID T/C/S2_VALID Max 217mA
30
D7 21 21 C4447
31 C4451
C4443 S 10uF S 0.1uF
MCL T/C/S2_MCL +1.8V_TU
SHIELD +3.3V_TU OPT 0.1uF 10V S
22 22
IC4402 +3.3V_S2_DE
D0 T/C/S2_D0 AZ1117BH-1.8TRE1
23 23 L4403
R4410
MLB-201209-0120P-N2
D1 T/C/S2_D1
S
IN 3 2 OUT
1
24 24 AR4401
S C4446 C4450
1 S 10uF S 0.1uF
D2 T/C/S2_D2 NON_S 47 ADJ/GND +3.3V_S2_TU
10V S
25 25 C4436 C4437
TU_TS_ERR S 10uF 0.1uF L4404
D3 T/C/S2_D3 TU_TS_SYNC 10V S 16V MLB-201209-0120P-N2
26 26 TU_TS_VAL
TU_TS_CLK S C4448 C4452
D4 T/C/S2_D4 10uF
27 27 S 0.1uF
10V S
AR4402
D5 T/C/S2_D5
28 28 FE_TS_DATA[0-7]
NON_S 47
FE_TS_DATA[0]
D6 T/C/S2_D6 FE_TS_DATA[1]
29 29 AR4401-*1 +5V_Normal
FE_TS_DATA[2] 33 +5V_TU +3.3V_Normal
FE_TS_DATA[3] S +3.3V_TU
D7 T/C/S2_D7 L4401
30 30 L4409 MLB-201209-0120P-N2
L4402
31 BLM18PG121SN1D +1.25V_TU MLB-201209-0120P-N2
S2_1.25V
31 C4435
C4406 C4412 C4462 22uF C4433 C4440 C4441 OPT C4445 C4449
S C4442 C4444 0.1uF
S2_RESET 100pF 0.1uF 10uF 16V 0.1uF 22uF 0.1uF C4464 0.1uF
AR4403 16V 22uF 0.1uF 22uF 16V
SHIELD 32 50V 16V 10V S 16V 16V 16V
S S 16V 16V
NON_S 47 AR4402-*1
S2_3.3V +3.3V_S2_LNB FE_TS_DATA[4] 33
33 FE_TS_DATA[5] S
R4403 R4406
2.2K FE_TS_DATA[6]
S2_F22 R4401
51
S 100
S S2_RESET
34 S C4409
LNB_TX 0.1uF
S2_SCL S
35 0 S R4447
S2_SDA R4448
AR4403-*1
36 0 S
47 FE_TS_DATA[7] 33
S
GND_2 +3.3V_S2_DE R4418
Close to the tuner
37
C4405 C4410 C4418 +3.3V_TU +2.5V_TU
S2_LNB 100pF 10uF
38 0.1uF
50V 10V
16V
S S S IC4401
IF_N 39 R4418-*1 AP2114H-2.5TRG1
33
IF_P Surge protectioin
Close to Tuner #38 pin S VIN VOUT
IF_AGC
SHIELD R4437
C4403 C4439 1
LNB_OUT GND
TU_RESET_SUB
R4449
1000pF C4408 C4413 OPT 0.1uF

S 2.2K
33pF 33pF D4401 16V

RF_SWITCH_CTL_2 50V 3.0SMCJ20A(suzhougrande) C4429 C4430
OPT S 20V 10uF
S 0.1uF
S
RF_SWITCH_CTL 10V 16V
TW9910_RESET

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LV7 EU TUNER 44 50
DUAL COMPONENT
Q4502,Q4503
Q4504,Q4506 1ST : 0TRIY80001A 2ND : 0TR387500AA
Q4507,Q4508
Q4501 1ST : EBK61012701, 2ND : EBK58172301
Q4505 1ST : 0TRIH80004A, 2ND : EBK61012501, 3RD : 0TR102009AM
D4513 1ST : T-BAT54_SUZHO, 2ND : 0DSON00138A
+3.3V_Normal +5V_Normal
+12V
Full Scart R4513

10K
R4548 1K L4506
SC_DET/COMP2_DET
R4530
E R4524 C4526 10K
D4511 MMBT3906(NXP) C4525
5.6V Q4501 470 0.1uF 0.1uF
50V 50V DTV_ATV_SELECT
B
IC4502
C NLASB3157DFT2G
Q4502 R4526
R4550 C4518 C 2SC3052 47K
10 R4549 0 R4520
SC_CVBS_IN 390 B SELECT B1
C4523 6 1 ATV_OUT
AV_DET D4504
C4507 0.1uF 47uF
5.5V R4511 47pF
22 E 16V
COM_GND 75 50V VCC GND
1% CLOSE TO SOC 5 2
21 R4521
SYNC_IN 390
Gain=1+Rf/Rg R4553
20 Rf A B0 0
SYNC_OUT 75 1% R4512 R4527 4 3
Rg
R4523 15K 1/10W
19 D4505 180
SYNC_GND2 5% DTV/MNT_V_OUT
OPT OPT R4533
5.5V C4513 C4532
18 75
SYNC_GND1 100uF +3.3V_Normal C4531 180pF 1%
17 16V 180pF
RGB_IO 50V 50V
R4547
16 OPT +3.3V_Normal Selece = High ==> A = B1
R_OUT D4506
10K
C4539
30V 100pF R4508
15 75 Selece = Low ==> A = B0
RGB_GND 50V
R4545
1%
14 SC_FB
10K
R_GND L4508 C CLOSE TO SOC
CM2012FR27KT R4546
13 1K B Q4510
D2B_OUT SC_R/COMP2_Pr
C4533 C4534 2SC3052
12 D4501
G_OUT R4505 C
5.5V 75 27pF 27pF E
1% R4534
11 50V 50V 10K B Q4509
D2B_IN
2SC3052
10 L4509
G_GND CM2012FR27KT E
9 SC_G/COMP2_Y
ID C4536
D4502 C4535
8 5.5V R4506 27pF
B_OUT 27pF
75 1% 50V
7 50V
AUDIO_L_IN
L4510
OPT
6 CM2012FR27KT
B_GND
SC_B/COMP2_Pb D4513
5 C4537 C4538 BAT54_SUZHO
AUDIO_GND D4503 30V
5.5V 27pF 27pF REC_8
4 R4507
AUDIO_L_OUT 75 50V 50V
3 1%
AUDIO_R_IN
R4522
2 FOR EMI 9.1K
AUDIO_R_OUT
SC_ID
1 OPT
D4512 R4525 C4524
30V 1K 1uF
10V
PSC008-01
JK4501
C4540 1uF R4552 22
SC/COMP2_L_IN
D4507
5.6V C4505 C4514 CLOSE TO SOC
R4509 CLOSE TO JACK
OPT 470K 560pF 560pF
50V 50V
TP4501
INCM_VID_SC
R4532
16V 36
0.1uF
C4528
C4541 1uF R4551 22
SC/COMP2_R_IN
D4508 R4510 C4506

5.6V 470K 560pF CLOSE TO JUNCTION C4515
OPT 50V 560pF
50V
BLM18PG121SN1D
L4504
DTV/MNT_L_OUT
D4509
5.6V C4516 C4521
OPT 1000pF 4700pF
50V
BLM18PG121SN1D
L4505
DTV/MNT_R_OUT
D4510
C4522
5.6V C4517 4700pF
OPT 1000pF
50V
AUD_OUT >> EU/CHINA_HOTEL_OPT IC4501

5.6K R4501 LM324D
+12V
[SCART AUDIO MUTE] [SCART PIN 8]
1K R4515 OUT1 OUT4
DTV/MNT_L_OUT 1 14
+12V
C4508 IN1- IN4-
33K R4516
BLM18PG121SN1D
10uF 2 13
16V C4511
6800pF C4519 R4518
33pF
10K IN1+ IN4+ OPT
L4501
SCART1_Lout_N 50V 3 12
R4538
5.6K R4502 10K C
SCART1_Lout_P OPT
VCC VEE/GND R4535 B OPT
4 11 +3.5V_ST 4.7K
Q4508
2SC3052
OPT
IN2+ IN3+ R4541 E
5 10 DTV/MNT_L_OUT
12K
R4531
C4501 OPT C
Q4503 10K R4536
0.1uF IN2- IN3- REC_8
33K R4517 6 9 2SC3052 1K B
5.6K R4503 SC_RE1
50V SCART1_Rout_P R4528 RT1P141C-T112
Q4505 OPT
R4519 2K Q4507
10K OUT2 OUT3 E 2SC3052
SCART1_Rout_N 5.6K R4504 7 8
R4514 C4520 SCART_MUTE
1K 33pF 3 1
DTV/MNT_R_OUT C
DTV/MNT_R_OUT
C4510 OPT
Q4504 2 B Q4506
SC_RE2
10uF 2SC3052 2SC3052
C4512 6800pF R4529 OPT
16V 2K
50V R4537 E
CLOSE TO soc 1K

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LV7 EU SCART 45 50
DUAL COMPONENT +3.3V_Normal AMP_RESET_N
C4615
1000pF
Q4601 50V
1ST : 0TRIY80001A 2ND : 0TR387500AA
50V
L4602
+24V_AMP
22000pF
BLM18PG121SN1D
C4616
OPT
AUD_MASTER_CLK R4607
3.3
+24V_AMP OPT
+24V
C4624
OUT1A_2
OUT1A_1
PVDD1_3
PVDD1_2
PVDD1_1
C4618 C4620 C4622
0.1uF 0.1uF 10uF 0.01uF
VDD_IO
GND_IO
/RESET
PGND1A
C4614 C4640 50V
10uF 50V 50V 35V
CLK_I
BST1A
L4601 0.1uF 10V
MLB-201209-0120P-N2 16V [EP] D4601
SPK_L+
AD
1N4148W R4608 R4615 L4605
100V 12 12 R4616
OPT 10.0uH C4636
OPT C4610 C4612 OPT 0.1uF 4.7K
C4601 C4602 C4606 C4608 10uF 0.1uF C4629 50V
0.1uF 0.1uF 10uF 0.1uF 10V 390pF L4606
50V 50V 10V 16V 50V C4634
16V 10.0uH 0.47uF
48
47
46
45
44
43
42
41
40
39
38
37
C4604
1000pF
50V
50V
SPEAKER_L
C4603 C4630 C4637
100pF R4605 AGND_PLL 1 36 OUT1B_2 D4602
390pF
50V 0.1uF
50V
R4617
50V 3.3K 1N4148W R4609 R4613 4.7K
AVDD_PLL 2 35 OUT1B_1 100V
OPT
12 12
THERMAL SPK_L-
DVDD_PLL 3 49 34 PGND1B C4625
22000pF
LF 4 33 BST1B 50V WAFER-ANGLE
DGND_PLL IC4601 VDR1

5 32 SPK_L+
OPT 4
C4611
10uF
GND_1 6 NTP-7400L 31 VCC_5
C4613
10V 0.1uF SPK_L-
16V DGND 7 30 GND_2 3
DVDD 8 29 VDR2 SPK_R+

2
C4627 C4628 C4633
SDATA 9 28 BST2A 1uF
25V
1uF
25V
1uF
25V SPK_R-
AUD_LRCH 1
WCK 10 27 PGND2A C4626
P4601
AUD_LRCK 22000pF
50V
BCK 11 26 OUT2A_2
AUD_SCK
R4603 100 SDA 12 25 OUT2A_1

SDA3_3.3V
13
14
15
16
17
18
19
20
21
22
23
24
R4604 100
SCL3_3.3V
C4607 C4609
+3.5V_ST 33pF 33pF
50V 50V SPK_R+
SCL
/FAULT
MONITOR0
MONITOR1
MONITOR2
BST2B
PGND2B
OUT2B_1
OUT2B_2
PVDD2_1
PVDD2_2
PVDD2_3
+24V_AMP D4603 R4610 R4614

R4602 1N4148W 12
10K 12 L4603
100V 10.0uH C4638 R4618
R4606 OPT
C4631 0.1uF 4.7K
C 100 C4605 390pF L4604 C4635 50V
50V 0.47uF
R4601 B Q4601
1000pF C4619 C4621 C4623
10.0uH 50V
SPEAKER_R
AMP_MUTE 50V C4632
10K 2SC3052 0.1uF 0.1uF 10uF 390pF
50V 50V 35V D4604 50V C4639 R4619
E
C4617 1N4148W R4611 R4612 0.1uF 4.7K
22000pF 100V 12 12 50V
OPT
50V
SPK_R-

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LV7 EU AMP 46 50
DUAL COMPONENT
D4703,D4704
1ST : EAH42720601, 2ND : EAH60994401
D4705,D4706
+3.5V_ST
IR & KEY
EEPROM_SCL R4705 P4701
100 P4702
R4701 R4702 12507WR-15L 12507WR-12L
10K 10K D4706
1% 1% CDS3C05HDMI1
5.6V IR_15PIN IR_12PIN
R4710 1 1
100
KEY1 R4706
EEPROM_SDA 100
R4711 D4702 2 2
+3.5V_ST 100 5.6V
KEY2 D4707
AMOTECH CDS3C05HDMI1
C4701 C4703 5.6V 3 3
0.1uF 0.1uF
+3.5V_ST D4701
R4712
47K 5.6V
COMMERCIAL AMOTECH 4 4
R4714 +3.5V_ST +3.5V_ST
IR
47K
R4713 COMMERCIAL 5 5
Q4701 C 10K
R4717 L4701
2SC3052 B
3.3K BLM18PG121SN1D
COMMERCIAL E COMMERCIAL R4716 OPT 6 6
C 47K
B
Q4702 ECOMMERCIAL OPT OPT
C4702 C4704 C4705 R4707 1.5K 7 7
2SC3052 0.1uF 0.1uF 1000pF LED_B/LG_LOGO
COMMERCIAL 16V 16V 50V
8 8
R4709
0
9 9
D4705
C4708 5.6V
100pF AMOTECH
+3.3V_Normal 50V 10 10
L4702
BLM18PG121SN1D
+3.5V_ST 11 11
COMMERCIAL
C4709 C4710 R4708
OPT 0.1uF OPT 0.1uF LED_R/BUZZ 12 12
+3.5V_ST
R4719 16V 16V 1.5K
47K
R4715 COMMERCIAL 13
22 13
IR_OUT R4721
COMMERCIAL 47K R4703
S/T_SCL
R4720 COMMERCIAL 100
Q4703 C 10K 14
2SC3052 B
COMMERCIAL_EU E R4722
COMMERCIAL_EU C 47K D4703 15
B CDS3C05HDMI1
Q4704 E COMMERCIAL 5.6V
2SC3052 16
COMMERCIAL R4704
S/T_SDA 100
OPT
R4718
0 D4704
CDS3C05HDMI1
5.6V

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LV7 EU IR 47 50
5V_HDMI_4
AV2_CVBS_IN
SIDE_USB_CTL2
SIDE_USB_OCD2 3D_SYNC
M_REMOTE_TX
M_REMOTE_RX L_VS
DD_MREMOTE
M_RFModule_RESET
WIRELESS_DET
WIRELESS_PWR_EN
3D_GPIO_2
3D_GPIO_1
3D_GPIO_0
/RST_HUB
DC_MREMOTE
WIFI_DP
WIFI_DM
AV2_CVBS_DET

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LV7 EU 48 50
VDDC10 +1.5V_FRC_DDR +1.5V_FRC_DDR
+1.26V_FRC VDDC10 [SPI FLASH(2Mbit)] +3.3V_FRC
L5205
CIC21J501NE
C5201 C5210 C5211 C5243 C5225 C5228 C5213 C5244 C5231 C5232 C5234 C5247
0.1uF 22uF 22uF 0.22uF 0.1uF 0.1uF 0.1uF 0.22uF 0.1uF 0.1uF 0.1uF 1uF
10V 10V 6.3V 6.3V 6.3V IC5202
R5244 R5246 W25X20BVSNIG
PLACE TERMINATION RESISTORS CLOSE TO URSA5 4.7K 10K
TXBCLKP
TXBCLKN
TXACLKP
TXACLKN
CS VCC
1 8
TXB2P
TXA1P
TXA4N
TXB0P
TXB0N
TXB1P
TXB1N
TXB2N
TXB3P
TXB3N
TXB4P
TXB4N
TXA0P
TXA0N
TXA1N
TXA2P
TXA2N
TXA3P
TXA3N
TXA4P
+1.26V_FRC DVDD_DDR_1V SPI_CS
L5201 R5245 DO HOLD R5252

CIC21J501NE 2 7
SPI_DO
33 3.3K
C5202 C5246 C5206 WP CLK
R5224 R5230
0.1uF 22uF 0.1uF 3 6 SPI_SCLK
13pF
13pF
10V 100 100
R5225 R5231 GND DIO
4 5 SPI_DI
Place Close to Bead 100 100
C5241
C5242
24MHz
DVDD_DDR_1V
X5201
R5226 R5232
+3.3V_FRC VDD33 VDD33 (VDDP)
100 100 URSA5_FLASH_WINBOND_2M
AVDD_LVDS_3.3V
L5202 R5227 R5233
GPIO[1]
3D_SYNC
GPIO[8]
+1.5V_FRC_DDR
CIC21J501NE
100 100 1M
L_VS
R5237
VDD33
C5203 C5207 C5214 C5219 C5245
AVDD_PLL
R5228 R5234
0.1uF 0.1uF 0.1uF 0.1uF 0.22uF IC5202-*1
AVDD33
VDDC10
6.3V 100 100 MX25L2006EM1I-12G, HF
0.1uF C5240
0
R5229 R5235
CS VCC
33
100 100 1 8
R5236
0
0
0
+3.3V_FRC AVDD33 AVDD33 SO/SIO1 HOL
R5238
R5239
R5240
R5241
R5242
2 7
L5206
CIC21J501NE WP SCL
3 6
F10
G10
F11
F12
G11
G12
K10
L10
M10
N10
N11
P10
P11
R13
T13
U15
R14
T14
U14
U13
R12
E11
R10
T11
R11
U11
F4
F5
D4
D5
E4
E5
M5
L4
L5
K9
M4
N4
N5
M9
N9
R2
R3
R4
R5
T4
U4
U3
T3
T2
U2
T1
R1
R6
R7
R8
R9
T8
U8
U7
T7
T6
U6
U5
T5
J1
J2
P9
K2
K1
P8
N2
M1
N1
N3
M3
L1
M2
L2
K3
L3
C5233 C5236 C5238 C5239 GND SI/S
0.1uF 0.1uF 0.1uF 0.1uF 4 5
AVDD_1
AVDD_2
AVDD_DDR_C_1
AVDD_DDR_C_2
AVDD_DDR_D_1
AVDD_DDR_D_2
AVDD_DDR_D_3
AVDD_DDR_D_4
AVDD_LVDS3.3V_1
AVDD_LVDS3.3V_2
AVDD_LVDS3.3V_3
AVDD_LVDS3.3V_4
AVDD_MPLL3.3V
AVDD_LPLL3.3V
AVDD_PLL3.3V
AVDDL_MOD1.26V
DVDD_DDR_1.26V
DVDD_HF1.26V
VD33_1
VD33_2
VD33_3
VDDC_1.26V_1
VDDC_1.26V_2
VDDC_1.26V_3
VDDC_1.26V_4
VDDC_1.26V_5
VDDC_1.26V_6
VDDC_1.26V_7
RXBCLKP
RXBCLKN
RXB0P
RXB0N
RXB1P
RXB1N
RXB2P
RXB2N
RXB3P
RXB3N
RXB4P
RXB4N
RXACLKP
RXACLKN
RXA0P
RXA0N
RXA1P
RXA1N
RXA2P
RXA2N
RXA3P
RXA3N
RXA4P
RXA4N
XTALO
XTALI
GPIO0/(UART_RX/S_PIF_DA0)
GPIO1
GPIO2/(S_PIF_CLK)
GPIO3/(LTD_DA1)
GPIO4/(LTD_DE)
GPIO5/(LTD_CLK)
GPIO6/(LTD_DA0)
GPIO7(3D_FLAG)
GPIO8
GPIO9/(UART_TX/S_PIF_DA1)
GPIO10/(S_PIF_FC)
GPIO11/(S_PIF_CS)
VSYNC_LIKE
M_S_PIF_CLK
M_S_PIF_CS
M_S_PIF_DA0
M_S_PIF_DA1
M_S_PIF_FC
S_M_PIF_CLK
S_M_PIF_CS
S_M_PIF_DA0
S_M_PIF_DA1
S_M_PIF_FC
SOFT_RST_L
SOFT_RST_R
OP_SYNC_L
OP_SYNC_R
URSA5_FLASH_MACRONIX_2M
FRC_A[0-13]
+3.3V_FRC AVDD_PLL AVDD_PLL FRC_A[0] P14 C8
DDR3_A0/DDR2_NC TXA0P/GCLK6/BLUE[7] LVDS_TXA0P
FRC_A[1] G15 C9
L5203 DDR3_A1/DDR2_A8 TXA0N/GCLK5/BLUE[6] LVDS_TXA0N
CIC21J501NE FRC_A[2] N14 B8
DDR3_A2/DDR2_NC TXA1P/OPT_N/LK3/BLUE[9] LVDS_TXA1P
FRC_A[3] L15 A8
C5204 C5208 C5215 C5217 DDR3_A3/DDR2_A10 TXA1N/FLK/BLUE[8] LVDS_TXA1N
FRC_A[4] H15 A7
0.1uF 0.1uF 10uF 0.1uF DDR3_A4/DDR2_A2 TXA2P/GREEN[1] LVDS_TXA2P
FRC_A[5] L14 B7
6.3V DDR3_A5/DDR2_A3 TXA2N/OPT_P/LK2/GREEN[0] LVDS_TXA2N
FRC_A[6] G14 C6
DDR3_A6/DDR2_A4 TXACLKP/RLV0N/GREEN[3] LVDS_TXACLKP
FRC_A[7] N12 C7
DDR3_A7/DDR2_A5 TXACLKN/RLV0P/GREEN[2] LVDS_TXACLKN
FRC_A[8] G13 B6
+3.3V_FRC AVDD_LVDS_3.3V AVDD_LVDS_3.3V DDR3_A8/DDR2_A6 TXA3P/RLV1N/GREEN[5] LVDS_TXA3P
FRC_A[9] N13 A6
DDR3_A9/DDR2_A9 TXA3N/RLV1P/GREEN[4] LVDS_TXA3N
L5204 FRC_A[10] H14 A5
CIC21J501NE DDR3_A10/DDR2_RASZ TXA4P/RLV2N/GREEN[7] LVDS_TXA4P
FRC_A[11] F15 B5
DDR3_A11/DDR2_A11 TXA4N/RLV2P/GREEN[6] LVDS_TXA4N
FRC_A[12] H13
C5205 C5209 C5216 C5220 C5223 C5227 DDR3_A12/DDR2_A0
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF FRC_A[13] P13 C4
DDR3_A13/DDR2_A12 TXB0P/RLV3N/GREEN[9] LVDS_TXB0P
C5
TXB0N/RLV3P/GREEN[8] LVDS_TXB0N
M12 B4
FRC_BA0 DDR3_BA0/DDR2_BA2 TXB1P/RLVCLKN/RED[1] LVDS_TXB1P
H12 A4
FRC_BA1 DDR3_BA1/DDR2_CASZ TXB1N/RLVCLKP/RED[0] LVDS_TXB1N
L13 A3
FRC_BA2
FRC_MCLK
F16
DDR3_BA2/DDR2_A1
DDR3_MCLK/DDR2_MCLK
NON 21:9 Cinema TXB2P/RLV4P/RED[3]/EPI_A3P
TXB2N/RLV4N/RED[2]/EPI_A3N
TXBCLKP/RLV5N/RED[5]/EPI_A2P
B3
C2
LVDS_TXB2P
LVDS_TXB2N
LVDS_TXBCLKP
GPIO1 : HI => B8/94, LOW => B4/98 F17 C3
FRC_MCLKB DDR3_MCLKZ/DDR2_MCLKZ TXBCLKN/RLV5P/RED[4]/EPI_A2N LVDS_TXBCLKN
CHIP_CONF : {GPIO8, PWM1, PWM0}
CHIP_CONF = 3’d5 : boot from interal SRAM
FRC_CKE
J13
DDR3_CKE/DDR2_ODT IC5201 TXB3P/RLV6N/RED[7]/EPI_A1P
TXB3N/RLV6P/RED[6]/EPI_A1N/
B2
A2
LVDS_TXB3P
LVDS_TXB3N
CHIP_CONF = 3’d6 : boot from EEPROM K12 C1
FRC_ODT DDR3_ODT/DDR2_CKE TXB4P/RLV7N/RED[9]/EPI_A0P LVDS_TXB4P
CHIP_CONF = 3’d7 : boot from SPI Flash
FRC_RASB
FRC_CASB
L12
K13
DDR3_RASZDDR2_WEZ
DDR3_CASZ/DDR2_BA1
LGE7303C TXB4N/RLV7P/RED[8]/EPI_A0N
B1
LVDS_TXB4N
K14 C16
URSA5 CONFIGURATION FRC_WEB DDR3_WEZ/DDR2_BA0 TXC0P/SOE
B17
LVDS_TXC0P
+3.3V_FRC TXC0N/POL LVDS_TXC0N
M14 B16
FRC_DDR3_RESETB DDR3_RESET/DDR2_A7 TXC1P/GSP_R LVDS_TXC1P
A16
TXC1N/GSP/VST LVDS_TXC1N
N16 A15
FRC_DQSL DDR3_DQSL/DDR2_DQSL TXC2P/GOE/GCLK1 LVDS_TXC2P
10K
R5211 10K
R5215 10K
M17 B15
10K
FRC_DQSU DDR3_DQSU/DDR2_DQSU TXC2N/GSC/GCLK3 LVDS_TXC2N

C14
OPT
F10
TXCCLKP/LLV0N LVDS_TXCCLKP
G10
F11
F12
G11
G12
K10
L10
M10
N10
N11
P10
P11
R13
T13
U15
R14
T14
U14
U13
R12
E11
R10
T11
R11
U11
F4
F5
D4
D5
E4
E5
M5
L4
L5
K9
M4
N4
N5
M9
N9
R2
R3
R4
R5
T4
U4
U3
T3
T2
U2
T1
R1
R6
R7
R8
R9
T8
U8
U7
T7
T6
U6
U5
T5
J1
J2
P9
K2
K1
P8
N2
M1
N1
N3
M3
L1
M2
L2
K3
L3
M16 C15
R5207
R5203
FRC_DQSLB DDR3_DQSBL/DDR2_DQSBL TXCCLKN/LLV0P LVDS_TXCCLKN

AVDD_1
AVDD_2
AVDD_DDR_C_1
AVDD_DDR_C_2
AVDD_DDR_D_1
AVDD_DDR_D_2
AVDD_DDR_D_3
AVDD_DDR_D_4
AVDD_LVDS3.3V_1
AVDD_LVDS3.3V_2
AVDD_LVDS3.3V_3
AVDD_LVDS3.3V_4
AVDD_MPLL3.3V
AVDD_LPLL3.3V
AVDD_PLL3.3V
AVDDL_MOD1.26V
DVDD_DDR_1.26V
DVDD_HF1.26V
VD33_1
VD33_2
VD33_3
VDDC_1.26V_1
VDDC_1.26V_2
VDDC_1.26V_3
VDDC_1.26V_4
VDDC_1.26V_5
VDDC_1.26V_6
VDDC_1.26V_7
RXBCLKP
RXBCLKN
RXB0P
RXB0N
RXB1P
RXB1N
RXB2P
RXB2N
RXB3P
RXB3N
RXB4P
RXB4N
RXACLKP
RXACLKN
RXA0P
RXA0N
RXA1P
RXA1N
RXA2P
RXA2N
RXA3P
RXA3N
RXA4P
RXA4N
XTALO
XTALI
GPIO0/(UART_RX/S_PIF_DA0)
GPIO1
GPIO2/(S_PIF_CLK)
GPIO3/(LTD_DA1)
GPIO4/(LTD_DE)
GPIO5/(LTD_CLK)
GPIO6/(LTD_DA0)
GPIO7(3D_FLAG)
GPIO8
GPIO9/(UART_TX/S_PIF_DA1)
GPIO10/(S_PIF_FC)
GPIO11/(S_PIF_CS)
VSYNC_LIKE
M_S_PIF_CLK
M_S_PIF_CS
M_S_PIF_DA0
M_S_PIF_DA1
M_S_PIF_FC
S_M_PIF_CLK
S_M_PIF_CS
S_M_PIF_DA0
S_M_PIF_DA1
S_M_PIF_FC
SOFT_RST_L
SOFT_RST_R
OP_SYNC_L
OP_SYNC_R
M15 B14
FRC_DQSUB DDR3_DQSBU/DDR2_DQSBU TXC3P/LLV1N LVDS_TXC3P
P14 C8 A14
PWM0 G15
DDR3_A0/DDR2_NC
DDR3_A1/DDR2_A8
TXA0P/GCLK6/BLUE[7]
TXA0N/GCLK5/BLUE[6]
C9
TXC3N/LLV1P LVDS_TXC3N
J15 N14
L15
DDR3_A2/DDR2_NC TXA1P/OPT_N/LK3/BLUE[9]
B8
A8
A13
PWM1 FRC_DML DDR3_DQML/DDR2_DQU5 H15
DDR3_A3/DDR2_A10 TXA1N/FLK/BLUE[8]
A7 TXC4P/LLV2N LVDS_TXC4P
FRC_DQL[0-7] R16 L14
DDR3_A4/DDR2_A2 TXA2P/GREEN[1]
B7 B13
FRC_DMU DDR3_DQMU/DDR2_DQU4 G14
DDR3_A5/DDR2_A3
DDR3_A6/DDR2_A4
TXA2N/OPT_P/LK2/GREEN[0]
TXACLKP/RLV0N/GREEN[3]
C6
TXC4N/LLV2P LVDS_TXC4N
N12 C7
GPIO[8] G13
DDR3_A7/DDR2_A5
DDR3_A8/DDR2_A6
TXACLKN/RLV0P/GREEN[2]
TXA3P/RLV1N/GREEN[5]
B6
N13 A6
FRC_DQL[0] R17 H14
DDR3_A9/DDR2_A9
DDR3_A10/DDR2_RASZ
TXA3N/RLV1P/GREEN[4]
TXA4P/RLV2N/GREEN[7]
A5 C12
GPIO[1] DDR3_DQL0/DDR2_DQU3 F15
DDR3_A11/DDR2_A11 TXA4N/RLV2P/GREEN[6]
B5
TXD0P/LLV3N LVDS_TXD0P
FRC_DQL[1] H17 H13
C13
R5204 OPT10K
DDR3_A12/DDR2_A0
R5208 OPT10K
10K
10K
P13 C4
DDR3_DQL1/DDR2_DQL0 DDR3_A13/DDR2_A12 TXB0P/RLV3N/GREEN[9]
C5 TXD0N/LLV3P LVDS_TXD0N
FRC_DQL[2] R15 M12
DDR3_BA0/DDR2_BA2
TXB0N/RLV3P/GREEN[8]
TXB1P/RLVCLKN/RED[1]
B4 B12
DDR3_DQL2/DDR2_DQL6 H12 A4
TXD1P/LLVCLKN LVDS_TXD1P
OPT
DDR3_BA1/DDR2_CASZ TXB1N/RLVCLKP/RED[0]
FRC_DQL[3] J17 L13
DDR3_BA2/DDR2_A1 TXB2P/RLV4P/RED[3]/EPI_A3P
A3
B3
A12
DDR3_DQL3/DDR2_DQL7
21:9 Cinema TXD1N/LLVCLKP LVDS_TXD1N

TXB2N/RLV4N/RED[2]/EPI_A3N
R5216
F16 C2
FRC_DQL[4] T17 A11
R5212
DDR3_MCLK/DDR2_MCLK TXBCLKP/RLV5N/RED[5]/EPI_A2P
F17 C3
DDR3_MCLKZ/DDR2_MCLKZ TXBCLKN/RLV5P/RED[4]/EPI_A2N
DDR3_DQL4/DDR2_DQL3 J13
DDR3_CKE/DDR2_ODT TXB3P/RLV6N/RED[7]/EPI_A1P
B2
TXD2P/LLV4N/EPI_B3P LVDS_TXD2P
FRC_DQL[5] H16 K12
TXB3N/RLV6P/RED[6]/EPI_A1N/
A2
C1
B11
DDR3_DQL5/DDR2_DQL2 L12
DDR3_ODT/DDR2_CKE TXB4P/RLV7N/RED[9]/EPI_A0P
B1 TXD2N/LLV4P/EPI_B3N LVDS_TXD2N
FRC_DQL[6] T15 K13
DDR3_RASZDDR2_WEZ
DDR3_CASZ/DDR2_BA1
TXB4N/RLV7P/RED[8]/EPI_A0N
C10
DDR3_DQL6/DDR2_DQL1 K14
DDR3_WEZ/DDR2_BA0
C16
TXDCLKP/LLV5N/BLUE[1]/EPI_B2P LVDS_TXDCLKP
IC5201-*1
TXC0P/SOE
FRC_DQL[7] G16 M14
TXC0N/POL
B17
B16
C11
DDR3_DQL7/DDR2_DQL5 DDR3_RESET/DDR2_A7 TXC1P/GSP_R
A16 TXDCLKN/LLV5P/BLUE[0]/EPI_B2N LVDS_TXDCLKN
N16
DDR3_DQSL/DDR2_DQSL
TXC1N/GSP/VST
TXC2P/GOE/GCLK1
A15 B10
M17
DDR3_DQSU/DDR2_DQSU TXC2N/GSC/GCLK3
B15
TXD3P/LLV6N/BLUE[3] LVDS_TXD3P
FRC_DQU[0] K15 C14
A10
FRC_DQU[1] N15
DDR3_DQU0/DDR2_DQU7
DDR3_DQU1/DDR2_DQML
M16
M15
J15
DDR3_DQSBL/DDR2_DQSBL
DDR3_DQSBU/DDR2_DQSBU
DDR3_DQML/DDR2_DQU5
LGE7303D TXCCLKP/LLV0N
TXCCLKN/LLV0P
TXC3P/LLV1N
TXC3N/LLV1P
TXC4P/LLV2N
C15
B14
A14
A13
TXD3N/LLV6P/BLUE[2]/EPI_B1N
TXD4P/LLV7N/BLUE[5]/EPI_B0P
A9
LVDS_TXD3N
LVDS_TXD4P
FRC_DQU[2] K17 R16
DDR3_DQMU/DDR2_DQU4 TXC4N/LLV2P
B13
B9
DDR3_DQU2/DDR2_DQU2 R17 C12 TXD4N/LLV7P/BLUE[4]/EPI_B0N LVDS_TXD4N
URSA5 H/W OPTION FRC_DQU[3] P17 H17
DDR3_DQL0/DDR2_DQU3
DDR3_DQL1/DDR2_DQL0
TXD0P/LLV3N
TXD0N/LLV3P
C13
+3.3V_FRC DDR3_DQU3/DDR2_DQU6 R15

DDR3_DQL2/DDR2_DQL6 TXD1P/LLVCLKN
B12
FRC_DQU[4] L17 J17

T17
DDR3_DQL3/DDR2_DQL7 TXD1N/LLVCLKP
A12
A11
DDR3_DQU4/DDR2_NC H16
DDR3_DQL4/DDR2_DQL3 TXD2P/LLV4N/EPI_B3P
B11
FRC_DQU[5] P16 D10
L/DIM_EDGE_32/37
DDR3_DQL5/DDR2_DQL2 TXD2N/LLV4P/EPI_B3N
T15 C10
DDR3_DQU5/DDR2_DQU1 G16
DDR3_DQL6/DDR2_DQL1
DDR3_DQL7/DDR2_DQL5
TXDCLKP/LLV5N/BLUE[1]/EPI_B2P
TXDCLKN/LLV5P/BLUE[0]/EPI_B2N
C11
MOD_GPIO0/VDD_ODD/HSYNC URSA_MODEL_OPT_0
FRC_DQU[6] K16 B10
D11
LVDS_EXT_URSA5
TXD3P/LLV6N/BLUE[3]
K15 A10
DDR3_DQU6/DDR2_DQU0 DDR3_DQU0/DDR2_DQU7 TXD3N/LLV6P/BLUE[2]/EPI_B1N MOD_GPIO1/VDD_EVEN/VSYNC URSA_MODEL_OPT_1
R5209 10K
R5213 10K
R5217 10K
N15 A9
R5205 10K
FRC_DQU[7] P15 K17

DDR3_DQU1/DDR2_DQML TXD4P/LLV7N/BLUE[5]/EPI_B0P
B9 D12
DDR3_DQU7/DDR2_DQMU P17
DDR3_DQU2/DDR2_DQU2
DDR3_DQU3/DDR2_DQU6
TXD4N/LLV7P/BLUE[4]/EPI_B0N
MOD_GPIO2/PWM13/GCLK4/LCK URSA_MODEL_OPT_2
D13
OPT
OPT
L17
DDR3_DQU4/DDR2_NC
P16 D10
K16
DDR3_DQU5/DDR2_DQU1 MOD_GPIO0/VDD_ODD/HSYNC
D11 MOD_GPIO3/PWM14/GCLK2/LDE 2D/3D_CTL
FRC_DQU[0-7] F14 P15
DDR3_DQU6/DDR2_DQU0
DDR3_DQU7/DDR2_DQMU
MOD_GPIO1/VDD_EVEN/VSYNC
MOD_GPIO2/PWM13/GCLK4/LCK
D12
DDR3_NC/DDR2_A13 MOD_GPIO3/PWM14/GCLK2/LDE
D13
R5253 3D-SG 33
+3.3V_FRC T16 F14
T16
DDR3_NC/DDR2_A13
3D_SYNC_RF
DDR3_NC/DDR2_DQL4 DDR3_NC/DDR2_DQL4
U12
PWM0/SCAN_BLK1
T12 U12 R5250 33
URSA_MODEL_OPT_0
D14
I2CM_SCL
PWM1/SCAN_BLK2
PWM0/SCAN_BLK1 PWM0
R5220 4.7K OPT
D15
P1
I2CM_SDA LPLL_FBCLK
G3
E17
T12 R5251 33
URSA_MODEL_OPT_1 P2
I2CS_SCL LPLL_OUTCLK
H3 PWM1/SCAN_BLK2 PWM1
D14 I2CS_SDA LPLL_REFIN
TESTPIN_1
TESTPIN_2
TESTPIN_3
TESTPIN_4
TESTPIN_5
TESTPIN_6
TESTPIN_7
TESTPIN_8
HW_RESET
I2CM_SCL
M0_SCLK
M0_MOSI
M1_SCLK
M1_MOSI
M2_SCLK
M2_MOSI
M3_SCLK
M3_MOSI
URSA_MODEL_OPT_2 R5221 4.7K OPT
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
SPI_CK
SPI_CZ
SPI_DI
SPI_DO
L/DIM_EDGE_42/47/55
D15 G3
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
I2CM_SDA LPLL_FBCLK
NC
2D/3D_CTL P1 E17
33 R5222
D6
D7
D8
D9
E6
E7
E8
E9
E10
E16
F3
F6
F7
F8
F9
G1
G2
G4
G5
G6
G7
G8
G9
G17
H1
H2
H4
H5
H6
H7
H8
H9
H10
H11
J4
J5
J6
J7
J8
J9
J10
J11
J12
J14
J16
K4
K5
K6
K7
K8
K11
L6
L7
L8
L11
L16
M6
M7
M8
M11
M13
N6
N7
N8
N17
P3
P4
P5
P6
P7
P12
U16
L9
J3
D1
D2
D3
E1
E2
E3
F1
F2
C17
D16
D17
E15
E14
E13
E12
F13
T9
U10
U9
T10
LVDS_S7M-PLUS
SCL2_+3.3V_URSA I2CS_SCL LPLL_OUTCLK

R5218 OPT 10K
P2 H3
10K
33 R5223
10K
10K
SDA2_+3.3V_URSA I2CS_SDA LPLL_REFIN

MODEL OPTION
TESTPIN_1
TESTPIN_2
TESTPIN_3
TESTPIN_4
TESTPIN_5
TESTPIN_6
TESTPIN_7
TESTPIN_8
HW_RESET
R5210 OPT
M0_SCLK
M0_MOSI
M1_SCLK
M1_MOSI
M2_SCLK
M2_MOSI
M3_SCLK
M3_MOSI
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
SPI_CK
SPI_CZ
SPI_DI
SPI_DO
PIN NAME PIN NO.
R5206
HIGH LOW
R5214
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
NC
MODEL_OPT_0 D10 L/DIM_10BLOCK L/DIM_16BLOCK
D6
D7
D8
D9
E6
E7
E8
E9
E10
E16
F3
F6
F7
F8
F9
G1
G2
G4
G5
G6
G7
G8
G9
G17
H1
H2
H4
H5
H6
H7
H8
H9
H10
H11
J4
J5
J6
J7
J8
J9
J10
J11
J12
J14
J16
K4
K5
K6
K7
K8
K11
L6
L7
L8
L11
L16
M6
M7
M8
M11
M13
N6
N7
N8
N17
P3
P4
P5
P6
P7
P12
U16
L9
J3
D1
D2
D3
E1
E2
E3
F1
F2
C17
D16
D17
E15
E14
E13
E12
F13
T9
33 U10
33 U9
T10
MODEL_OPT_1 D11 RESERVED RESERVED
33
MODEL_OPT_2 D12 LVDS_EXT_URSA5 LVDS_S7M_PLUS
NON USED
MODEL_OPT_3 D13 RESERVED RESERVED BCM35230 LVDS CHC/D
R5247
R5248
R5249
TXC0N
Debugging for URSA5 TXC0P
TXC1N
P5201 +3.3V_FRC
Q5202 TXC1P
12507WR-04L
SPI_SCLK
AO3407A
SPI_DI
M0_SCLK
M0_MOSI
M1_SCLK
M1_MOSI
M2_SCLK
M2_MOSI
M3_SCLK
SPI_CS
SPI_DO
M3_MOSI
TXC2N
S
TXC2P
URSA5_DEBUG
TXCCLKN
1 SW5201 C5212 URSA5_UO2_RESET
JS2235S R5255 TXCCLKP
G
22K 4.7uF
R5219 16V TXC3N
URSA5_UO2_RESET
10K URSA5_UO2_RESET TXC3P
2
OPT TXC4N
1 6 SDA2_3.3V
URSA5_DEBUG SCL2_3.3V
R5258 R5259 TXC4P
3 R5201 22 0 0 R5262
SCL2_+3.3V_DB URSA5_MP 2.2K TXD0N
URSA5_MP 2 5
SCL2_+3.3V_URSA SDA2_+3.3V_URSA URSA5_UO2_RESET TXD0P
URSA5_DEBUG R5260 R5261 C
R5202 22 URSA5_DEBUG TXD1N
4 0 0 R5254
SDA2_+3.3V_DB OPT OPT 4.7K
3 4 B Q5201 TXD1P
SCL2_+3.3V_DB SDA2_+3.3V_DB FRC_RESET 2SC3052
5 URSA5_UO2_RESET TXD2N
URSA5_UO2_RESET
R5256 E TXD2P
10K
OPT TXDCLKN
TXDCLKP
TXD3N
TXD3P
R5243 33
TXD4N
URSA5_UO3_RESET
TXD4P
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS MStar URSA5 2010. 08.18
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. FRC block 52 55
+1.5V_FRC_DDR
Close to DDR Pin

R5301
1K
1% +1.5V_FRC_DDR
+1.5V_FRC_DDR
MVREFCA DDR3 1.5V De-Cap Place near Memory
R5302
1K
1% C5301
0.1uF
0.1uF
C5305
C5303 C5304
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C5306
C5307
C5308
C5309
C5310
C5311
C5312
C5313
C5314
0.1uF 22uF
16V 10V
+1.5V_FRC_DDR Place the serail damping resistors
Place Close to DDR Pin in the middle of DRAM pattern
R5303
1K
1%
MVREFDQ
R5311 22
R5304 FRC_DMU DDR3_DMU AR5306
1K
1%
C5302
NON 21:9 Cinema(1600MHz) R5312 22
FRC_DQL[4]
FRC_DQL[6]
DDR3_DQL[4]
DDR3_DQL[6]
0.1uF FRC_DQSL DDR3_DQSL
FRC_DQL[2] DDR3_DQL[2]
IC5301 FRC_DQL[0] DDR3_DQL[0]
H5TQ1G63DFR-PBC DDR3_A[0-13] R5313 22
FRC_DQSLB DDR3_DQSLB 22
IC5301-*1 R5314 22
M8 N3 DDR3_A[0] FRC_DQSU DDR3_DQSU AR5307
H5TQ1G63DFR-RDC MVREFCA VREFCA A0
P7 DDR3_A[1] FRC_DQU[5] DDR3_DQU[5]
A1
P3 DDR3_A[2] R5315 22 FRC_DQU[3] DDR3_DQU[3]
21:9 Cinema(1866MHz) A2 FRC_DQSUB DDR3_DQSUB
H1 N2 DDR3_A[3] FRC_DQU[7] DDR3_DQU[7]
N3 M8 MVREFDQ VREFDQ A3
A0 VREFCA P8 DDR3_A[4] FRC_DQU[1] DDR3_DQU[1]
P7 A4 R5316 22
A1 P2 DDR3_A[5] FRC_DML DDR3_DML 22
P3 R5305 A5
A2 L8 R8 DDR3_A[6]
N2 H1 ZQ A6
A3 VREFDQ 240 R2 DDR3_A[7] R5317 22
P8 A7 FRC_ODT DDR3_ODT AR5308
A4 1% T8 DDR3_A[8]
P2 A8 FRC_DQU[4] DDR3_DQU[4]
A5 B2 R3 DDR3_A[9]
R8 L8 VDD_1 A9 R5318 22 FRC_DQU[6] DDR3_DQU[6]
A6 ZQ D9 L7 DDR3_A[10] FRC_RASB DDR3_RASB
R2 VDD_2 A10/AP FRC_DQU[2] DDR3_DQU[2]
A7 G7 R7 DDR3_A[11]
T8 VDD_3 A11 FRC_DQU[0] DDR3_DQU[0]
A8 K2 N7 DDR3_A[12] R5319 22
R3 B2 VDD_4 A12/BC FRC_CKE DDR3_CKE 22
A9 VDD_1 K8 T3 DDR3_A[13] Place Close to DDR Pin
L7 D9 VDD_5 A13
A10/AP VDD_2 N1
R7 G7 VDD_6 R5320 22
A11 VDD_3 N9 M7 FRC_MCLK DDR3_MCK AR5309
N7 K2 VDD_7 A15 R5309
A12/BC VDD_4 R1 56 FRC_DQL[3] DDR3_DQL[3]
T3 K8 VDD_8 DDR3_MCK
NC_6 VDD_5 R9 M2 R5321 22 FRC_DQL[1] DDR3_DQL[1]
N1 VDD_9 BA0 DDR3_BA0 R5310 FRC_MCLKB DDR3_MCKB
VDD_6 N8 FRC_DQL[5] DDR3_DQL[5]
M7 N9 BA1 DDR3_BA1 56
NC_5 VDD_7 M3 C5315 DDR3_MCKB FRC_DQL[7] DDR3_DQL[7]
R1 BA2 DDR3_BA2 R5322 22
VDD_8 A1 DDR3_MCK 0.01uF FRC_DDR3_RESETB DDR3_RESETB 22
M2 R9 VDDQ_1
R5307
A8 J7 25V
BA0 VDD_9
OPT
150
N8 VDDQ_2 CK
BA1 C1 K7 AR5301
M3 VDDQ_3 CK
BA2 C9 K9 DDR3_MCKB FRC_A[10] DDR3_A[10]
A1 VDDQ_4 CKE
VDDQ_1 D2 DDR3_CKE FRC_BA1 DDR3_BA1
J7 A8 VDDQ_5
CK VDDQ_2 +1.5V_FRC_DDR E9 L2 FRC_A[12] DDR3_A[12]
K7 C1 VDDQ_6 CS
CK VDDQ_3 F1 K1 FRC_A[4] DDR3_A[4]
K9 C9 VDDQ_7 ODT DDR3_ODT
CKE VDDQ_4 H2 J3 22
D2 VDDQ_8 RAS DDR3_RASB +1.5V_FRC_DDR
VDDQ_5 H9 K3
L2 E9 VDDQ_9 CAS DDR3_CASB
CS VDDQ_6 L3
K1 F1 WE DDR3_WEB AR5302
ODT VDDQ_7 J1 R5308 0
J3 H2 NC_1 FRC_A[6] DDR3_A[6]
RAS VDDQ_8 J9 T2
K3 H9 NC_2 RESET DDR3_RESETB FRC_A[8] DDR3_A[8]
CAS VDDQ_9 L1
L3 NC_3 FRC_A[1] DDR3_A[1]
WE L9
J1 NC_4 FRC_A[11] DDR3_A[11]
NC_1 T7 F3
T2 J9 NC_6 DQSL DDR3_DQSL 22
RESET NC_2 G3
L1 DQSL DDR3_DQSLB
NC_3
L9
NC_4 A9 C7 AR5303
F3 T7 VSS_1 DQSU DDR3_DQSU
DQSL NC_7 B3 B7 FRC_A[0] DDR3_A[0]
G3 VSS_2 DQSU DDR3_DQSUB
DQSL E1 FRC_A[2] DDR3_A[2]
VSS_3
G8 E7 FRC_A[13] DDR3_A[13]
C7 A9 VSS_4 DML DDR3_DML
DQSU VSS_1 J2 D3 DDR3_DQL[0-7] FRC_A[9] DDR3_A[9]
B7 B3 VSS_5 DMU DDR3_DMU
DQSU VSS_2 J8 22
E1 VSS_6
VSS_3 M1 E3 DDR3_DQL[0]
E7 G8 VSS_7 DQL0
DML VSS_4 M9 F7 DDR3_DQL[1]
D3 J2 VSS_8 DQL1 AR5304
DMU VSS_5 P1 F2 DDR3_DQL[2]
J8 VSS_9 DQL2
VSS_6 P9 F8 DDR3_DQL[3]
E3 M1 VSS_10 DQL3 FRC_A[7] DDR3_A[7]
DQL0 VSS_7 T1 H3 DDR3_DQL[4]
F7 M9 VSS_11 DQL4 FRC_A[5] DDR3_A[5]
DQL1 VSS_8 T9 H8 DDR3_DQL[5]
F2 P1 VSS_12 DQL5 FRC_A[3] DDR3_A[3]
DQL2 VSS_9 G2 DDR3_DQL[6]
F8 P9 DQL6 22
DQL3 VSS_10 H7 DDR3_DQL[7]
H3 T1 DQL7
DQL4 VSS_11 B1
H8 T9 VSSQ_1
DQL5 VSS_12 B9 D7 DDR3_DQU[0] AR5305
G2 VSSQ_2 DQU0
DQL6 D1 C3 DDR3_DQU[1] FRC_BA2 DDR3_BA2
H7 VSSQ_3 DQU1
DQL7 D8 C8 DDR3_DQU[2] FRC_BA0 DDR3_BA0
B1 VSSQ_4 DQU2
VSSQ_1 E2 C2 DDR3_DQU[3] FRC_WEB DDR3_WEB
D7 B9 VSSQ_5 DQU3
DQU0 VSSQ_2 E8 A7 DDR3_DQU[4] FRC_CASB DDR3_CASB
C3 D1 VSSQ_6 DQU4
DQU1 VSSQ_3 F9 A2 DDR3_DQU[5] 22
C8 D8 VSSQ_7 DQU5
DQU2 VSSQ_4 G1 B8 DDR3_DQU[6]
C2 E2 VSSQ_8 DQU6
DQU3 VSSQ_5 G9 A3 DDR3_DQU[7]
A7 E8 VSSQ_9 DQU7
DQU4 VSSQ_6
A2 F9
DQU5 VSSQ_7
B8 G1
DQU6 VSSQ_8 DDR3_DQU[0-7]
A3 G9
DQU7 VSSQ_9

DDR3 4Mbit 53 55
CORE +1.26V_FRC TYPICAL 980mA
+3.3V_FRC
+1.5V_FRC TYPICAL 350mA +1.5V_FRC_DDR
+12V +3.3V_FRC
IC5401 +1.26V_FRC
R5405 IC5403
AOZ1072AI 10K
L5403 AP7173-SPG-13 HF(DIODES)
POWER_ON/OFF2_2
L5402 3.6uH R5409 OPT10K
NR8040T3R6N [EP]
CIC21J501NE PGND LX_2
1 8 1 8 R1
THERMAL
IN OUT R5414
VIN LX_1 4.3K
2 7 R5406 1%
9
3.3K 2 7
C5406 C5407 R5404 1%
0.1uF 1uF 20K PG FB
AGND
3 2A 6
EN 10V
OPT
R5407
R1
3 6 R5415
3.9K C5412 C5414 3.9K
C5402 C5404 1% 22uF 22uF VCC SS 1%
10uF 10uF FB COMP 10V 10V R5413
25V 25V 4 5 C5410 10K 4 5 R2
R5402 C5408 100pF C5419 R5416 C5420 C5421
20K 3300pF 50V EN GND 560pF 1K 10uF 10uF
Placed on SMD-TOP 50V 1% 16V 16V
OPT EAN41406705
C5416 C5417
10uF 0.1uF
16V 16V C5418
R5408 1uF
12K 10V
1% R2
Vout=(1+R1/R2)*0.8 Vout=0.6*(1+R1/R2)
+1.5V of DDR&URSA5 uses same power line
+3.3V_FRC
+12V
TYPICAL 300mA
L5401
CIC21J501NE
+3.3V_FRC
IC5402
AOZ1072AI-3
L5404
3.6uH
PGND LX_2 NR8040T3R6N
1 8
VIN LX_1
2 7 R5410
C5405 27K
1%
0.1uF R5403
AGND
3 2A 6
EN 10K POWER_ON/OFF2_2
R1
C5413
22uF
C5415
22uF
R5411 10V 10V
C5401 C5403 4.3K
1%
10uF 10uF FB COMP
25V 25V 4 5
C5411
R5401 C5409
20K 2200pF 100pF
EAN60922902 50V
OPT
R5412
10K
1% R2
Vout=0.8*(1+R1/R2)

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR URSA5 Power Block 54 55
THE
M1-*3 M1-*2 M1-*1 M1
MDS62110206 MDS62110204 MDS62110210 MDS62110208
GASKET_6.5T GASKET_5.5T GASKET_5.0T GASKET_4.5T
M2-*3 M2-*2 M2-*1 M2
MDS62110206 MDS62110204 MDS62110210 MDS62110208

M3-*3 M3-*2 M3-*1 M3

MDS62110206 MDS62110210 MDS62110208
MDS62110204
GASKET_6.5T GASKET_5.0T GASKET_4.5T
GASKET_5.5T

M4-*3 M4-*2 M4-*1 M4
MDS62110206 MDS62110204 MDS62110210 MDS62110208

THE CRITICAL COMPONENTS IN THE

M5-*3 M5-*2 M5-*1 M5
MDS62110206 MDS62110204 MDS62110210 MDS62110208

M6-*1 M6
M6-*3 M6-*2
SMD GASKET 4.5T

MDS62110208
SMD GASKET 6.5T

MDS62110210
Copyright © 2011 LG Electronics. Inc. All rights reserved.

SMD GASKET 5.0T
MDS62110206
SMD GASKET 5.5T

MDS62110204
SMD GASKET
GASKET_5.5T
M7-*3 M7-*1 M7
MDS62110206 M7-*2 MDS62110210 MDS62110208

GASKET_6.5T MDS62110204 GASKET_5.0T GASKET_4.5T
GASKET_5.5T
M8-*1 M8
M8-*3
M8-*2 MDS62110208
MDS62110206 MDS62110210
MDS62110204 GASKET_5.0T GASKET_4.5T
GASKET_6.5T
GASKET_5.5T
M9-*3 M9-*1 M9
MDS62110206 M9-*2 MDS62110210 MDS62110208
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS

MDS62110204
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

GASKET_5.5T

M10-*3 M10-*1 M10

MDS62110206 M10-*2 MDS62110210 MDS62110208
MDS62110204
SYMBOL MARK OF THE SCHEMETIC.

M11-*3 GASKET_5.5T M11-*1 M11
MDS62110206 M11-*2 MDS62110210 MDS62110208
MDS62110204
GASKET_5.5T
M12-*3 M12-*1 M12
MDS62110206 M12-*2 MDS62110210 MDS62110208

MDS62110204
GASKET_5.5T
GASKET3.5T_HEATSINK M1-*6 M1-*4

M1-*5
MDS62110213 MDS62110214 MDS62110205
GASKET_9.5T MDS62110209 GASKET_7.5T
M20
GASKET_8.5T
M2-*6 M2-*5 M2-*4
GASKET3.5T_HEATSINK MDS62110214 MDS62110209 MDS62110205
MDS62110213
M21 M3-*6 M3-*4
MDS62110214 M3-*5 MDS62110205
GASKET3.5T_HEATSINK GASKET_8.5T
MDS62110213 M4-*6
M4-*4
M22 MDS62110214 M4-*5
MDS62110205
GASKET_8.5T
GASKET3.5T_HEATSINK M5-*6 M5-*4
MDS62110213 MDS62110214 M5-*5 MDS62110205
GASKET_9.5T GASKET_7.5T
M23 MDS62110209
GASKET_8.5T
M6-*6
M6-*4
M6-*5
MDS62110214
SMD GASKET 8.5T
SMD GASKET 9.5T

SMD GASKET 7.5T
MDS62110205
GASKET_8.5T
M7-*6 M7-*4
MDS62110214 M7-*5 MDS62110205
MDS62110209
GASKET_8.5T
M8-*6
M8-*4
MDS62110214 M8-*5 MDS62110205
MDS62110209
GASKET_8.5T
M9-*6 M9-*4
MDS62110214 M9-*5 MDS62110205
MDS62110209
M10-*6 GASKET_8.5T
M10-*4
MDS62110214 MDS62110205
M10-*5
MDS62110209
M11-*6 GASKET_8.5T M11-*4
MDS62110214 M11-*5 MDS62110205
MDS62110209
M12-*6 GASKET_8.5T
M12-*4
MDS62110214 MDS62110205
M12-*5
MDS62110209
GASKET_8.5T
BCM35230
SMD GASKET
56
56
2010. 09. 18
LGE Internal Use Only

RGB/ PC AUDIO/ SPDIF/ EARPHONE/ RS232C
DUAL COMPONENT
+5V_Normal
RGB PC D3810 D3804,D3805,D3806
KDS184 D3807,D3808,D3813 1ST : EAH39491601, 2ND : EAH33945901
A2 D3814
C
A1 D3810 1ST : 0DD184009AA, 2ND : 0DSIH00028A
JK3803
+3.3V_Normal KJA-PH-0-0177
+5V_Normal GND 5
Q3801 1ST : 0TRIY80001A, 2ND : 0TR387500AA
IC3801
74F08D R3816
R3809 R3810 R3813
IC3802 2.7K L 4
D0A VCC AT24C02BN-SH-T 2.7K 2.7K 10K HP_LOUT
1 14
R3858
R3856 22 1K
A0 VCC DETECT 3
D0B
2 13
D3B 1 8 HP_DET
DSUB_VSYNC
A1 WP
R3857 22 Q0 D3A
2 7
EDID_WP R 1
3 12 HP_ROUT
A2 SCL 22 R3812
DSUB_HSYNC 3 6
RGB_DDC_SCL
R3850 0 D1A
4 11
Q3
GND SDA 22 R3811
4 5
OPT RGB_DDC_SDA
R3851 0 D1B
5 10
D2B R3852 0
OPT
Q1
6 9
OPT
D2A R3853 0
C3812
18pF
C3813
18pF EARPHON JACK
50V 50V
OPT
GND Q2
7 8
OPT
R3802 D3804 C3810
10K 30V 22pF
50V +3.3V_Normal
EARPHONE AMP L3803

OPT D3811 BLM18PG121SN1D
R3801 Closed to JACK D3809
D3805 LPF READEY
10K C3811 5.6V
30V 5.6V OPT (For H/P Noise Improvement)
22pF OPT
50V C3824 C3826
L3806 10uF 0.1uF
BLM15BD121SN1 10V 16V
R3862 L3804
0 BG2012B080TF
DSUB_B+ ESD_COMMON HP_LOUT
C3807 D3808 C3829
R3807 Close to the IC C3823
47pF 30V 0.22uF
75 1uF
5.6V 50V 10V
10V
D3808-*1
ESD_CERADIODE
OUTL
SGND
VDD
+3.3V_Normal
EN
R3825
C3827 100K
C3818 16 15 14 13 2.2uF OPT
L3807 1uF 10V R3826 OPT
10V INL- HPVDD 4.7K R3827
BLM15BD121SN1 1 12
HP_LOUT_N 0
C3819
DSUB_G+ 1uF C
ESD_COMMON +3.3V_Normal 10V INL+ CPP R3828
R3806 C3808 D3806 2 11 1K
HP_LOUT_P Q3801 B
75 47pF 30V C3820 IC3804 C3828 2SC3052 SIDE_HP_MUTE
5.6V 50V 1uF
INR+ TPA6132A2 PGND 2.2uF
D3806-*1 R3814 10V 10V
ESD_CERADIODE 3 10 E
10K HP_ROUT_P
C3821
1uF
DSUB_DET 10V INR- CPN
1K R3815 4 EAN60724701 9
HP_ROUT_N
L3808
BLM15BD121SN1 5 6 7 8
R3819
D3812 D3812-*1
4.7K
R3817
5.6V
4.7K
5.6V
OUTR
G0
G1
HPVSS
DSUB_R+ ESD_COMMON ESD_COMMON ESD_CERADIODE
C3809 D3807
R3808 47pF 30V L3805
5.6V R3863
R3820
75 BG2012B080TF
R3818
50V 0
OPT
D3807-*1
OPT
ESD_CERADIODE HP_ROUT
C3825 C3830
GREEN_GND
DDC_CLOCK
DDC_DATA
BLUE_GND
SYNC_GND
2.2uF 0.22uF
RED_GND
DDC_GND
10V
H_SYNC
V_SYNC
10V
GND_2
GREEN
GND_1
BLUE
RED
NC
SPG09-DB-010
SHILED
11
12
13
14
15
16
P3801
10
6
RS232C
1
10
5
9
0 R3829
IR_OUT 4
IR_OUT
R3860 8
100 JP3809
3
+3.5V_ST
7
R3859
100 JP3808
ESD_COMMON 2
D3814
PC AUDIO IC3803
ESD_COMMON
30V
6
D3813
MAX3232CDR 1
JK3801 30V
PEJ027-04
0.1uF C3814 C1+ VCC
3 E_SPRING 1 16 SPG09-DB-009
D3813-*1
D3814-*1
+3.5V_ST ESD_CERADIODE P3802
ESD_CERADIODE
6A T_TERMINAL1 V+ GND 5.6V
0.1uF C3815 2 15 5.6V
R3854
7A B_TERMINAL1 ESD_COMMON 22
PC_R_IN C1- DOUT1 R3830 R3831
3 14
D3802 4.7K 4.7K
4 R_SPRING C3803 C3806
AMOTECH R3804 OPT
470K 560pF 560pF C2+ RIN1 OPT
5.6V 50V 50V 0.1uF C3816 4 13
5 T_SPRING
R3821
R3855 C2- ROUT1 0
7B B_TERMINAL2 ESD_COMMON 22 5 12
PC_L_IN BCM_RX
T_TERMINAL2 D3801 R3822

6B AMOTECH C3802 C3805 0.1uF C3817 V- DIN1 0
R3803 6 11
5.6V 470K 560pF 560pF
50V 50V NEC_RXD
DOUT2 DIN2 R3823

7 10 0
BCM_TX
RIN2 ROUT2 R3824
8 9 0
NEC_TXD
EAN41348201
+3.3V_Normal
SPDIF OUT GND

1
Fiber Optic
JST1223-001
JK3802
R3805 VCC
2
2.7K
R3861
0 VINPUT
3
SPDIF_OUT
C3804
4
D3803
30V 0.1uF
16V
FIX_POLE
OPT
HIGH : SELECT X1, Y1, SELECT MAIN TX/RX

LOW : SELECT X0, Y0, SELECT MICOM TX/RX

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LV7 COMM JACK 99 99

LG 47LW470S-ZB Chassis LD12P

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Formati disponibili

LG 47LW470S-ZB Chassis LD12P

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Formati disponibili

Internal Use Only

North/Latin America http://aic.lgservice.com

MODEL : 47LW470S 47LW470S-ZB

P/NO : MFL67002346 (1107-REV00) Printed in Korea

PRODUCT SAFETY ................................................................................. 3

ADJUSTMENT INSTRUCTION .............................................................. 10

EXPLODED VIEW .................................................................................. 18

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

IMPORTANT SAFETY NOTICE

General Guidance Leakage Current Hot Check (See below Figure)

Before returning the receiver to the customer, AC Volt-meter

always perform an AC leakage current check on the exposed

1. Application range 3. Test method

1) Temperature: 25 ºC ± 5 ºC(77 ºF ± 9 ºF), CST: 40 ºC ± 5 ºC

4. Model General Specification

DTV (MPEG2/4, DVB-T2): 5 countries

DTV (MPEG2/4, DVB-C): 10 countries

DTV (MPEG2/4, DVB-S) : 31 countries

Analog Only - 5 countries

Supported satellite : 22 satellites

6. RGB Input (PC)

(2) HDMI Input (1.3)

(4) USB Input

(7) 3D Input mode

In case of keeping module is in the circumstance of 0 °C, it

In case of keeping module is in the circumstance of below -

Connect: PCBA Jig-> RS-232C Port== PC-> RS-232C Port

2) MAC Address & CI+ key & Widevine key download

(2) Method & notice

d. Check the model name Instart menu. -> Factory name

(1) Using RS232 0x03 90 40 A9 C0 B3 00 02 3A 80 18 71 38 2D 40 58 2C

Transmission [A][I][ ][Set ID][ ][20][Cr] [O][K][X] or [NG] 0x06 3E 1E 53 10 00 0A 20 20 20 20 20 20 ⓓ

(2) Check the menu on in-start.

Pat t ern Generat o r

ALL 0001 0100 Analog * If TV internal pattern is used, not needed

0001 0100 Digital

A If internal pattern is not available, use RF input. In EZ

A Adj. condition and cautionary items

2) When 3D OSD appear automatically, then select green key.

Fig . 3 Connect the Dongle

4.4. EYE-Q function check

4.5.2. RF emitter inspection

<IR Emitter inspection>

(2) If RF emitter signal is correctly received to RF receiver, the

5. Tool Option selection

5.1. Ship-out mode check(In-stop)

Only for training and service purposes

Copyright © 2011 LG Electronics. Inc. All rights reserved.

PC- RGB Rear I2C Sub Micom

LGE Internal Use Only

2 47 NC_3 NC_24 CI_ADDR[7]

- Low : Write Protection 21 28

NC_12 NC_19 CI_ADDR[6]:

RGB_DDC_SDA GND SDA

TXOUT0_U1P TXA3N AE6

HDMI0_HTPLG_OUT TXOUT0_U2P 0.1uF AB5 GND_1 X-TAL_2

BCM REFRENCE is 562ohm

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

0.22uF 0.1uF 0.01uF IN OUT IN OUT 22uF

+2.5V_BCM35230 EPHY_VDD25 +2.5V_BCM35230

+2.5V_BCM35230 VAFE3_VDD25 +2.5V_BCM35230 PLL_VAFE_AVDD25

C254 C257 C264 C268 POWER 3.3V

HIGH LOW IC101