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  • Decoder 2to4 Vivado

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    Amina Ghardallou
    60 visualizzazioni6 pagine
    This document provides tutorials and exercises for digital system projects using a Xilinx FPGA board. It summarizes the steps to design a 2-to-4 decoder in Vivado, including creating a new project, adding VHDL and constraint files, running synthesis and implementation, programming the FPGA board, and verifying the design works as expected by toggling switches and observing LEDs. An exercise is then provided to modify the design into a 4-to-16 decoder.

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    decodeur in vivado

    Titolo originale

    decoder_2to4_vivado

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    This document provides tutorials and exercises for digital system projects using a Xilinx FPGA board. It summarizes the steps to design a 2-to-4 decoder in Vivado, including creating a new project, adding VHDL and constraint files, running synthesis and implementation, programming the FPGA board, and verifying the design works as expected by toggling switches and observing LEDs. An exercise is then provided to modify the design into a 4-to-16 decoder.

    Copyright:

    © All Rights Reserved
    Scarica in formato PDF, TXT o leggi online su Scribd
    Segnala contenuti inappropriati
    60 visualizzazioni6 pagine

    Decoder 2to4 Vivado

    Caricato da

    Amina Ghardallou
    This document provides tutorials and exercises for digital system projects using a Xilinx FPGA board. It summarizes the steps to design a 2-to-4 decoder in Vivado, including creating a new project, adding VHDL and constraint files, running synthesis and implementation, programming the FPGA board, and verifying the design works as expected by toggling switches and observing LEDs. An exercise is then provided to modify the design into a 4-to-16 decoder.

    Copyright:

    © All Rights Reserved
    Scarica in formato PDF, TXT o leggi online su Scribd
    Segnala contenuti inappropriati
    di 6

    Digital System Projects

    Department of Electrical and Computer Engineering

    Digital Systems Tutorials and Exercises


    By Prawat Nagvajara

    Tutorial 1: 2-to-4 Decoder (Fig. 1)

    Decoder Z0
    X1
    X0 Z1
    Z2

    En Z3

    Fig.1 Decoder Block Diagram

    1. Start Xilinx Vivado

    1.1 Create a new folder, for instance, named xilinx_projects, in write permitted drive for your future
    digital design on FPGA projects.

    1.2 Go to All Programs > Xilinx Design Tools and launch Vivado. If it does not show in All Programs
    menu it is at C:\Xilinx\Vivado\2014.4\bin\vivado.bat

    2. Create New Project

    2.1 Quick Start -> Create New Project


    2.2 Create a New Vivado Project -> Next
    Project name: decoder
    Project location:
    The location is in the folder created in 1.1
    Checked on Create Project Subdirectory -> Next
    2.3 Project Type: RTL Project, check “Do not specify sources at this time” -> next
    2.4 Default Part

    1
    Digital System Projects

    2.5 New Project Summary -> Finish

    2.6 View Project Setting. Check if the target language is VHDL and the Part is xc7a35tcpg236-1.

    3. VHDL Source File

    3.1 Project Manager -> Add Sources -> Add or Create Design Sources -> Create Files
    File Name: decoder -> Finish
    Define Module -> OK
    “Module Ddefinition…” -> yes

    2
    Digital System Projects

    3.2 Open decoder.vhd

    Maximize editor pane


    Edit code and save file

    4. Design Constraints File

    4.1 Add Sources -> Add or create Constraints -> Next


    4.2 Download from digilentinc.com -> Basys3 -> Support Documents -> Basys3 Master XDC File for Vivado
    designs -> Download

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    Digital System Projects

    4.3 Add Files-> Basys3_Master.xdc


    4.4 Open Basys3_Master.xdc maximize editor (change and replace is CTRL-r).

    The design sources pane looks as follows

    The design constraints file is as follows,

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    Digital System Projects

    5. Synthesis, Implementation and Generate Bitstream

    5.1 Run synthesis


    5.2 Run Implementation
    5.3 Generate Bitstream

    6. Program FPGA
    6.1 Connect Basys 3 board (micro USB) and switch power
    6.1 Open Hardware Manual
    6.2 Open Target -> Open New Target

    6.3 Program Device

    7. Verify Correctness
    7.1 Refer to the design constraints what switches are x(1), x(0) and en and what leds are z(0), …, z(3).

    Exercise

    Problem Statement: Design a 4-to-16 decoder.

    1. Use the array type syntax (Bhasker 3.3 Array Type) for assigning a vector with a single ‘1’. For example
    i) (5 => ‘1’, others => ‘0’) is a vector with the bit at index 5 equal to a ‘1’ and other bits are ‘0’s.
    ii) (others => ‘0’) is a vector with all ‘0’s.

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    Digital System Projects

    The new 14-to16 decoder description has a case statement for x like,
    case x is
    when “0000” => Z <= (0 => ‘1’, others => ‘0’);
    when “0001” => Z <= (1 => ‘1’, others => ‘0’);
    when “0010” => Z <= (2 => ‘1’, others => ‘0’);
    …
    when “1111” => Z <= (15 => ‘1’, others => ‘0’);
    end case;

    2. Use” find and replace” feature of the editor for the LEDs assignment in the XDC file.

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