EE360: Digital Design I

Design Problem

Design a circuit that performs some arithmetic operations for the 7-bit signed 2's-
complement numbers A and B. The circuit inputs and outputs are:

1. The control inputs S2S1S0 that specify the operation performed by the circuit as
defined in the table 1 below.
2. A 7-bit input X that is used to upload both values of A and B into internal
registers.
3. A 2-bit control input R that is used to direct the 7-bit input X to one of the
internal registers A or B as defined in table 2:
4. The circuit has a 14-bit signed 2's-complement output (Z).

Table 1
Control Bits
Operation Notes
𝑺𝟐 𝑺𝟏 𝑺𝟎
000 𝐴+𝐵
001 𝐴−𝐵
010 −𝐴 − 𝐵
011 |𝐴 |
100 𝐴∗𝐵
𝑍 = 1 (𝐴 > 𝐵 )
101 𝐶𝑜𝑚𝑝𝑎𝑟𝑒(𝐴, 𝐵) 𝑍 = 2 (𝐴 < 𝐵 )
𝑍 = 3 (𝐴 = 𝐵 )
M is signed 2’s-complement binary,
110 𝐴 ∗ 2𝑀 Where M = B2..0
When M is negative, the fraction is truncated
111 Not used

Table 2
R1R0 Action
00 No Action
01 X is loaded into register A
10 X is loaded into register B
11 X is loaded into both registers

R 2
A Apply the
X 7 required 14 Z

B Operation
on A and B

3
S
 EE360: Digital Design I
Design Problem

Requirements and Report guideline

1. You need to implement circuit using the FPGA board given to your team.
a. Use switches SW6..0 for the input X
b. Use switches SW9..7 for the input S.
c. Use Buttons BT1..0 for the input R.
d. Use the seven segments for the output
i. Use HEX4 segment for the output sign
ii. Use HEX3..0 segments for the operation output value
e. Use the circuits binary2bcd that will be given to you (as Verilog
modules) to display you circuit output Z into the seven segments display.
2. Your report should at least contain the following:
a. Problem definition.
b. Discussion of at least two alternative designs, and select the best based
on clear criteria (i.e., scalability, and performance). You must provide
the details of the selected design.
i. The circuit block diagram where you show all the modules and
their interconnections.
ii. The detailed design of each module.
iii. You should also discuss design alternatives for the circuit
modules.
c. Verilog modules, and simulation results for all modules, and for the
whole circuit (for the selected design).
d. References.