Final Report

Adam Christa 47362657 ECE 5387 Digital Systems Design Final Project Report 12/10/19
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ECE 5387 Final Project
Report
Table of Contents:
Implementations: Pages 2-5

Dataflow Diagrams: Pages 5-8
Resource Scheduling: Pages 8-10
Datapath: Page 10
Controller: Page 11
Test Vector Criteria: Page 12
Claims/Analysis: Page 13-14
Appendix 1 (Non-testbench): Page 15-30
Appendix 2 (Testbenches): Page 30-37
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Implementations
Signed Adder- My signed 8 bit binary adder functions quite similarly to a standard unsigned 8
bit binary adder. In order to create a signed 8 bit binary adder, I first utilized the XOR gate on the
second addend bits coupled with a carry in bit to produce a modified addend. The carry in bit
corresponded to the operation I desired to be performed. If the operation desired was addition,
the carry in bit was 0. If the operation desired was subtraction, the carry in bit was 1. Source
code of this process is shown below. FIG.1
Next, I utilized a series of ripple full adders in order to execute the RTL logic for the
adder. I implemented a full adder using case statements within an always block. The case
statement performs similarly to a truth table. The source code for the logic of the full adder
should be shown below. FIG.2

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In the full adders, I utilized the first addend bits and the second modified addend bits as the
A and B inputs in the full adder. In the first full adder, I use the proper carry in based on the
desired operation. The source code for the full adders is shown below. FIG.3
Finally, I needed to calculate the signed 7th bit of the signed adder. In order to do
this, I utilized a ternary statement to assign the 7th bit based on whether or not there was
overflow, the desired operation (mode), and a difference in the signs of the two addends. The
statement is crucial because it decides whether or not the sum is positive or negative. The source
code for the ternary assignment should be shown below. FIG.4
assign result[7] = (!overflow2 && isOneNegative && !mode) || (overflow2 && !isOneNegative && !mode) || (!
overflow3 && isOneNegative && mode) || (overflow3 && !isOneNegative && mode) ? 1'b1 : 1’b0;
I now have all of the bits necessary for the signed adder to be fully operational.
Signed Multiplication- My signed truncated binary multiplier utilizes Booth’s algorithm for
signed binary multiplication in order to meet functionality standards. Booth’s algorithm gives a
procedure for multiplying binary integers in signed 2’s complement representation in efficient
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way, i.e., less number of additions/subtractions required. It operates on the fact that strings of 0’s
in the multiplier require no addition but just shifting and a string of 1’s in the multiplier from bit
weight 2^k to weight 2^m can be treated as 2^(k+1 ) to 2^m. Booth’s algorithm requires
examination of the multiplier bits and shifting of the partial product. Prior to the shifting, the
multiplicand may be added to the partial product, subtracted from the partial product, or left
unchanged [1]. In my version of Booth’s algorithm implementation, I utilize a ternary
assignment operator in order to determine which operation to perform on the partial product prior
to shifting. Source code for the ternary assignment operator is shown below. FIG.5
In order to receive the final correct answer, I needed to have eight of these ternary
assignment “if-else” operators. A figure describing process should be shown below [1]. FIG.6
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Unfortunately, this means that I must compute the entire 16 bit product in order to
achieve correct functionality of my code. However, I believe my implementation of Booth’s
algorithm for a truncated signed algorithm is a better solution than utilizing a Wallace Tree or
any other implementation that only computes the most significant 8 bits because:
1. Booth’s algorithm is more intuitive for another programmer to understand since it is
(basically) repeated addition.
2. The code itself is much more organized into 8 identical ternary operators instead of 64
“AND” gates
3. The multiplier utilizes less logic
Since my implementation of the signed multiplier computes all 16 bits, I retrieved only
the most significant 8 bits in order to determine my final product. If you would like a more in
depth explanation of Booth’s algorithm, I would suggest perusing the wikipedia page on the
subject: https://en.wikipedia.org/wiki/Booth%27s_multiplication_algorithm
Dataflow Diagrams
Before drawing my first data flow diagram, I calculated the minimum number of
adders and multipliers necessary for the entire computation. According to the project guidelines,
in order to receive all of the inputs, 12 clock cycles are necessary. Additionally, 4 more clock
cycles are required to compute the f output vector. Therefore, the total number of clock cycles
required at maximum is 16. According to the project guidelines, 4 multiplications will be
necessary and 8 additions will be necessary due to each input and output vector being made of 4
indices. I can now determine the minimum number of adders and multipliers necessary. FIG.7/8
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Since I now know the minimum number of multipliers and adders, I can create a
version of the data flow diagram. FIG.9

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According to the project guidelines, the maximum latency that our design is
allowed to have is 15 clock cycles. In FIG.9, it is clear that it will require 16 clock cycles for the
program to reach its final output from the first input. Therefore, FIG.9 is an incorrect data flow
diagram. In order to meet specifications, I will need to increase the number of adders and/or
multipliers I am using. Upon inspection of FIG.9, it is evident that if I had 2 adders instead of 1, I
could decrease the maximum number of clock cycles necessary because I could compute F1 after
E1 is computed (in clock cycle 10). Therefore, I will now create a new data flow diagram that
utilizes 2 adders and 1 multiplier instead of 1 adder and 1 multiplier. FIG.10

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In the above data flow diagram of FIG.10, the number of clock cycles from first
input to final output is 13 clock cycles. Therefore, the latency of the FIG.10 diagram is 13 clock
cycles. Since the FIG.10 data flow diagram is below the maximum 15 clock cycles, I will be
attempting to utilize this data flow diagram in my implementation.
Resource Scheduling
In FIG.7/8 above, I determined that the minimum number of resources I required
was 1 adder and 1 multiplier. Therefore, I created a resource scheduling chart that utilized 1
adder and 1 multiplier to meet functionality. FIG.11

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In the above FIG.11, the latency is 16 clock cycles because it requires 16 clock
cycles for the data path to extend from the first input of A1 to the final output of F4.
Additionally, the initiation rate is 8 clock cycles because the minimum number of clock cycles
between the first input of 1 test vector and the first input of the next test vector is 8 clock cycles.
Unfortunately, this does not meet specifications because of the fact that the maximum latency we
are allowed to have is 15 clock cycles. In FIG.9/10 above, I determined from the data flow
diagram that having 2 adders and 1 multiplier allows the latency to reach 13 clock cycles, which
is below the maximum number of clock cycles allowed. Therefore, I will need to create a second
resource scheduling chart that has 2 adders and 1 multiplier. FIG.12

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In FIG.12, my latency is now 13 clock cycles because it requires 13 clock cycles for
the data path to extend from the first input of A1 to the final output of F4. Additionally, the
initiation rate is 4 clock cycles because the minimum number of clock cycles between the first
input of 1 test vector and the first input of the next test vector is 4 clock cycles. Since this does
meet specifications, I will be attempting to use the resource management in FIG.12 for the
implementation of my final design.
Datapath Inputs/Outputs
Datapath Diagram
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Controller Inputs/Outputs
Controller ASM
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Test Vector Criteria
According to the project guidelines, I am required to have at least 10 test vectors in
order to demonstrate that my design is functional.
1. (First Vector) For my first test vector, I simply chose the decimal value of 1 (8’b00000001)
for each input vector. The result of every input having the decimal value of 1 is easy to
compute in one’s head (the result should be zero). Therefore, I use my first test vector to
make sure all of the values of a1-4, b1-4, and d1-4 are all producing the same result.
2. (Vectors 2/3) For my second and third test vector, I chose values that were all positive and
large for my inputs (Ex: 8’b01110111). The large positive numbers would demonstrate that
my signed adder is working properly when there is either overflow or underflow.
3. (Vectors 4/5) For my fourth and fifth test vector, I chose values that were both negative and
small (8’b11111101). The small negative numbers would demonstrate that my multiplier is
functional when multiplying two negative numbers.
4. (Vectors 6/7) For my sixth and seventh test vector, I chose values that are negative and large
(Ex: 8’b10000011). The large negative values demonstrate the my multiplier can handle large
signed negative values and that my adder can handle negative signed overflow.
5. (Vectors 8/9) For my eighth and ninth test vector, I chose values that were either large and
negative with small positive numbers or large and positive with small negative numbers. This
demonstrates that my multiplier can multiply when the signs of the multiplier and the
multiplicand are not the same.
6. (Tenth Vector) The final test vector is made of random 8 bit signed binary numbers in order to
make sure that there were not any potential corner cases that I overlooked.
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Problems Encountered
Early on, I had a lot of trouble determining how to create a signed binary 8 bit
multiplier. I had looked at multiple online sources in my attempt to determine how to create a
signed binary multiplier. My first attempt at creating the binary multiplier utilized 64 “AND”
gates. Unfortunately, I ended up creating an unsigned binary multiplier instead of a signed binary
multiplier. I could not find an easy way to modify this unsigned multiplier to be signed;
therefore, I gave up on the “AND” gate implementation. Next, I tried creating a Wallace Tree.
The implementation of the Wallace Tree was also quite difficult for me because it contained so
many gates that I could not keep track of. Finally, the implementation that allowed me to create
the signed multiplier was the implementation of Booth’s algorithm. I used several online sources
that explained Booth’s algorithm to facilitate my design. Each iteration of the multiplier took
several hours if not several days to implement, which unfortunately reduced the amount of time I
had to get my data path working as I designed it.
Additionally, I encountered troubles with my datapath. It took me much longer than I
imagined it would to get my data path working according to spec.
Functionality Claims
This project took a longer time than I ever expected it would. Alone, I believe I spent at
least 15 hours in the creation of my signed multiplier, 3 hours in the creation of my signed adder,
and 10 hours in the creation of my data path. I was able to get my signed multiplier working
correctly, my signed adder working correctly, and my data path working with 2 adders and
multiplier. Additionally, my data path meets spec by completing the vector in only 13 clock
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cycles. Unfortunately, I did not get time to test my data path with more than 4 vectors, though I
am highly confident that it would work with any inputs as my 4 test vectors thoroughly ended up
covering all potential test cases for my signed adder and signed multiplier.
Additionally, I did not get the chance to create a top module nor controller in Verilog as
I simply did not have time to since I spent so long making sure that my data path and multiplier
are working correctly.
Summary of Claims
1. Signed Adder and Signed Multiplier function perfectly under all test vectors
2. Data path functions correctly by utilizing 2 adders and 1 multiplier (see data path and
resource management above)
3. Data path meets spec due to latency only reaching 13 clock cycles at a maximum
4. NO top module nor controller as I simply did not have time. I have worked very hard on this
project and wanted to make sure everything that I completed was accurate. A theoretical
model and ASM for my controller exists above.
Timing Analysis
I was not able to determine timing for my model since I did not complete the top module
nor the controller.

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Appendix 1 (All Non-Testbench Code)
module fa ( A ,B ,Cin ,Cout ,S , clk);
output Cout ;
output S ;
input clk;
input A ;
wire A ;
input B ;
wire B ;
input Cin ;
wire Cin ;
reg Cout;
reg S;
always @(A or B or Cin) begin
case ({A,B,Cin})
0: begin Cout=0; S=0; end

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endcase
end
endmodule
module addsub8 (
output [7:0] result ,
output overflow ,
input [7:0] A ,
input [7:0] B ,
input mode ,
input clk
);
wire isOneNegative;
xor v10(isOneNegative, A[7], B[7]);
wire B0;
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wire B1;
wire B2;
wire B3;
wire B4;
wire B5;
wire B6;
wire B7;
wire C0;
wire C1;
wire C2;
wire C3;
wire C4;
wire C5;
wire C6;
wire C7;
xor v1(B0, B[0], mode);

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fa U0(A[0],B0,mode,C0,result[0], clk);
fa U1(A[1],B1,C0,C1,result[1], clk);
wire temp;
fa U7(A[7],B7,C6,C7,temp, clk);
xor v9(overflow,C5,C6);
wire overflow2;
and (overflow2, C5, C6);
wire overflow3;
nand(overflow3, C5, C6);
assign result[7] = (!overflow2 && isOneNegative && !mode) || (overflow2 && !isOneNegative
&& !mode) || (!overflow3 && isOneNegative && mode) || (overflow3 && !isOneNegative &&
mode) ? 1'b1 : 1'b0;

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endmodule
module multiplier(prod, busy, mc, mp, clk, start);
output [7:0] prod;
wire [15:0] tempProd1;
output busy;
input [7:0] mc, mp;
input clk, start;
reg [7:0] A, Q, M;
wire [7:0] A2, Q2, A3, Q3, A4, Q4, A5, Q5, A6, Q6, A7, Q7, A8, Q8, A9, Q9;
reg Q_1;
wire Q_2, Q_3, Q_4, Q_5, Q_6, Q_7, Q_8, Q_9;
reg [3:0] count;
wire [7:0] sum, difference, sum2, difference2, sum3, difference3, sum4, difference4, sum5,
difference5, sum6, difference6, sum7, difference7, sum8, difference8;
always @(posedge clk)
begin
if (start) begin
A = 8'b0;
M = mc;
Q = mp;
Q_1 = 1'b0;
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count = 4'b0;
end
else begin
end
end
addsub8 adder (sum, A, M, 1'b0);
addsub8 subtracter (difference, A, ~M, 1'b1);
assign tempProd1 = {A, Q};
assign {A2, Q2, Q_2} = (Q[0] && !Q_1) ? {difference[7], difference, Q} :
((!Q[0] && Q_1) ? {sum[7], sum, Q} :
((Q[0] && Q_1) ? {A[7], A, Q} :
((!Q[0] && !Q_1) ? {A[7], A, Q} : 16'bxxxxxxxxxx)));
addsub8 adder2 (sum2, A2, M, 1'b0);
addsub8 subtracter2 (difference2, A2, ~M, 1'b1);
assign {A3, Q3, Q_3} = (Q2[0] && !Q_2) ? {difference2[7], difference2, Q2} :
((!Q2[0] && Q_2) ? {sum2[7], sum2, Q2} :
((Q2[0] && Q_2) ? {A2[7], A2, Q2} :
((!Q2[0] && !Q_2) ? {A2[7], A2, Q2} : 16'bxxxxxxxxxx)));

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((!Q3[0] && Q_3) ? {sum3[7], sum3, Q3} :
((Q3[0] && Q_3) ? {A3[7], A3, Q3} :
((!Q4[0] && Q_4) ? {sum4[7], sum4, Q4} :
((Q4[0] && Q_4) ? {A4[7], A4, Q4} :
Addsub8 subtracter5 (difference5, A5, ~M, 1'b1);
((!Q5[0] && Q_5) ? {sum5[7], sum5, Q5} :
((Q5[0] && Q_5) ? {A5[7], A5, Q5} :

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((!Q6[0] && Q_6) ? {sum6[7], sum6, Q6} :
((Q6[0] && Q_6) ? {A6[7], A6, Q6} :
((!Q7[0] && Q_7) ? {sum7[7], sum7, Q7} :
((Q7[0] && Q_7) ? {A7[7], A7, Q7} :
Addsub8 subtracter8 (difference8, A8, ~M, 1'b1);
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((!Q8[0] && Q_8) ? {sum8[7], sum8, Q8} :
((Q8[0] && Q_8) ? {A8[7], A8, Q8} :
assign prod = {A9};
endmodule
module datapath(f1, f2, f3, f4, a1, a2, a3, a4, b1, b2, b3, b4, d1, d2, d3, d4, ld, clk, start);
input [7:0] a1, a2, a3, a4, b1, b2, b3, b4, d1, d2, d3, d4;
input ld, clk;
output[7:0] f1, f2, f3, f4;
input start;
reg [7:0] c1, c2, c3, c4, e1, e2, e3, e4;
reg[3:0] count;
wire o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11, o12;
reg [7:0] f1, f2, f3, f4;

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wire[7:0] tempWire;
wire busy1, busy2, busy3, busy4;
reg [7:0] mc, mp;
wire [7:0] multResult;
wire[7:0] addResult;
wire[7:0] addResult2;
reg [7:0] ad1, ad2, ad3, ad4;
reg [7:0] subtract1, subtract2;
always @(posedge clk)
begin
if (start)
count <= 4'b0;
else if (count == 4'b0)
count <= count + 1'b1;

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begin
mc <= a1;
mp <= b1;
end
begin
mc <= a2;
mp <= b2;
end
begin
mc <= a3;
mp <= b3;
c1 <= multResult;
end
begin
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mc <= a4;
mp <= b4;
c2 <= multResult;
end
begin
ad1 <= c1;
ad2 <= d1;
c3 <= multResult;
end
begin
ad1 <= c2;
ad2 <= d2;
e1 <= addResult;
c4 <= multResult;
end
begin
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ad1 <= c3;
ad2 <= d3;
ad3 <= e1;
ad4 <= b1;
e2 <= addResult;
end
begin
ad1 <= c4;
ad2 <= d4;
ad3 <= e2;
ad4 <= b2;
f1 <= addResult2;
e3 <= addResult;
end
begin
ad3 <= e3;
ad4 <= b3;
e4 <= addResult;
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f2 <= addResult2;
end
begin
ad3 <= e4;
ad4 <= b4;
f3 <= addResult2;
end
begin
f4 <= addResult2;
end
begin
//f4 <= addResult2;
end
end
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multiplier mult1(multResult, busy1, mc, mp, clk, 1'b1);
addsub8 add1(addResult, o1, ad1, ad2, 1'b0, clk);
addsub8 add2(addResult2, o2, ad3, ad4, 1'b1, clk);
endmodule
Appendix 2 (Testbenches)
module datapathfinal_tb();
reg [7:0] a1, a2, a3, a4, b1, b2, b3, b4, d1, d2, d3, d4;
reg ld, clk, start;
wire [7:0] f1, f2, f3, f4;
datapath U1(f1, f2, f3, f4, a1, a2, a3, a4, b1, b2, b3, b4, d1, d2, d3, d4,ld, clk, start);
initial
begin
start = 1'b1;
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clk = 1'b0;
ld = 1'b1;
#10;
clk = 1'b1; // First clock (A1)
a1 = 8'b01000000;
#10;
start = 1'b0;
clk = 1'b0;
#10;
clk = 1'b1; // Second clock (A2)
a2 = 8'b11111111;
#10;
clk = 1'b0;
#10;
clk = 1'b1; // Third clock A(3)
a3 = 8'b01111111;
#10;
clk = 1'b0;
#10;
clk = 1'b1; // Fourth clock A(4)
a4 = 8'b01010011;
#10;
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clk = 1'b0;
#10;
clk = 1'b1; // Fifth clock B(1)
b1 = 8'b1010001;
#10;
clk = 1'b0;
#10;
clk = 1'b1; // Sixth clock B(2)
b2 = 8'b10011000;
#10;
clk = 1'b0;
#10;
clk = 1'b1; // Seventh clock B(3)
b3 = 8'b01001000;
#10;
clk = 1'b0;
#10;
clk = 1'b1; // Eigth clock B(4)
b4 = 8'b10011111;
#10;
clk = 1'b0;
#10;
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clk = 1'b1; // Ninth clock D(1)
d1 = 8'b10011000;
#10;
clk = 1'b0;
#10;
clk = 1'b1; // Tenth clock D(2)
d2 = 8'b10011110;
#10;
clk = 1'b0;
#10;
clk = 1'b1; // Eleventh clock D(3)
d3 = 8'b10011111;
#10;
clk = 1'b0;
#10;
clk = 1'b1; // Twelfth clock D(4)
d4 = 8'b00111111;
#10;
clk = 1'b0;
#10;
clk = 1'b1; // Thirteenth Clock
#10;
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clk = 1'b0;
#10;
clk = 1'b1; // Fourteenth Clock
#10;
clk = 1'b0;
#10;
clk = 1'b1;
End
Endmodule
module signed_adder_tb();
reg [7:0] A, B;
reg mode;
reg clk;
wire [7:0] result;
wire overflow;
addsub8 U1 (result, overflow, A, B, mode, clk);
initial
begin
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#10;
clk = 1'b0;
mode = 1'b0;
#10;
clk = 1'b1;
A = 8'b11111111;
B = 8'b00000001; // Result should be 0
#10;
clk = 1'b0;
#10;
clk = 1'b1;
A = 8'b10000000;
B = 8'b01111111; // result should be ff
#10;
clk = 1'b0;
#10;
clk = 1'b1;
A = 8'b10110000;
B = 8'b11000100; // result should 74
#10;
clk = 1'b0;
#10;
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clk = 1'b1;
A = 8'b00111100;
B = 8'b01010000; // result shoulf 8c
#10;
clk = 1'b0;
#10;
clk = 1'b1;
A = 8'b00001000;
B = 8'b00010000;
#10;
clk = 1'b0;
#10;
clk = 1'b1;
A = 8'b01010000;
B = 8'b10001000; //result should d8
#10;
clk = 1'b0;
#10;
clk = 1'b1;
A = 8'b11111011;
B = 8'b11110110;
#10;
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clk = 1'b0;
#10;
clk = 1'b1;
A = 8'b11111111;
B = 8'b11111111; // result should be f1
#10;
end
endmodule
module testbench;
reg clk, start;
reg [7:0] a, b;
wire [15:0] ab;
wire busy;
multiplier multiplier1(ab,busy, a, b, clk, start);
initial begin
clk = 0;
#10;
clk = 1'b1;
start = 1'b1;
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a = 8'b11111111;
b = 8'b11111111;
#10;
clk = 1'b0;
#10;
clk = 1'b1;
a = 8'b01111111;
b = 8'b01111111;
#10;
clk = 1'b0;
#10;
clk = 1'b1;
a = 8'b10000000;
b = 8'b10000000;
#10;
clk = 1'b0;
#10;
clk = 1'b1;
a = 8'b10110110;
b = 8'b01100100;
end
endmodule
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Appendix 3 (C++ Signed Binary Adder Verifier)
/C++ program
#include<iostream>
using namespace std;
void display(int arr[]){
for(int i=31;i>=0;i--){
cout<<arr[i];
cout<<"\n";
void binary(int n , int arr[]){
if(n<0)n*=-1;
int i=0;
while(n){
arr[i++]=n%2;
n/=2;
void twocomp(int arr[]){
int i=0;
while(arr[i]!=1){
i++;
i++;
for(;i<32;i++){
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if(arr[i]==0)arr[i]=1;
else if(arr[i]==1)arr[i]=0;
void Add(int num1[],int num2[],int sum[]){
int carry=0;
int s;
for(int i=0;i<32;i++){
s=num1[i]+num2[i]+carry;
sum[i]=s%2;
carry = s/2;
int main(){
int n1,n2;
cout<<"Enter number1 : ";
cin>>n1;
cout<<"Enter number2 : ";
cin>>n2;
int num1[32],num2[32],sum[32];
for(int i=0;i<32;i++){
num1[i]=0;
num2[i]=0;
sum[i]=0;
}
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binary(n1,num1);
binary(n2,num2);
if(n1<0)twocomp(num1);
if(n2<0)twocomp(num2);
Add(num1,num2,sum);
if(num1[31]==0 && num2[31]==0 &&sum[31]==1)cout<<"\nOverflow\n";
else if(num1[31]==1 && num2[31]==1 &&sum[31]==0)cout<<"\nOverflow\n";
else {
cout<<"\nnum1 : ";
display(num1);
cout<<"\n\n";
cout<<"\nnum2 : ";
display(num2);
cout<<"\n\n";
cout<<"\nSum : ";
display(sum);
cout<<"\n";
cout<<"\n\n"<<n1<<" + "<<n2<<" = "<<n1+n2<<"\n";
return 0;
}
-page !41 of 41
!
References:
[1] https://www.geeksforgeeks.org/computer-organization-booths-algorithm/
[2] https://electrotrick.wordpress.com/2017/09/24/booth-algorithm-multiplication/

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Final Report

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Adam Christa 47362657 ECE 5387 Digital Systems Design Final Project Report 12/10/19

ECE 5387 Final Project

Implementations: Pages 2-5

code of this process is shown below. FIG.1

should be shown below. FIG.2

code for the ternary assignment should be shown below. FIG.4

unchanged [1]. In my version of Booth’s algorithm implementation, I utilize a ternary

achieve correct functionality of my code. However, I believe my implementation of Booth’s

1. Booth’s algorithm is more intuitive for another programmer to understand since it is

(basically) repeated addition.

3. The multiplier utilizes less logic

required at maximum is 16. According to the project guidelines, 4 multiplications will be

version of the data flow diagram. FIG.9

utilizes 2 adders and 1 multiplier instead of 1 adder and 1 multiplier. FIG.10

attempting to utilize this data flow diagram in my implementation.

In FIG.7/8 above, I determined that the minimum number of resources I required

adder and 1 multiplier to meet functionality. FIG.11

resource scheduling chart that has 2 adders and 1 multiplier. FIG.12

implementation of my final design.

According to the project guidelines, I am required to have at least 10 test vectors in

order to demonstrate that my design is functional.

my signed adder is working properly when there is either overflow or underflow.

functional when multiplying two negative numbers.

multiplicand are not the same.

had to get my data path working as I designed it.

Additionally, I encountered troubles with my datapath. It took me much longer than I

imagined it would to get my data path working according to spec.

are working correctly.

resource management above)

model and ASM for my controller exists above.

nor the controller.

module fa ( A ,B ,Cin ,Cout ,S , clk);

always @(A or B or Cin) begin

0: begin Cout=0; S=0; end

1: begin Cout=0; S=1; end

2: begin Cout=0; S=1; end

4: begin Cout=0; S=1; end

5: begin Cout=1; S=0; end

6: begin Cout=1; S=0; end

7: begin Cout=1; S=1; end

output [7:0] result ,

xor v10(isOneNegative, A[7], B[7]);

xor v1(B0, B[0], mode);

xor v2(B1, B[1], mode);

xor v3(B2, B[2], mode);

xor v4(B3, B[3], mode);

xor v5(B4, B[4], mode);

xor v6(B5, B[5], mode);

xor v8(B7, B[7], mode);

and (overflow2, C5, C6);

nand(overflow3, C5, C6);

mode) ? 1'b1 : 1'b0;

module multiplier(prod, busy, mc, mp, clk, start);

output [7:0] prod;

wire [15:0] tempProd1;

input [7:0] mc, mp;

input clk, start;

wire Q_2, Q_3, Q_4, Q_5, Q_6, Q_7, Q_8, Q_9;

reg [3:0] count;

difference5, sum6, difference6, sum7, difference7, sum8, difference8;

always @(posedge clk)

addsub8 adder (sum, A, M, 1'b0);

addsub8 subtracter (difference, A, ~M, 1'b1);