Floorplanning and Place and Route (Flat)

Module 8 Running the ECO Flow

Table of Contents

Lab 8-1 Loading a Design for ECO Routing ...................................................................................... 1

Loading the Design ................................................................................................................... 1
Using Verify Connectivity .......................................................................................................... 1

Floorplanning and Place and Route (Flat)

Module 8 Running the ECO Flow

Lab 8-1 Loading a Design for ECO Routing

Objective: To start the Innovus software, input the required files and implement an ECO using a Verilog file.

Loading the Design

1. Verify that your working directory is set to

FPR/work/ECO
2. Compare the tdsp-core.v and tdsp_core_eco.v files.
The tdsp_core.v file is the original netlist. In the tdsp_core_eco.v file, the instances
connected to the p_data_out[15] and p_data_out[14] nets have been swapped. Search for
instances i-5324 and i_5331 to find the nets.

Using Verify Connectivity

1. Start the software by entering this command in a csh window (after you source the
cshrc): innovus

2. In the innovus shell, run the ecoDesign command to read in the original design, read the
new Verilog file and implement the ECO.
ecoDesign tdsp_core.enc.dat tdsp_core tdsp_core_eco.v
Note :The above command takes a innovus database and a modified netlist as input and
performs ECO operations. It restores the design, examines the changes in the new netlist
and automatically implements the required changes with ecoPlace and ecoRoute

The tdsp_core.enc.dat is the design corresponding to the original tdsp_core.v netlist. The
tdsp-core_eco.v file contains the required ECO that will be implemented. The ecoDesign
command will route the changes in the netlist.
3. Write out a new DEF file, tdsp_core_routed_eco.def.

4. Verify that the new DEF file contains the expected connectivity changes by viewing the
tdsp_core_routed_eco.def file and making sure that its connectivity is the same as in the
Verilog ECO file. You can continue with the postroute flow if you want, including timing and
signal integrity analysis, repair, metal fill and verification.
5. Close the Innovus software.

Summary

In this lab, you

Loaded a placed design.
Ran an ECO and generated a routed design.

Floorplanning and Place and Route (Flat) Page 1