Registers

 An n-bit register has a group of n flip-flops and some logic

gates and is capable of storing n bits of information.
 The flip-flops store the information while the gates control
when and how new information is transferred into the register.
 Some functions of register:
 retrieve data from register
 store/load new data into register (serial or parallel)
 shift the data within register (left or right)

Introduction: Registers 1
CS1104-13
 Simple Registers
 No external gates.
 Example: A 4-bit register. A new 4-bit data is loaded
every clock cycle. CP

I3 A3

Q
D

I2 A2

Q
D

I1 A1

Q
D

I0 A0

Q
CS1104-13 2
Simple Registers
Registers With Parallel Load
 Instead of loading the register at every clock pulse,
we may want to control when to load.
 Loading a register: transfer new information into the
register. Requires a load control input.
 Parallel loading: all bits are loaded simultaneously.

CS1104-13 Registers With Parallel Load 3

4-bit Register with parallel load
Registers With Parallel Load or Store (no change)
Load'.A0 + Load. I0
Load
D Q A0
I0

D Q A1
I1

D Q A2
I2

D Q A3
I3

CLK
CLEAR

CS1104-13
Registers With Parallel Load or store 5
Shift Registers
 Another function of a register, besides storage, is to
provide for data movements.
 Each stage (flip-flop) in a shift register represents
one bit of storage, and the shifting capability of a
register permits the movement of data from stage to
stage within the register, or into or out of the register
upon application of clock pulses.

CS1104-13 Shift Registers 6

Shift Registers
 Basic data movement in shift registers (four bits are
used for illustration).

Data in Data out Data out Data in

(a) Serial in/shift right/serial out SISO (b) Serial in/shift left/serial out SISO

Data in Data in
Data in

Data out
Data out
(c) Parallel in/serial out (d) Serial in/parallel out
PISO Data out
(e) Parallel in / parallel out

(f) Rotate right (g) Rotate left

CS1104-13 Shift Registers 7

PIPO Registers

CS1103
Serial In/Serial Out Shift Registers
 Accepts data serially – one bit at a time – and also
produces output serially.

Serial data Q0 Q1 Q2 Q3 Serial data

D Q D Q D Q D Q
input output
C C C C

CLK

CS1104-13 Serial In/Serial Out Shift Registers 9

Example
 Indicate the last output stored in 4-bits shift right register, with initial
value 0010 and use 5 clocks as follows, at clock 1 and 2, the input to FF
is 1 and at clock 3, 4 ,and 5 the input is 0

CS1103
Serial In/Serial Out Shift Registers
 Application: Serial transfer of data from one register to another.

SI SO SI SO
Shift register A Shift register B

Clock CP
Shift control

Clock

Shift Wordtime
control

CP
T1 T2 T3 T4

CS1104-13 Serial In/Serial Out Shift Registers 11

Serial In/Serial Out Shift Registers
 Serial-transfer example.

Timing Pulse Shift register A Shift register B Serial output of B

Initial value 1 0 1 1 0 0 1 0 0
After T1 1 1 0 1 1 0 0 1 1
After T2 1 1 1 0 1 1 0 0 0
After T3 0 1 1 1 0 1 1 0 0
After T4 1 0 1 1 1 0 1 1 1

CS1104-13 Serial In/Serial Out Shift Registers 12

Parallel In/Parallel Out Shift Registers
 Simultaneous input and output of all data bits.
Parallel data inputs

D0 D1 D2 D3
Data in

D Q D Q D Q D Q
C C C C

Data out
CLK
(e) Parallel in / parallel out
Q0 Q1 Q2 Q3

Parallel data outputs

CS1104-13 Parallel In/Parallel Out Shift Registers 13

Serial In/Parallel Out Shift Registers
 Accepts data serially.
 Outputs of all stages are available simultaneously.
Data in
Data input D SRG 4
CLK C
Data out
Q0 Q1 Q2 Q3 Serial in/parallel out

Logic symbol

Data input D Q D Q D Q D Q
C C C C

CLK

Q0 Q1 Q2 Q3

CS1104-13 Serial In/Parallel Out Shift Registers 14

Parallel In/Serial Out Shift Registers
 Bits are entered simultaneously, but output is serial.

Data in

D0 D1 D2 D3

SHIFT/LOAD SRG 4
Serial data out
CLK C

Logic symbol

CS1104-13 Parallel In/Serial Out Shift Registers 15

Parallel In/Serial Out Shift Registers
 Bits are entered simultaneously, but output is serial.
Data input

D0 D1 D2 D3
SHIFT/LOAD

Serial
D Q D Q D Q D Q data
Q0 Q1 Q2 Q3 out
C C C C

CLK
SHIFT.Q0 + SHIFT'.D1

CS1104-13 Parallel In/Serial Out Shift Registers 16

Bidirectional Shift Registers
 Data can be shifted either left or right, using a control
line RIGHT/LEFT (or simply RIGHT) to indicate the
direction.

RIGHT/LEFT

Serial
data in

RIGHT.Q0 + D Q D Q D Q D Q Q3
RIGHT'.Q2 Q1 Q2
C C C C

Q0
CLK
Bidirectional Shift Registers
CS1104-13
Can be implemented using 2X1 multiplexer
Bidirectional Shift Registers
 4-bit bidirectional shift register with parallel load.

Mode Control
s1 s0 Register Operation
0 0 No change
0 1 Shift right
1 0 Shift left
1 1 Parallel load

Bidirectional Shift Registers with parallel load

CS1104-13 18
Bidirectional Shift Registers with parallel load
 4-bit bidirectional shift register with parallel load.
Parallel outputs

A4 A3 A2 A1

Q Q Q Q
Clear
D D D D

CLK

s1 4x1 4x1 4x1 4x1

s0 MUX MUX MUX MUX
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

Serial
input for Serial
shift-right input for
I4 I3 I2 I1 shift-left
Parallel inputs
CS1104-13 Bidirectional Shift Registers 19
Shift Register Counters
 Shift register counter: a shift register with the serial
output connected back to the serial input.
 They are classified as counters because they give a
specified sequence of states.
 Ring counter.

CS1104-13 Shift Register Counters 20

Ring Counters
 One flip-flop (stage) for each state in the sequence.
 The output of the last stage is connected to the D
input of the first stage.
 An n-bit ring counter cycles through n states.
 No decoding gates are required, as there is an output
that corresponds to every state the counter is in.

CS1104-13 Ring Counters 21

Ring Counters
 Example: A 6-bit (MOD-6) ring counter.
PRE
Q0 Q1 Q2 Q3 Q4 Q5
D Q D Q D Q D Q D Q D Q

CLR
CLK

Clock Q0 Q1 Q2 Q3 Q4 Q5 100000
0 1 0 0 0 0 0
000001 010000
1 0 1 0 0 0 0
2 0 0 1 0 0 0
3 0 0 0 1 0 0 000010 001000
4 0 0 0 0 1 0
5 0 0 0 0 0 1 000100

CS1104-13 Ring Counters 22