Analog Integrated Circuits

Laboratory

Two-Stage Amplifier

Hong-Yi Huang

Nano Integrated Circuits and Systems Lab.

Graduate Institute of Electrical Engineering

1
 Outline
 Theory Analysis of Two-Stage Amplifier

 Comparison of Two-Stage Amplifier and Different Amplifier

 Frequency Compensation – Method 1

 Frequency Compensation – Method 2

 Specification

 ICMR

 Output Voltage Swing

 CMRR

 Slew Rate & Settling Time

 Experiment Steps

 Questions

Two Stage Amplifier 2 Analog ICs; Hong-Yi Huang

 Two Stage Op Amp

Mp3 Mp4
Wp/Lp Wp/Lp
=11/1 =11/1
Wp/Lp
x =66/1
Mp6

Vin+ Vin-
Mn2 Mn1 Vout
Wn/Ln Wn/Ln
=5/1 =5/1 CL=10pF
IREF
Wn/Ln Wn/Ln
=10/1 =30/1
Wn/Ln Mn7
Mn8 Mn5 =10/1

 First-Stage is constructed by Mn1, Mn2, Mp3, Mp4 and a constant current source
Mn5 as a Differential Amplifier.

 Second-Stage is constructed by Mp6 and a constant current source Mn7 as a

Common Source Amplifier

Two Stage Amplifier 3 Analog ICs; Hong-Yi Huang

 Two Stage Op Amp
 According to the theory analysis ：
1
I  2

 Positive CMR ： Vinmax   VDD   REF   Vt, p3 max   Vt, n1min 

β 
 p3 
1
I  2
 Negative CMR ： Vinmin    REF   Vt, n1max   VDS sat 
 βn1 
gm,n2 2gm, nn2
 First-Stage gain ： A v 1  
gds,n2  gds,p4 IREF λn2  λp4 

 Second-Stage gain ： A  gm,p6


gm, n2
gds,p6  gds,n7 Ip13 λp6  λn7 
v2

gds, p4  gds, n2
 Pole1 ： 
CX
gds, p6  gds, n7
 Pole2 ： 
CL

 Gain-bandwidth ： G.B.  A V P1

Two Stage Amplifier 4 Analog ICs; Hong-Yi Huang

 Performance comparison

Tow stage

Gain -3dB G.B.

Tow 82dB 100KHz 50MHz

Differential Amp
stage

Diff 42dB 100KHz 250MHz

amp

 From the simulation result, the performance of Two-Stage Operational

Amplifier is better than Differential Amplifier.

Two Stage Amplifier 5 Analog ICs; Hong-Yi Huang

 Unstable oscillation

Vout
Gain

Phase

Vin+

 If we connect the circuit as a unit gain buffer, we can see from

the simulation result that phase margin < 0°, so it will become Vout
Vin
an unstable system. Infect, the typical value of phase margin
must larger than 45° to form a stable system.

Two Stage Amplifier 6 Analog ICs; Hong-Yi Huang

 Frequency Compensation – Method 1

Mp3 Mp4
Wp/Lp Wp/Lp
=11/1 =11/1
Wp/Lp
x =66/1
Mp6

Vin+ Vin-
Mn2 Mn1 Vout
Wn/Ln Wn/Ln CC=2pF
=5/1 =5/1 CL=10pF
IREF
Wn/Ln Wn/Ln
=10/1 =30/1
Wn/Ln Mn7
Mn8 Mn5 =10/1

 Connect a compensation capacitor CC between first stage and second stage to

improve phase margin.

Two Stage Amplifier 7 Analog ICs; Hong-Yi Huang

 Frequency Compensation – Method 1
 From the theory analysis we get：

- (gds, p4  gds, n2 )(gds, p6  gds, n7 )

 Pole1 ： p1 
gm, p6 CC

 Pole2： - gm, p6
p2 
CL

 Zero ： gm, p6
Z 
CC

 Slew Rate ： IREF

CC

Two Stage Amplifier 8 Analog ICs; Hong-Yi Huang

 Frequency Compensation – Method 1
Without CC

CC=2pF(gain)
Without CC

CC=2pF(phase)

 After compensation, decrease pole1 frequency and increase pole 2 frequency

so that phase margin is around 55° and also the system becomes more stable.

Two Stage Amplifier 9 Analog ICs; Hong-Yi Huang

 Frequency Compensation – Method 1
CC=6pF(gain)
CC=4pF(gain)
CC=2pF(gain)

CC=2pF
CC=6pF(phase)
CC=4pF(phase) CC=4pF

CC=2pF(phase) CC=6pF

 We can see that while the CC increases the phase margin also increase and
decrease the Slew Rate, because the larger CC needs more time to charge or
discharge.

Two Stage Amplifier 10 Analog ICs; Hong-Yi Huang

 Frequency Compensation – Method 2

Mp3 Mp4
Wp/Lp Wp/Lp
=11/1 =11/1
Wp/Lp
x =66/1
Mp6

Vin+ Vin-
Mn2 Mn1 Vout
Wn/Ln Wn/Ln Rc CC=2pF
=5/1 =5/1 CL=10pF
IREF
Wn/Ln Wn/Ln
=10/1 =30/1
Wn/Ln Mn7
Mn8 Mn5 =10/1

 Now, we introduce another method to compensate frequency by connecting a

resistor RC.

Two Stage Amplifier 11 Analog ICs; Hong-Yi Huang

 Frequency Compensation – Method 2
 From the theory analysis we get：

1 1
 Pole1 ： p1  
1 gm, p6R2 R1Cc gm, p6R2R1Cc

 Pole2 ：    gm, p6 Cc  gm, p6


C1C2  CcC1  CcC2
p2
C2

 Pole3 ：    1 Where R1  1
p3
R cC1 gds, p4  gds, n1
1
R2 
 Zero ： Z 
1 gds, p6  gds, n7
 1 
Cc   Rc  C1  CX：total capacitor at X
 gm, p6 
C2  CL：total capacitor at output

Two Stage Amplifier 12 Analog ICs; Hong-Yi Huang

 Frequency Compensation – Method 2
 Use RC to determine the zero frequency.

1
 (1) Choose R c  , to move zero to infinite.
gm, p13

1  gm, p6
 (2) Choose W p2=WZ， 
 1  C2
CC   RC 
g 
 m, p6 

 CC  C2  1 
RC    
 
 CC  gm, p6 

Two Stage Amplifier 13 Analog ICs; Hong-Yi Huang

 Frequency Compensation – Method 2

Only Cc

With Rc Cc

 First, we choose RC=1.234k ohm to move the zero to infinite.

 From the simulation, we can see that the gain does not increases after second
pole, it means that the zero is moved to infinite. And the PM is around 70 °.

Two Stage Amplifier 14 Analog ICs; Hong-Yi Huang

 Frequency Compensation – Method 2

Only Cc

With Rc Cc

 
 We let RC   CC  C2  1   6K , so that W p2=W Z .
 C  g 
 C  m, p6 
 From the simulation, the PM increase to around 90°

Two Stage Amplifier 15 Analog ICs; Hong-Yi Huang

 Input Common Mode Range (ICMR)
 Input Common Mode Range (ICMR): the range of input common mode
voltage

.dc Vinp 0 1.8 0.1

IDS2

Vout
Vinp

ICMR

Two Stage Amplifier 16 Analog ICs; Hong-Yi Huang

 Output Voltage Swing
 Output Voltage Swing:

The range of output voltage which can operate normally.

VOUT
10R
VOUT   VIN  10 VIN
VINM R

10R

R
VINM
VOUT
0.9V

Two Stage Amplifier 17 Analog ICs; Hong-Yi Huang

 Common Mode Rejection Ratio (CMRR)
 Common Mode Rejection Ratio
(CMRR): the ability of rejecting
common mode signal.

vinp vinp 0 dc 1v ac 1v

vinn vinn 0 dc 1v ac 0v

.ac dec 10 100 100000MEG

.print vdb(vout)
Common mode gain
.alter

vinn vinn 0 dc 1v ac 1v

Two Stage Amplifier 18 Analog ICs; Hong-Yi Huang

 Common Mode Rejection Ratio (CMRR)

CMRR=Ad-Acm

Acm
Ad

Two Stage Amplifier 19 Analog ICs; Hong-Yi Huang

 Slew Rate & Settling Time
 Slew Rate: the maximum rate of
change dvo/dt is called slew rate.

 Settling Time: the time during output

signal be stable shown as left figure.

vinp vinp 0 pulse(0.7v 1.5v 0n 0n 0n

400n 800n)

.meas tran t when v(vout)=1.5v rise=1

.meas SR param='0.9/t'

Two Stage Amplifier 20 Analog ICs; Hong-Yi Huang

 Slew Rate & Settling Time
VINP

VOUT V1
∆V1 SR1   4.76 V
T1 us
∆T1

VINP

VOUT V2
∆V2 SR2   7V
T2 us
∆T2

 From the simulation, we can see that the slew rate will increase while the swing of
input pulse increases.

Two Stage Amplifier 21 Analog ICs; Hong-Yi Huang

 Experiment Steps
 From the circuit structure in page 3, simulate differential amplifier and two stage
amplifier respectively and compare the gain, -3dB frequency and G.B.

 Connect the two stage amplifier as a unit gain buffer in page 6, simulate it and
observe the stability and output waveform.

 From the circuit structure in page 7, simulate the effect of phase margin when
adding compensation capacitor.

 Vary the value of compensation capacitor to observe the effect to phase margin and
also to observe the effect to slew rate.

 From the circuit structure in page 11 ,observe the effect after adding a compensated
resistor.

Two Stage Amplifier 22 Analog ICs; Hong-Yi Huang

 Questions
 Why do we use a Common Source structure as the output stage of Two-Stage
Operational Amplifier? What if we use the other structures?

Two Stage Amplifier 23 Analog ICs; Hong-Yi Huang