VLSI Design Verification and Testing Overview

Definition
Design for Testability (DFT) - 1
Ad-hoc methods

Scan design
 Design rules
 Scan register
 Scan flip-flops
 Scan test sequences
Mohammad Tehranipoor  Overhead
Electrical and Computer Engineering
 Scan design system

Summary
University of Connecticut

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Definition Ad-Hoc DFT Methods

Design for testability (DFT) refers to those design
Good design practices learned through
techniques that make test generation and test
experience are used as guidelines:
application cost-effective.
 Don’t-s and Do-s

DFT methods for digital circuits:

Avoid asynchronous (unclocked) feedback.
 Ad-hoc methods

Avoid delay dependant logic.
 Structured methods:

Avoid parallel drivers.

Scan

Avoid monostables and self-resetting logic.

Partial Scan

Built-In Self-Test (BIST)

Avoid gated clocks.

Boundary Scan
Avoid redundant gates.

Avoid high fanin fanout combinations.

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Ad-Hoc DFT Methods Ad-Hoc DFT Methods

Design Reviews

Good design practices learnt through  Manual analysis
experience are used as guidelines:
Conducted by experts
 Don’t-s and Do-s (contd.)  Programmed analysis

Make flip-flops initializable.
Using design auditing tools

Separate digital and analog circuits.
 Programmed enforcement

Provide test control for difficult-to-control signals.

Must use certain design practices and cell types.

Buses can be useful and make life easier.

Limit gate fanin and fanout.
Objective: Adherence to design guidelines and

Consider ATE requirements (tristates, etc.) testability improvement techniques with little
impact on performance and area.

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 Ad-Hoc DFT Methods Scan Design
 Objectives

Disadvantages of ad-hoc DFT methods:
Simple read/write access to all or subset of storage

Experts and tools not always available elements in a design.

Test generation is often manual with no
Direct control of storage elements to an arbitrary value
guarantee of high fault coverage (0 or 1).
 Functional patterns
Direct observation of the state of storage elements and

Design iterations may be necessary hence the internal state of the circuit.

Very time consuming

Key is – Enhanced controllability and observability.

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Scan Design Scan Design

 Circuit is designed using pre-specified design rules.

Circuit-Under-Test (CUT)
 Test structure (hardware) is added to the verified design:
Scan-out (SO)

Add one (or more) test control (TC) primary input.

Replace flip-flops by scan flip-flops and connect to form one or

Primary more shift registers in the test mode.
Primary
Gates
Gates
Gates

Gates

Inputs
Outputs
Make input/output of each scan shift register
controllable/observable from PI/PO.
 Use combinational ATPG to obtain tests for all testable faults in
Scan-in (SI) the combinational logic.
 Add shift register tests and convert ATPG tests into scan
Scan Flip-Flop sequences for use in manufacturing test.

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Scan Design Rules Correcting a Rule Violation

All clocks must be controlled from PIs.

Comb.
logic D1 Q

Use only clocked D-type flip-flops for all state
Comb.
variables. D2
FF
logic
CK

At least one PI pin must be available for test; more
pins, if available, can be used.

All clocks must be controlled from PIs. Comb.
logic

Clocks must not feed data inputs of flip-flops. Q
D1
D2 FF Comb.
logic
CK

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 Correcting a Rule Violation Scan Flip-Flop (Master-Slave)

D Master latch Slave latch

D D 0 D Q TC
D Q
Logic Q
1
SI overhead
CK CK MUX
CK
CK SD Q

SE CK D flip-flop

D Flip-Flop Scan Flip-Flop CK Master open Slave open

t

TC Normal mode, D selected Scan mode, SD selected

t

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Level-Sensitive Scan-Design Latch (LSSD) Adding Scan Structure

Master latch Slave latch
PI PO
D
Q
Combinational SFF SCANOUT

MCK Q logic SFF

SCK D flip-flop
SFF
SD
Normal

MCK
mode

Logic TCK
overhead
TCK MCK
mode
Scan

TC or TCK Not shown: CK or

TCK MCK/SCK feed all
SCANIN SFFs (scan Flip-
Level Sensitive rather than
Scan Path flops).
SCK t
edge sensitive Also called Scan Chain
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Comb. Test Vectors Comb. Test Vectors

Don’t care
or random
PI I1 I2 bits

SCANIN S1 S2

PI I1 I2 O1 O2 PO TC 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0000000

Combinational
SCANIN
SCANOUT PO O1 O2
TC
logic
Next
Present S2 N1 N2
S1 state SCANOUT N1 N2
state
Sequence length = (nsff + 1) ncomb + nsff clock periods
ncomb = number of combinational vectors
nsff = number of scan flip-flops

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 Testing Scan Register Multiple Scan Registers

Scan flip-flops can be distributed among any number of
shift registers, each having a separate scanin and scanout

Scan register must be tested prior to application of scan test pin.
sequences.
Test sequence length is determined by the longest scan

A shift sequence 00110011 . . . of length nsff+4 in scan shift register.
mode (TC=0) produces 00, 01, 11 and 10 transitions in all
Just one test control (TC) pin is essential.
flip-flops and observes the result at SCANOUT output.

Total scan test length: PI/SCANIN
Combinational
PO/
M SCANOUT
((nsff + 1) ncomb + nsff ) + (nsff + 4) clock periods. logic U
SFF X
(ncomb + 2) nsff + ncomb + 4 clock periods.
SFF

Example: 2,000 scan flip-flops, 500 comb. vectors, total scan SFF
test length ~ 106 clocks.
TC

Multiple scan registers reduce test length.
CK

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Multiple Scan Registers Scan Overhead

Scan flip-flops can be distributed among any number of shift
registers, each having a separate scanin and scanout pin.
IO pins: One pin necessary.

Area overhead:
 Gate overhead = [4 nsff/(ng+10nff)] x 100%,
where ng = comb. gates; nff = flip-flops;

Example – ng = 100k gates, nff = 2k flip-flops, overhead =
SI1 Scan Chain 1 SO1 6.7%.
SI2 SO2  More accurate estimate must consider scan wiring and layout
SO3
area.
SI3 Scan Chain 2

Performance overhead:
 Multiplexer delay added in combinational path; approx. two
Scan Chain 3 gate-delays.
TC  Flip-flop output loading due to one additional fanout; approx.
5-6%.

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Hierarchical Scan Optimum Scan Layout

X’

Scan flip-flops are chained within subnetworks X
before chaining subnetworks. IO SFF
cell

Advantages: pad

Automatic scan insertion in netlist

SCANIN

Circuit hierarchy preserved – helps in debugging and Flip-
design changes flop
cell

Disadvantage: Non-optimum chip layout. Y Y’

Scanin Scanout TC SCAN

SFF1 SFF4
SFF1 SFF3 OUT
Scanin
Scanout

SFF2 SFF3 Routing

SFF4 SFF2
channels
Hierarchical netlist Interconnects Active areas: XY and X’Y’
Flat layout

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 Scan Area Overhead Example: Scan Layout

2,000-gate CMOS chip
Linear dimensions of active area:
X = (C + S) / r
Fractional area under flip-flop cells, s = 0.478
X’ = (C + S + αS) / r y = track dimension, wire
Scan flip-flop (SFF) cell width increase, α = 0.25
width+separation
β) / T
Y’ = Y + ry = Y + Y(1--β C = total comb. cell width
Routing area fraction, β = 0.471
S = total non-scan FF cell
Cell height in routing tracks, T = 10
Area overhead width

Calculated overhead = 17.24%
X’Y’--XY s = fractional FF cell area
= S/(C+S)
Actual measured data and performance:
= -------------- x 100% α = SFF cell width fractional
XY increase
β
1--β r = number of cell rows Scan implementation Area overhead Normalized clock rate
or routing channels
= [(1+α αs)(1+ -------) – 1] x 100% β = routing fraction in active
______________________________________________________________________
T area None 0.0 1.00
T = cell height in track
1--ββ dimension y Hierarchical 16.93% 0.87
= (αs + ------- ) x 100% Optimum layout 11.90% 0.91
T
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ATPG Example: S5378 Automated Scan Design

Behavior, RTL, and logic
Sequential Rule
Design and verification
violations
ATPG
Original Full-scan Scan design
rule audits
Number of combinational gates 2,781 2,781 Gate-level
Number of non-scan flip-flops (10 gates each) 179 0 netlist
Number of scan flip-flops (14 gates each) 0 179 Combinational Scan hardware
Gate overhead 0.0% 15.66% ATPG insertion
Number of faults 4,603 4,603
Combinational Scan
PI/PO for ATPG 35/49 214/228
vectors netlist
Fault coverage 70.0% 99.1%
Fault efficiency 70.9% 100.0% Scan sequence Scan chain order Chip layout: Scan-
CPU time on SUN Ultra II, 200MHz processor 5,533 s 5s and test program chain optimization,
Number of ATPG vectors 414 585 generation timing verification
Scan sequence length 414 105,662
Design and test
data for
Test program manufacturing Mask data

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Timing and Power Summary

Scan is the most popular DFT technique:

Small delays in scan path and clock skew can cause
Rule-based design
race condition.
Automated DFT hardware insertion

Large delays in scan path require slower scan clock.
Combinational ATPG

Dynamic multiplexers: Skew between TC and TC
Advantages:

Design automation
signals can cause momentary shorting of D and SD

High fault coverage; helpful in diagnosis
inputs.
Hierarchical – scan-testable modules are easily combined into

Random signal activity in combinational circuit large scan-testable systems
during scan can cause excessive power dissipation.
Moderate area (~10%) and speed (~5%) overhead

Disadvantages:

Large test data volume and long test time

Basically a slow speed (DC) test

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