DESIGNING OF VARIOUS HIGH

PERFORMANCE VLSI BASED

ADDERS

[EC-B19]

Electronics Department
Medi-Caps University Indore

Guided By: Prof. Aditya Mandloi

Submitted By : Aviral Shrivastav

Harshita Verma

Kanika Gupta

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 TABLE OF CONTENTS

Abbreviations 3

List of table 4

List of figures 5

1. PROBLEM STATEMENT: 6

2. LITERATURE SURVEY: 6

3. OBJECTIVE: 7

3.1. < To design Brent Kung Adder and Kogge Stone Adder using design software. > 7

3.2. < To simulate Brent Kung Adder and Kogge Stone Adder. > 7

3.3. < To compare the performance of both PPAs based on their speed, area and Power dissipation . > 7

4. METHODOLOGY 7

5. PROPOSED SOLUTION 8

6. PLAN OF REMAINING WORK 8

7. CURRENT CHALLENGES 8

8. PROJECT OUTCOME – ACHIEVEENTS 9

9. APPLICATION OF THE PROJECT 10

10. FUTURE SCOPE OF WORK 10

11. IMPROVEMENT DONE AFTER FIRST PRESENTATION AND FEEDBACK BY VALUERS 10

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 ABBREVIATIONS

KSA - Kogge Stone Adder

BKA - Brent Kung Adder
PPA - Parallel Prefix Adder
CSA - Carry Select Adder
RCA - Ripple Carry Adders
HCA - Han Carlson Adder
HHCA - Hybrid Han Carlson Adder
VLSI - Very Large Scale Integration
HDL - Hardware Description Language
ISE - Integrated Software Environment

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 LIST OF TABLES

Table 1 - Report KSA

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 LIST OF FIGURES

Fig.1 : Kogge Stone Adder

Fig.2 : Brent Kung Adder
Fig.3: KSA Block Representation
Fig.4: Black Cell
Fig.5 KSA Schematic
Fig.6 : Grey Cell
Fig.7 : XOR Circuit

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 PROJECT-I
PROPOSAL SUBMISSION (ECPC01)

Date : 16/10/2019

GROUP NO: B19

PROJECT TITLE: Designing of various high performance VLSI based adders.

PROJECT GUIDE: Prof. AdityaMandloi

GROUP MEMBERS:

1) EN16EL301067 and AviralShrivastav

2) EN16EL301103 and HarshitaVerma
3) EN16EL301111 andKanika Gupta

1. PROBLEM STATEMENT:

One problem that exists in this project is to find the differences between BKA and KSA
in terms of area size. Although both are PPA that performs the same functions, these
adders have differences between them. After conducting this project, the differences
between BKA and KSA can be known. Another problem in this project is requirement to
find which PPA is better in terms of time propagation delay, power consumption and
area. By conducting this project, it is interesting to see which PPA can perform better in
terms of bits addition.

2. LITERATURE SURVEY:

The [1] presents a VLSI implementation of a high speed Kogge-Stone adder (KSA) using
0.18µm process technology. The adder is known to be one of the fastest adder
architectures, and this is validated through a comparison with other adder architectures
including the standard ripple carry adder and the carry look ahead adder.The [2]
investigates the performance of four different Parallel Prefix Adders namely Kogge Stone
Adder (KSA), Brent Kung Adder (BKA), Han Carlson Adder (HCA) and Hybrid Han
Carlson Adder (HHCA). In this paper the key contribution is the information about the
structure of the Parallel Prefix Adders and their performance parameters. VLSI, in
modern day technology has seen extensive use of PPA with a better delay performance.
These pre-compute the carries and thus have upper hand over the commonly used Ripple
Carry Adder (RCA). Addition has been an indispensable operation in most of the widely
used applications. In [3] the above points are discussed. The [4] discuses that Parallel
Prefix adders have been one of the most notable among several designs proposed in the
past. The advantage of utilizing the flexibility in implementing the three structures based
upon throughput requirements. Due to continuing integrating intensity and the growing

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 needs of portable devices, low-power and high-performance designs are of prime
importance. The [5] highlight’s IC design environment, the chip performance is influence
by design environment, schematic and sizing parameter of the transistor. Therefore, this
study is an attempt to investigate the performance of 4-bit Brent Kung Parallel Prefix
Adder using Silvaco EDA Tools and targeted to 0.18um Silterra Technology. The [6]
tells about Carry Select Adder (CSA) architectures are proposed using parallel prefix
adders. Instead of using dual Ripple Carry Adders (RCA), parallel prefix adder i.e., Brent
Kung (BK) adder is used to design Regular Linear CSA. In [7] Carry Select Adder
understands between RCA and BK in term of area and delay. Delay of RCA is larger
therefore we have replaced it with Brent Kung parallel prefix adder which gives fast
result. At last [8] describes comparative performance of 4-bit RCA and 4-Bit BK parallel
prefix adder designed using TANNER EDA tool. This paper presents performance
analysis of different Fast Adders. The comparison is done on the basis of three
performance parameters i.e. Area, Speed and Power consumption. Further, we present a
design methodology of hybrid carry lookahead/carry skip adders (CLSKAs). This
modified carry skip adder is modeled by using both fix and variable block size.

Fig.1 : Kogge Stone Adder Fig.2 : Brent Kung Adder

3. OBJECTIVE:

1) To design Brent Kung Adder and Kogge Stone Adder using design software
2) To simulate Brent Kung Adder and Kogge Stone Adder
3) To compare the performance of both PPAs based on their speed, area and Power
dissipation.

4. METHODLOGY:

This project is a research of two common adders of Parallel PrefixAdder (PPA) type, the
Brent Kung Adder (BKA) and Kogge Stone Adder (KSA). BKA and KSA are chosen
because these two adders are the most common adders being used in the electronic
industry at the moment. The research is done by comparing the two PPAs based on their
performances.In Very Large Scale Integration (VLSI) designs, Parallel prefix adders
(PPA) have the better delay performance. A parallel prefix adder involves the execution

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 of the operation in parallel which can be obtained by segmentation into smaller pieces.
The binary addition is the basic arithmetic operation in digital circuits and it became
essential in most of the digital systems including Arithmetic and Logic Unit (ALU),
microprocessors and Digital Signal Processing (DSP). At present, the research continues
on increasing the adder’s delay performance. In this project the investigation of different
types of PPA’s. These adders are implemented in verilog Hardware Description
Language (HDL) using Xilinx Integrated Software Environment (ISE) Design Suite. The
area, delay and power consumed by all types of PPA’s are analyzed. The adder designs
are implemented and delay, power and area of all the adders are investigated.

5. PROPOSED SOLUTION:

Parameters like area, power consumption, delay etc. are of utmost importance for the
determination of the functionality and usage of a VLSI device itself and its applications.
Thus we propose to compare the different PPAs on these bases by using tools like tanner
v13.1 andVerilog Hardware Description Language (HDL) using Xilinx Integrated
Software Environment (ISE) Design Suite. A comprehensive analysis and comparison
will lead to the understanding of these parameters in different conditions and
applications. This would result in suitable application of the adders in order to get
optimized output

6. PLAN OF REMAINING WORK

Study of basic methodology of Brent Kung adder. 21 to 23/09/2019

Understanding the architecture of Brent Kung adder. 30 to 31/10/2019

Designing of Verilog HDL code for BKA(Brent Kung adder). 04 to 06/10/2019

Comparison and analysis of PPAs( KSA and BKA) on 18 to 20/11/2019

different parameters.

7. CURRENT CHALLENGES

The current challenge in VLSI is optimization and using right circuit at right place. For
example there are various types of adder circuit from simple half adder to parallel prefix
adders, now if we want simple 2 bit addition we can use half adder and for complex
addition we can use Carry select adder or may be PPA .So by using right circuit at right
place we can enhance circuit performance in terms of delay, speed, costing, power
dissipation and efficiency of a circuit.

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 8. PROJECT OUTCOME – ACHIEVEENTS
As of now we have
1) Studied KSA.
2) Analyzed KSA.
3) Implemented KSA on Xilinx.
4) Generated KSA schematic .

Fig.3: KSA Block Representation Fig.4: Black Cell

Fig.5 KSA Schematic

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 Fig.6 : Grey Cell Fig.7 : XOR Circuit

Optimization Goal Speed

Maximum combinational path delay 16.001ns
Total memory usage 157320 kilobytes
Number of errors 0 ( 0 filtered)
Table.1 : Report KSA

9. APPLICATION OF THE PROJECT

The main application of this work is to come out with the best adder so that it can be used
in the VLSI industry.Adders have very important role in digital VLSI circuits.
Performance of processor and system, in VLSI can be improved by using adder with the
best performance so it is needed to design unique adder which provides high speed,low
area as well as delay in order to meet the needs of current VLSI industry.

10. FUTURE SCOPE OF WORK

This work has been designed for 8-bit word size and result are evaluated for parameters
like area, delay and power. This work can further extended for higher number of bits(16
-bit, 32-bit, 64 -bit…). New architectures can be designed in order to reduce power, area
and delay of the circuits. Steps may be taken to optimize the other parameters like
frequency, number of gate, clock, length etc.

11. IMPROVEMENT DONE AFTER FIRST PRESENTATION AND FEEDBACK BY

VALUERS

Performed a detailed analysis of the adders (KSA and BKA).

Required changes made in the ppt.

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REFERENCES:

[1] Xiang, Lee &Zabidi, Muhammad &Awab, Ainy&AbRahman, Ab Al-Hadi.(2018). VLSI

Implmentation of a Fast Kogge-Stone Parallel-Prefix Adder. Journal of Physics:
Conference Series. 1049. 012077. 10.1088/1742-6596/1049/1/012077.
[2] S. Rakesh, K.S. Vijula Grace, A comprehensive review on the VLSI design performance
of different Parallel Prefix Adders, Materials Today: Proceedings, Volume 11, Part 3,
2019.
[3] AradhanaRaju , RichiPatnaik , RittoKurianBabu & PurabiMahato(2016).Parallel prefix
adders — A comparative study for fastest response .Publisher : IEEE,2016 International
Conference on Communication and Electronics Systems (ICCES),
DOI: 10.1109/CESYS.2016.7889974. P.AnnapurnaBai&M.VijayaLaxmi. Design of 128-
bit Kogge-Stone Low Power.
[4] P. Annapurna Bai&M.VijayaLaxmi, Design of 128-bit Kogge-Stone Low power Parallel
Prefix VLSI Adder for High Speed Arithmetic Circuits, International Journal of
Engineering and Advanced Technology (IJEAT) ISSN: 2249 – 8958, Volume-2, Issue-6,
August 2013.
[5] Abidin, A.Z. & Al Junid, Syed & Sharif, K.K.M. & Othman, Zulbasri&Haron, Adib.
(2012). 4-bit Brent kung parallel prefix adder simulation study using silvaco EDA tools.
13. 51-59. 10.5013/IJSSST.a.13.3A.07.
[6] PallaviSaxena,Design of low power and high speed Carry Select Adder using Brent Kung
adder Published in ;2015 International Conference on VLSI Systems, Architecture,
Technology and Applications (VLSI-SATA),DOI: 10.1109/VLSI-SATA.2015.7050465.
[7] Potdukhe, Pappu&Jaiswal, Vishal. (2016). Design of high speed carry select adder using
brent kung adder. 652-655. 10.1109/ICEEOT.2016.7754762.
[8] R.P.P. Singh , Parveen Kumar & Balwinder Singh , Performance Analysis of Fast
Adders Using VHDL , Published in 2009 International Conference on Advances in
Recent Technologies in Communication and Computing ,
DOI: 10.1109/ARTCom.2009.132 .

PLAGIARISM REPORT :

Website used https://www.duplichecker.com

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Name and Enrolment of Students: Signature

1. EN16EL301067 and Aviral Shrivastav ______________________

2. EN16EL301103 and HarshitaVerma ______________________

3. EN16EL301111 and Kanika Gupta ______________________

Comments/Instructions from the Project Guide:

Approved and Forwarded for Presentation -2

GROUP GUIDE: Prof. Aditya Mandloi ______________________

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Brent kung working

These are used to take up the binary additions because of their flexibility.
Carry Look Ahead Adder’s (CLA) structure is utilized in order to get the
parallel prefix adders . Tree structures algorithm are used to increase the
speed of arithmetic operation. Parallel prefix adders are used for high
performance arithmetic circuits in industries as they increase the speed of
operation. The construction of parallel prefix Adder involves three stages:
1. Pre- processing stage
2. Carry generation Process
3. Post processing stage
Pre-possessing stage:- Generate and propagate signals to each pair of the
inputs A and B are computed in this stage. These signals are given by the,
Following equations:
Pi=AixorBi (1)
Gi=AiandBi (2)
Carry generation network:- In this stage, carries equivalent to each bit is
calculated. All these operations are implemented and carried out in parallel.
Carries in parallel are segmented into smaller pieces after the
implementation of the stage. Carry propagate and generate are used as
intermediate signals which are given by the logic equations3& 4:

CPi:j=Pi:k+l and Pk:j (3)

CGi:j=Gi:k+l or (Pi:k+l and Gk:j) (4)
The operations involved in fig. 1 are given as:
CPO=Pi and Pj (3(i))
CGO=(Pi and Gj) or Gi (3(ii))

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Figure1: Carry Network
Post processing Stage:- This is the concluding step to compute the
summation of input bits. It is similar for all the adders and then sum bits are
computed by logic equation 4& 5: Ci-1= (Pi and Cin ) or (4) Si=Pi xor Ci-1
(5)

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