European Journal of Scientific Research

ISSN 1450-216X Vol.31 No.1 (2009), pp. 19-28

© EuroJournals Publishing, Inc. 2009
http://www.eurojournals.com/ejsr.htm

High Speed and Low Power FPGA Implementation of FIR Filter

for DSP Applications

Shanthala S
Asst. Professor, Bangalore Institute of Technology, Bangalore, India
Research Scholar, EC Research Centre
NMAM Institute of Technology
Nitte-574110, India
E-mail: shanthala_wg@yahoo.com

S. Y. Kulkarni
Principal, NMAM Institute of Technology
Nitte-574110, Karnataka, India
E-mail: sy_kul@yahoo.com

Abstract

Signal processing ranks among the most demanding applications of digital design
concepts and practices. It is a mature technology domain wherein the demands for
enhanced performance and reduced resource utilization have risen exponentially over the
years. Recent advancements in Field Programmable Gate Array (FPGA) design technology,
has resulted in FPGA(s) becoming the preferred platform for evaluating and implementing
signal processing algorithms. Special features of the FPGA architecture, like embedded
multipliers, fast carry chains, scalability and re-configurability make it a very attractive
platform for complex signal processing algorithms. Digital Signal Processing (DSP) deals
with the manipulation of digital signals using complex signal processing systems built from
basic building blocks like filters and signal transformations. The advent of engineering
tools like MATLAB has enabled the design of these basic building blocks faster and more
accurate. This document provides a brief discourse on the effective application of VLSI
design methodologies for efficient implementation of these basic DSP blocks, using an FIR
Filter and the Fast Fourier Transform as specific cases.

Keywords: Low Power, FIR filter, FPGA, DSP

1. Introduction
A filter is used to modify an input signal in order to facilitate further processing. A digital filter works
on a digital input (a sequence of numbers, resulting from sampling and quantizing an analog signal)
and produces a digital output. According to Dr. U. Meyer-Baese [Baese 2nd Ed.], “the most common
digital filter is the Linear Time-Invariant (LTI) filter”. Designing an LTI involves arriving at the filter
coefficients which, in turn, represents the impulse response of the proposed filter design. These
coefficients, in linear convolution with the input sequence will result in the desired output. The linear
convolution process can be represented as [[Baese 2nd Ed.]:
High Speed and Low Power FPGA Implementation of FIR Filter for DSP Applications 20

y[n] = x[n] * f [n] = ∑ x[k ] f [n − k ] = ∑ f [k ]x[n − k ]

k k
(1.1)

Here, y[n] signifies the output of the filter and x[n] is the digital input to the filter. The impulse
response of the filter is given by f[k] and the operator ‘*’ denotes the convolution operation. It can be
seen that the extent of the summation is governed by k, which denotes the extent of the impulse
response of the filter. Therefore, if the filter has an infinite impulse response, the summation extends to
infinity and the filter is said to be an Infinite Impulse Response (IIR) filter. A filter with a finite value
for k is said to be a Finite Impulse Response (FIR) filter. It can be inferred that the output of an FIR
filter remains dependant only on the inputs and the coefficients. Therefore, the FIR filter detailed above
is an LTI filter [2]. Equation (1.1) can be re-written as follows, for an order of L, as follows:
L −1
y [ n ] = x[ n ] * f [ n ] = ∑
k =0
f [ k ] x[ n − k ] (1.2)

Figure 1: shows the schematic of an FIR filter of order L.

Figure 1: FIR filter of order L, with constant coefficients

x[n] Z-1 Z-1 Z-1 Z-1

X X X X X
f[0] f[1] f[2] f[L-2] f[L-1]

+ + + + y[n]

Calculating the constant coefficients of such a digital filter involves considerable amount of
computation and this is generally performed using software tools. The Filter Design and Analysis
(FDA) tool packaged along with MATLAB is such a tool. The coefficients of an FIR filter, as
mentioned earlier, denote the impulse response of the filter. It is imperative for any system
implementation of such a filter to use a number format that represents the coefficients to as much
precision as allowed by the resource constraints. The double length floating point notation for filter
coefficients, used by the FDA tool poses immense challenges in terms of cost and resources, while
implementing on an FPGA. To overcome this, the filter coefficients have to be quantized to a fixed
point notation, resulting in the introduction of a certain amount of imprecision. This chapter details the
process of designing filters and analyzing the effects of coefficient quantization on the overall response
using the MATLAB FDA tool. Hardware description for the filter implementation is generated in
Verilog HDL and simulations of the hardware description are performed using ModelSim.

2. Designing Digital FIR Filters Using FDA Tool

The Filter Design and Analysis Tool (FDA Tool) is a graphical user interface (GUI) available in the
Signal Processing Toolbox of MATLAB for designing and analyzing filters. It takes the filter
specifications as inputs. Table 1 shows the specifications of an FIR low pass equi-ripple filter.

Table 1: FIR filter specifications

Filter performance parameter Value

Pass band frequency 11000 Hz
Pass band attenuation 3 dB
Stop band frequency 12000 Hz
Stop band attenuation 65 dB
Sampling frequency 48000
21 Shanthala S and S. Y. Kulkarni

The sampling frequency is chosen as 4 times the stop band and the filter has a steep transition
band with a width of 1000 Hz. These specifications are fed as inputs to the FDA tool in MATLAB
R2006b. The tool performs the filter design calculations using double precision floating point numeric
representation and displays the response of a reference filter. Figure 2 shows the filter design window
of FDA tool, after completion of the design process.

Figure 2: Filter design using MATLAB FDA tool

The designed filter is of order 84. It must be noted that the FDA Tool uses double precision
floating point representation for the design calculations. This allows the tool to achieve a fair degree of
precision, which is reflected in the close-to-ideal response of the reference filter. Figure 3 shows the
response of the reference filter, in detail. Specifications of the filter, namely, pass band, stop band,
transition band, pass band ripple and stop band ripple are denoted in the screen shot.

Figure 3: Response of the reference filter

High Speed and Low Power FPGA Implementation of FIR Filter for DSP Applications 22

The response shown is calculated from 0 Hz (DC) up to 24000 Hz, which is half of the
sampling frequency specified (FS / 2). The pass band response ripples with 0 dB as centre and the stop
band ripples are all below 65dB in magnitude. The filter has a steep transition band starting at 11000
Hz, achieving stop band attenuation at 12000 Hz.

2.1. Effects of finite word length

The accuracy of a digital filter is limited by the finite word length used in its implementation. When a
filter is constructed with digital hardware, the minimum word length needed for specified performance
accuracy must be determined [DeBrunner, 2002]. An ideal filter requires infinite word length to truly
represent the filter coefficients. However, the resource constraints associated with hardware
implementation pose the challenge of using fixed point arithmetic in VLSI implementations, for the
sake of cost and speed. The simplest and most widely used approach to the problem is to round off the
optimal infinite precision coefficients to a b-bit representation [Sung and Kum, 1995]. Two such
formats namely, Q 16.14 and Q8.7 are considered to analyze the effects of varying the word length
while quantizing the filter coefficients. The transfer function of a direct form FIR filter is given by:
M

∑b k z −k
H ( z) = k =0
L
(1.3)
1+ ∑ak z −k

k =0
As a result of the fixed point finite word length used in a digital filter, each coefficient is
replaced by its t-bit representation. That is, the coefficient ak is replaced by (ak + αk), with αk bounded
in absolute value by 2-b. Similarly, bk is replaced by (bk + βk), Therefore, the filter transfer function
changes . The new transfer function [H (z)]t is given by [DeBrunner, 2002]:

∑ (b )
M

k + β k z −k
[ H ( z )] = k =0
(1.4)
t
( )
L
1+ ∑ ak +αk z −k

k =0

2.2. Quantization to Q16.14 format

Using the FDA Tool, the reference filter is quantized to a Q16.14 fixed point numeric representation
format[Hu, DeBrunner & DeBrunner, 2002 and Lim, Yang, Li, and Song, 1999]. This means that the
total word length is 16 bits, out of which the most significant bit (MSB) is used to represent the sign of
the number, the next bit for representing the non-fractional magnitude and the remaining the fractional
magnitude. Table 2 illustrates this distribution in detail.

Table 2: Numeric representation format Q16.14 - Bit distribution

MSB Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit LSB
(15) (14) (13) (12) (11) (10) (9) (8) (7) (6) (5) (4) (3) (2) (1) (0)
s M MF MF MF MF MF MF MF MF MF MF MF MF MF MF

Here, ‘S’ denotes the sign bit, ‘M’ denotes the non fractional magnitude and ‘MF’ denotes the
fractional magnitude. After applying the aforesaid quantization to the filter coefficients, the response of
the filter is compared against that of the reference filter (which uses double precision floating point
representation). Figure 4 shows the response of the filter after quantizing the coefficients to Q16.14
format.
23 Shanthala S and S. Y. Kulkarni
Figure 4:FIR filter response after coefficient quantization to Q16.14

The quantized filter has larger ripples than the reference filter. This is explained by the fact that
the coefficients have lost some amount of precision while being quantized from a double precision
floating point representation to the Q16.14 format. As established by equation 1.2, any change in the
precision of the filter coefficients (F[k]) will have a direct bearing on the output of the filter.

2.3. Quantization to Q8.7 format

A larger effect of coefficient quantization can be observed for the representation format Q8.7.
Here, the total word length is 8 bits and the number of bits available for representing the fractional
magnitude is 7. Table 3 illustrates this distribution in detail.

Table 3: Numeric representation format Q16.14 - Bit distribution

MSB Bit Bit Bit Bit Bit Bit Bit

(8) (6) (5) (4) (3) (2) (1) (0)
S M MF MF MF MF MF MF

Here, ‘S’ denotes the sign bit, ‘M’ denotes the non fractional magnitude and ‘MF’ denotes the
fractional magnitude. After quantizing the filter coefficients to Q8.7 format, the response of the filter is
compared with the reference filter. Figure 5 shows the response of the filter after quantizing
coefficients to Q8.7 format.
The pass band response is relatively unaffected by the quantization. However, the difference is
drastic in the stop band response of the quantized filter. This is due to the substantial loss of precision
as a result of quantization to the sub-optimal Q8.7 format. Table 4 shows the effect of quantization on
the values of the first 4 filter coefficients.
High Speed and Low Power FPGA Implementation of FIR Filter for DSP Applications 24
Figure 5: FIR filter response after coefficient quantization to Q8.7

Table 4: Effect of quantization on filter coefficients

Coefficient Double precision floating point Quantized - Q 16.14* Quantized - 8.7*

f[0] -0.00054329878115638654 -0.00054931640625 0
f[1] -0.0070136005387712343 -0.00701904296875 -0.0078125
f[2] -0.021419539568209876 -0.02142333984375 -0.0234375
f[3] -0.034769720164499404 -0.0347900390625 -0.03125
Note: *The values of filter coefficients after quantization have been exported from FDA tool

2.4. Hardware Implementation - Generating Verilog HDL Code

The major challenge in implementing a higher order filter in hardware is the large number of
multiplications. During HDL generation from FDA Tool, instructions can be given to optimize the
HDL by using a variety of techniques like pipelining and distributed arithmetic. The FDA tool allows
the user to generate test benches to analyze the response of the filter to a variety of test input patterns.
The HDL code for the filter designed in the previous section is generated using FDA Tool, with
multipliers implemented in pipelined tree architecture. HDL code and test benches (for unit impulse
response) are generated for both the quantized versions (Q16.14 and Q8.7). The initial portion of the
simulation results for FIR filter with coefficients quantized to Q16.14 format is shown in Figure 6.
25 Shanthala S and S. Y. Kulkarni
Figure 6: Simulation results for Q16.14 FIR filter – Initial portion

An impulse input is applied to the filter at time 45ns (this is when the system comes out of
reset). The filter starts responding at time 200ns (after 155ns). The response sequence starts with the
first filter coefficient and goes on till time 1900ns, with 84 coefficients coming out as response. Note
that the output is 32 bit wide. The last signal displayed is the iteration counter (n) that shows the order
of the coefficient being output. Figure 7 shows the final portion of the output, showing the end of the
impulse response at time 1900ns.

Figure 7: Simulation results for Q16.14 FIR filter – Final portion

The approach for the Q8.7 filter is just the same and results obtained are also similar. Here, the
output is 16 bits wide. Figure 8 shows the response of the FIR filter with coefficients quantized to Q8.7
format.
High Speed and Low Power FPGA Implementation of FIR Filter for DSP Applications 26
Figure 8: Simulation results for Q16.14 FIR filter

Response
Response shows
shows more
more
inaccuracies
number due to zeroes
of finite
word length Q8.7
(inaccuracies)

3. Methods to Reduce the Effect of Fixed Word Length

Figure 9: Relation ship between δ, N and b [Kodek, 1980]

3.1. Integer Programming

The effect of fixing the word length used to represent the coefficients of a digital FIR filter of order N,
can be minimized by using an optimum number of bits b to represent the N coefficients of the filter by
using integer programming techniques. According to Dusan M. Kodek, “Using the approximate design
formula for optimal infinite-precision low-pass FIR filters and a statistical upper bound for error
27 Shanthala S and S. Y. Kulkarni

caused by the rounding, it is possible to get an approximate relationship between deviation δ, number
of coefficients N, and coefficient word length b.” [Kodek, 1980] This relationship between δ, N and b
is obtained experimentally upon optimal finite word length low-pass FIR filters defined by equations
(1.5) and (1.6), and for the equivalent filters with rounded coefficients. Figure 9 details the
relationship:
Pass band response D(f) = 1, Positive weight function W(f) = 1, 0 <f< 0.20 (1.5)
Stop band response D(f) = 0, Positive weight function W(f) = 1, 0.25 <f< 0.5. (1.6)
It can be seen that the response for optimal and rounded coefficients are very close. The
difference between the optimal and rounded coefficients multiplied by 2(b-1) is never greater than 4 for
all N between 6 and 40 and all b between 3 and 15. This shows that there is an optimal number of bits
b for each value of Nb. [Kodek, 1980].

3.2. Word Length Optimization

This is an iterative and qualitative method to arrive at the optimum word length based on a specified
system performance. The net-list of a signal flow block diagram is pre processed to group the signals
that can have the same fixed-point attributes in order to minimize the number of variables for the
optimization. The grouping strategy should be to group signals connected by a delay, a multiplexer, or
a switch or input-output signals of an adder etc. Based on the range of each signal, a uniform word
length is assigned to each group. Next step is to obtain a minimum word-length for each group, i.e., the
smallest word-length that satisfies the fixed-point performance of the system. The word length that has
the minimum hardware cost and still satisfies the specified system performance criteria, is chosen.
[Sung and Kum, 1995]

3.3. Cascade or Parallel Realization for Higher Order Filters

In general, the effect of coefficient inaccuracy resulting from finite word length fixed point
representation is more pronounced for a high-order filter when it is realized in the direct form than
when it is realized in the parallel or cascade form. Therefore, the parallel or cascade form should be
used for high-order filters whenever possible. The saving in the number of coefficient bits can be quite
substantial. [DeBrunner , 2002]

4. Conclusion
Using powerful computer based software tools to perform redundant calculations in the filter design
process enables a designer to arrive at the best design within the shortest time. While implementing a
filter on hardware, the biggest challenge is to achieve specified system performance at minimum
hardware cost. One among the hurdles is to understand, estimate and overcome where possible, the
effects of using a finite word length to represent the infinite word length coefficients. Selecting a non-
optimized word length can result in the filter transfer function being different from what is expected.
The effects of using finite word length representation can be minimized by analytical or qualitative
methods or simply by choosing to implement higher order filters in cascaded or parallel form.
High Speed and Low Power FPGA Implementation of FIR Filter for DSP Applications 28

References
[1] U. Meyer-Baese, Digital Signal Processing with Field Programmable Gate Arrays Second
Edition , Springer, p.109.
[2] U. Meyer-Baese, Digital Signal Processing with Field Programmable Gate Arrays Second
Edition , Springer, p.110.
[3] DUSAN M. KODEK, 1980, “Design of Optimal Finite Word length FIR Digital Filters Using
Integer Programming Techniques” IEEE Transactions on Acoustics, Speech, and Signal
Processing, Vol. ASSP-28, No. 3, JUNE 1980.
[4] Wonyong Sung and Ki-Il Kum, 1995, “Simulation-Based Word-Length Optimization Method
for Fixed-point Digital Signal Processing Systems”, IEEE Transactions on Signal Processing,
Vol. 43, No.12, December 1995.
[5] X. Hu, L. S. DeBrunner, and V. DeBrunner, 2002, “An efficient design for FIR filters with
Variable precision”, Proc. 2002 IEEE Int. Symp. on Circuits and Systems, pp.365-368, vol.
4,May 2002.
[6] Y. C. Lim, R. Yang, D. Li, and J. Song, 1999. “Signed-power-of-two term allocation scheme
for the design of digital filters,” IEEE Transactions on Circuits and Systems II, vol. 46, pp.577-
584, May 1999.
[7] S. C. Chan, W. Liu, and K. L. Ho, 2001, “Multiplier less perfect reconstruction modulated
filterbanks with sum-of-powers-of-two coefficients,” IEEE Signal Processing Letters, vol. 8,
no. 6,pp. 163-166, June 2001.