MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp.

81–85 81
ISSN 2230- 7672 © MIT Publications

Design Simulation and Analysis of NMOS

Characteristics for Varying Oxide Thickness
Alpana Singh Ritika Tandon Pallavi Saxena
Assistant Professor Assistant Professor ME Scholar
ECE Department ECE Department NITTTR, Chandigarh,
MIT Moradabad,Moradabad, U.P., MIT, Moradabad, Moradabad U.P., INDIA
INDIA INDIA pspallavisaxena@gmail.com
aalps_646@rediffmail.com ritikatandon15@gmail.com

ABSTRACT
In this paper effects of varying oxide thickness have been analyzed on oxide capacitance. The p well MOSFET device has been
designed and simulated using 80 nm technologies with TCAD tool. The oxide thickness has been varied from 10 nm to 11nm
and its effects on oxide capacitance has been analyzed. This result shows that when tox is 10.13 nm, the C’ox increased with 4.5
×10-17 F/m while C‘ox decreased by 12.3 % when tox is 10.42 nm. Since the integrated circuits being scaled down for improve-
ment in performance and lower power consumption, understanding the rate of gate oxide thickness will lead to better models.
Key Words: NMOS; Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET); Capacitance-Voltage
Characteristics; Oxide Thickness.

1. INTRODUCTION
The metal–oxide–semiconductor field-effect transistor or known
as MOSFET is the most used semiconductor device today. With
high yield, low cost and dense packaging is considerations that
have pushed the MOSFET to the status of the most widely used
device in information technology hardware[1]. The MOSFET
is a device used to amplify or switch electronic signals with fast
switching time and most important device for very large scale
integrated (VLSI) circuits such as microprocessor. With demand
increased for mobile communication and computation, power
consumption is a great value to be considered, the MOSFET
has become increasingly critical used since it consumes little
power[2]. In MOSFET, there are three terminals such as source
(S), drain (D) and gate (G). The top layer of the MOS system Fig. 1: Cross –section of NMOS structure
is the metal, and it is used to form the gate electrode. Central First, it is self isolating, so that the devices can placed side by
to the functionality is the thin insulating layer, the gate-oxide. side on a chip without the needs for providing isolation tubs. As
Gate oxide layer or known as dielectric is to provide an isolation a result, it is considerably smaller than its bipolar counterpart,
layer between metal and semiconductor so that there is no current and requires less processing steps. Furthermore, it can be made
flow between gate and substrate of the semiconductor as shown in bulk silicon, thus avoiding the costly epitaxial growth [5].
in Fig.1. Hence, epitaxial structures are increasingly used in high – density
Up till now, the silicon dioxide (SiO2) has been used as a gate- application, to minimize latch–up problems, caused by devices
oxide due to its properties of high- quality electrical insulator interactions through a common substrate.
and it’s used as barrier material during impurity deposition[3]. The MOS transistor contains two types, the p–channel MOS-
Besides, SiO2 is a very good insulator, typically having a FET (PMOS) and n-channel MOSFET (NMOS).Both of these
resistivity greater than 1015(Ω-cm) and large 8-9 eV energy band MOS transistors have their own characteristic that differenti-
gap. The MOS (Metal Oxide Semiconductor) transistor is the ates each other [6]. The p–channel transistor (PMOS), based
most promising active component for silicon VLSI circuits at the on aluminum – gate technology, was the earliest practical MOS
present time [4]. There are a number of reasons for this choice. device structure.
MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp. 81–85 82
ISSN 2230- 7672 © MIT Publications

In this project, the NMOS transistors are used. The purpose of 3. TCAD BASED NMOS DESIGN
this research is to analyze the effect of oxide thickness on C-V The general processes to design 80nm MOSFET involving
and I-V characteristics for the NMOS. simulation of fabrication process, structure and mesh and elec-
trical testing. A recipe of MOSFET is modified and used in this
2. BACKGROUND design. The first process was the simulation for 80nm MOSFET
One of important consideration of the MOS structure is the fabrication process which was designed using TCAD.
capacitance as a function of applied voltage. It is provide an For the fabrication process, the development of the NMOS started
important characterization tool to check on the quality of the with the formation of n-well for p-substrate. The p-substrate was
structure. In C-V measurements, a dc bias voltage is applied to layered with a 100A thick oxide layer by oxidation process. This
the gate, and a small signal is applied to obtain the capacitance oxide layer will act as a protector when doing ion implantation
at the bias applied. There are three important regions such as process. After that, phosphorus was implanted with the positive
accumulation, depletion and inversion. In accumulation, the resistive as a mask during the annealing process. The temperature
holes accumulate at the surface and creating a positive mobile used is in range 900-1200 Celsius temperature.
interface charge. There no depletion regions here. At this point,
the MOS is behave like a parallel plate capacitor with SiO2 as
the dielectric with equation
C’= C’ox per unit area ...(1)
where C’ox is the oxide capacitance per unit area.
As the gate voltage becomes positive and the channel is depleted
of holes, the depletion capacitance becomes. As the device gets
more depletion, it will be an inversion regions. The capacitance
depends on measurements at low frequencies (typically ~1 – 100
MHz) or high frequency (typically ~1MHz) since in certain time
is needed to generate the minority carriers in the inversion layer.
At low frequency, capacitance equals the oxide capacitance since
charge is added to and removed from inversion layer and the
capacitance can be calculated by equation.
eSiO2 Fig. 2: Structure of NMOS
C= ...(2)
tox The process is followed by formation of active area for transistor
Where SiO2 is oxide permittivity. NMOS. These areas were defined using photolithography. The
For high frequency, capacitance obtained from series connection active edge of NMOS which is p-well is normally covered by
of the oxide capacitance and depletion capacitance with maximum lithography. Then, the implantation of boron ion was done to
depletion width. From high frequency C-V characteristics in the increase the density of n-type surface. It will act as an obstacle
inversion, the values of parameter bulk or depletion capacitance of p-channel under the field oxide.
C’B, the depletion width WB and the doping concentration in
the substrate of can be calculated as in equation (3), (4) and(5).
eSi
CB = ...(3)
WB

 2εSi( 2φ f ) 
WB =  qN  ...(4)
4

kT N ' A
ff = ln ...(5)
q ηf
where q is the magnitude of charge (1.602 × 10–19 Coulomb),
Si is the dielectric constant of Si (11.8), k is Boltzman’s Constant
(1.38 × 10–23J/K), N’A is the acceptor concentration, and T is
temperature. The C’inversion also can be calculated by equation
(6).
C 'ox C ' B
Cinversion = ...(6)
C 'ox + C ' B Fig. 3: Meshing of NMOS
MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp. 81–85
ISSN 2230- 7672 © MIT Publications
The next process is the formation of the polysilicon gate where
the oxide layer will be growth and also the implantation of boron
ion. The pattern of the gate is designated by lithography action
for drain (D) and source (S). The formation process of drain (D)
and source(S) for MOSFET is carried with resistive electron layer
by all over the wafer for S and D pattern. The final process for 4. SIMULATION AND DISCUSSION
development of MOSFET is metallization. The aluminum materi-
als are doped on wafer surface. The resistive layer is coated and
the related patterns are made by lithography proces.
In process simulation, processing steps such as etching, depo-
sition, ion implantation, thermal annealing and oxidation are
Si simulated based on physical equations, which govern the
respective processing steps. The simulated part of the silicon
wafer is discredited (meshed) and represented as a finite-element structure manipulation, and loading structure information. The
structure. After the fabrication processes are completed, the
electrical testing called device simulation is done onto the
fabricated MOSFET.
Fig. 4: Layout of 80 nm NMOS transistor
Device simulations can be thought of as a virtual measurement
of the electrical behavior of a semiconductor device, such as a
transistor or diode. The device is represented as a meshed finite-
element structure.
Fig. 5: 2D view of NMOS
83
Each node of the device has properties associated with it, such
as material type and doping concentration. For each node, the
carrier concentration, current densities, electric field, generation
and recombination rates, and so on are computed.
A. Device Simulator
The process and device simulation has been done by TCAD.
There are some operation involved to fabricate NMOS structure
such as developing a good simulation grid, performing conformal
deposition, performing geometric etches, performing oxidation,
diffusion, annealing, and ion implantation, metallization,
NMOS structure can be plot by the TCAD simulator as shown
in Figs. 2,3,4,5.
In process simulation, processing steps such as etching,
deposition, ion implantation, thermal annealing and oxidation
are simulated based on physical equations,which govern the
respective processing steps. The simulated part of the silicon
wafer is discretized (meshed) and represented as a finite-element
structure. After the fabrication processes are completed, the
electrical testing called device simulation is done onto the
fabricated MOSFET.
B. C-v Characteristics
From Figs. 7 and 8, the graph that being extracted is for the low
frequency of 1Hz. When Vg = 0V or less, the graph shows that
it is in accumulation regions. The C’ox value in accumulation
for to x = 10.13nm is 4.5 ×10–17 F/m while C’ox value for tox
=10.42nm is 4.0 ×10–17 F/m. For Vg range of 0V to 2.5V, the
graph is in depletion regions and starts 2.5 V above, the graph
is in inversion regions.
Fig. 6: Gate oxidation parameters
During the inversion region, the capacitor depends on frequency.
The capacitance for 1Hz is equal to C’ox per unit area where
for Vg = 5V, C’ox value for tox = 10.13 nm is 6.875 × 10–17 F/m
and C’ox value in inversion for to x =10.42nm is 6.0 ×10–17
F/m. With low frequency, the values of C’ox can be calculated
by equation (2).
MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp. 81–85 84
ISSN 2230- 7672 © MIT Publications

There are two electrical DC analyses done onto the NMOS a

transistors to obtain the curve for ID (Drain Current) versus
VGS (Gate to Source Voltage) and ID (Drain Current) versus
VD (Drain Voltage).

Fig. 7: C-V characteristics graph for difference SiO2

In Table 1, the simulation values of C’ox is from Fig. 6 when

Vg = 0V for both thickness. For the simulation value of C’ox ,
its decreased by 12.3% when tox is 10.42nm while for calculated
value, C’ox decreased by 2.79 %.
Table 1: Values of C’ox of 10.13 nm and 10.42 nm Fig. 9: ID (Drain Current) -VGS (Gate to Source Voltage)

tox Calculated C’ox Simulation C’ox

10.13 nm 3.407 × 10 F/m
–3
4.5 × 10–1 F/m
10.42 nm 3.312 × 10–3 F/m 4.0 × 10–1 F/m

By equation (3), (4), (5) and (6), the C’B = 2.132 × 10–9 F/m,
WB = 0.049 m, and Φf = – 0.9307 V. The value of C’ inversion
for 10.13 nm is 1.7613 × 10–9 F/m while C’inversion for 10.42
nm is 1.769 ×10–9 F/m.

Fig. 10: ID (Drain Current)-VD (Drain Voltage)

graph for 80 nm NMOS

Table 2: Simulation values for 80nm MOSFET

Fig. 8: C-V characteristics graph for different oxide thickness
C. I-v ChARACTERISTICS
Figs 2,4 depict the layout for NMOS transistor. For both tran-
sistors, the metal used is aluminum. The metals are used for
interconnection and routing. The insulator used in this device
is polysilicon. The source and drain areas are shown in green
colour and placed in between gate region for both transistors.
The electrical DC analysis are done for both transistors and the
results are shown using TCAD tools.
Type NMOS
Vth (v) 0.210889
Idsat (A) 9.575e – 04
Ioff (A) 2.623e – 05
The threshold voltage (Vth) for transistor MOSFET is also
known as the voltage that was generated between the gate and
source at MOS device where current drain-source, drop until zero
value. From Figs. 9 and 10, Vth is the starting voltage for MOS
transistor. If the value of voltage that is being used is less than
Vth, the transistor will be in cut-off area. The threshold voltage
(Vth) for 80nm p-well MOSFET is 0.210889V for NMOS. Table
2 shows the value of drain saturation current (Idsat) for NMOS
transistor is 9.575e – 04. The Idsat is increasing proportionally
with the increasing of gate length.
MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp. 81–85 85
ISSN 2230- 7672 © MIT Publications

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