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Course Objectives:
1. To understand MOS device characteristics and to implement simple gates using CMOS
logic style with delay and power constraints
2. To understand the CMOS fabrication process styles including layout design rules
3. To design combinational and sequential circuits using different logic styles
4. To use modern EDA tools to simulate and synthesize VLSI circuits
Expected Course Outcome:
1. Clear understanding fundamental concepts of MOS transistors
2. Ability to design simple logic gates using CMOS logic style
3. Ability to calculate power and delay of simple CMOS circuits
4. Understanding of fabrication processes and their impact on the circuit performance
5. Ability to design and validate combinational and sequential circuits using different logic
styles
6. Ability to design VLSI circuits at sub-system abstraction level
7. Ability to use modern EDA tools to design VLSI circuits
Single bit Adder, Carry look ahead adder, Carry propagate Adder, Magnitude Comparator, Barrel
Shifter, Signed and unsigned multiplier.
Text Books:
1. Neil H.Weste, Harris, A. Banerjee, “CMOS VLSI Design, A circuits and System
Perspective”, 2014, Fourth Edition, Pearson Education, Noida, India.
Reference Books:
1. Jan M. Rabaey, Anantha Chadrakasan, BorivojeNikolic, “Digital Integrated Circuits: A
Design Perspective”, 2014, Third Edition, Prentice Hall India, New Jersey, US.
2. Yogesh Chauhan, Darsen Duane Lu, Vanugopalan Sriramkumar, Sourabh Khandelwal, Juan
Duarte, NavidPayvadosi, Ai Niknejad, Chenming Hu, “FinFETModeling for IC Simulation
and Design”, 2015, Academic Press, Elsevier.
Mode of Evaluation: Continuous Assessment Test –I (CAT-I), Continuous Assessment Test –II
(CAT-II), Digital Assignments/ Quiz / Completion of MOOC, Final Assessment Test (FAT).
CO – SLO Mapping
Theory:
Module CO SLO
1 CO_01 2
2 CO_02 2
3 CO_03 2
4 CO_04 5
5 CO_05 5
6 CO_05 5
7 CO_06 5
Laboratory:
CO-07 - SLO 14