Reg. No.

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Final Assessment Test – November 2017

Programme : B.Tech (ECE) Semester : Fall 2017 – 18
Code : ECE2003
Course Title : Digital Logic Design
Class Nbr(s) : 1789, 1786, 1788
Faculty(s) : S. Subashini, P. Reena Monica, S. Umadevi Slot : B2
Time : 3 Hours Max. Marks : 100

Answer all the Questions

Sub.
Q.No. Question Description Marks
Sec.
1. a. If the input to the digital circuit consisting of a cascade of 20 XOR gates as shown in
figure 1 ,then find the equivalent output Y

[5]

Figure 1

b. Convert the following decimal numbers to BCD code and then attach an odd parity bit to it
in the MSB position.
[5]

(i) 275 (ii) 9147

2. Derive a Karnaugh map representation of the function
F1 = (A,B,C,D) = Σ(0, 2, 3, 5, 6) and d(A,B,C,D) = Σ(8, 10, 13, 15).
Use the Karnaugh map method and verify by applying De Morgan’s theorem to derive a
minimal number of literals expression of F1. Design the two-level NAND-NAND [15]
implementation of the SOP form of function F1,and the two-level NOR-NOR
implementation of the POS form of function F1.

3. Design a combinational logic circuit with a single output that will serve as an auto buzzer
circuit. This circuit should output a HIGH signal to sound a buzzer for each of the
following conditions:
a) if the driver’s DOOR is open and the KEYS are in the ignition
[10]
b) if the SEATBELT is not buckled, the SEAT is occupied and the KEYS are in the
ignition
Construct the truth table for the conditions described above and design the buzzer control
unit using minimal number of logic gates.
4. Implement a 5-to-32-line decoder with four 3-to-8-line decoders with enable and a 2-to- 4-line
decoder. [10]

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5. Determine the state transition diagram from the sequential circuit

[15]

6. Design a shift register with parallel load operations according to the following function table
Shift Load Register operations
0 0 No change
[10]
0 1 Load parallel data
1 x Shift Right

7. Design a sequence detector that receives binary data stream at its input X and signals [10]
when a combination ‘1011’ arrives at the input by making its output Y high which
otherwise remains low. Consider, data is coming from right i.e. the first bit to be identified
is 1, second 1, third 0 and fourth 1 from the input sequence.
Show all the design steps and use ‘D’ flip flops for implementation. Consider a non-
overlapping binary sequence.
8. Write a verilog code to realise a 3-bit gray code counter using case statement. [5]
9. Write the Verilog code for a priority encoder such that if two or more single bit inputs are
[5]
at logic 1, then the input with highest priority will take precedence.
10. In a microcomputer the addresses of memory locations are binary numbers that identify
each memory circuit where a byte is stored. The number of bits that make up an address
depends on how many memory locations are there. Since the number of bits can be very
large, the addresses are often specified in Hex instead of binary.
(i) If a microprocessor uses 20-bit address, how many different memory locations [2]
are there?
(ii) How many hex digits are needed to represent the address of a memory
location? [2]
(iii) What is the Hex address of 256th memory location? (Note that the first address
[3]
is always ‘0’)
(iv) Draw the circuit of a 6T SRAM cell.
[3]
Total Marks [100]


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