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Construction 
of
Combinational
Circuits
4-bit binary
Adder-
Subtractor
Difference
between
EPROM and
EEPROM
Difference
between
Decoder and
Demultiplexer
Prime
Implicant chart
for minimizing
Cyclic Boolean
functions
Difference
⇣
between DDR
and SDRAM
Counting
Boolean
function with
some variables
Don't Care (X)

Conditions in
K-Maps
1 of 16 06/12/19, 3:09 pm
Adders and Subtractors in Digital Logic

Block Diagram of Combinational Logic Circuit:
2 of 16 06/12/19, 3:09 pm
Points to Remember on Combinational Logic Circuit:
1. Output depends upon the combination of inputs.

2. Output is pure function of present inputs only i.e., Previous State inputs won’t have any ef-
fect on the output. Also, It doesn’t use memory.
3. In other words,
OUTPUT=f(INPUT)
4. Inputs are called Excitation from circuits and outputs are called Response of combinational
logic circuits.
Classi�cation of Combinational Logic Circuits:
1. Arithmetic:
Adders
⇣
Subtractors
Multipliers
Comparators
2. Data Handling:
Multiplexers
DeMultiplexers
Encoders and Decoders
3. Code Converters:
BCD to Excess-3 code and vice versa

BCD to Gray code and vice versa
Seven Segment ▲
Design of Half Adders and Full Adders:
3 of 16 06/12/19, 3:09 pm
A combinational logic circuit that performs the addition of two single bits is called Half
Adder.
A combinational logic circuit that performs the addition of three single bits is called Full
Adder.
1. Half Adder:
It is a arithmetic combinational logic circuit designed to perform addition of two single bits.
It contain two inputs and produces two outputs.
Inputs are called Augend and Added bits and Outputs are called Sum and Carry.
Let us observe the addition of single bits,
0+0=0
0+1=1
1+0=1
1+1=10
Since 1+1=10, the result must be two bit output. So, Above can be rewritten as,
0+0=00
⇣
0+1=01
1+0=01
1+1=10
The result of 1+1 is 10, where ‘1’ is carry-output (C out) and ‘0’ is Sum-output (Normal Output).
4 of 16 06/12/19, 3:09 pm
Truth Table of Half Adder:
Next Step is to draw the Logic Diagram. To draw Logic Diagram, We need Boolean Expression,
which can be obtained using K-map (karnaugh map). Since there are two output variables ‘S’ and
‘C’, we need to de�ne K-map for each output variable.
⇣
K-map for output variable Sum ‘S’ :
K-map is of Sum of products form. The equation obtained is ▲
S = AB' + A'B
5 of 16 06/12/19, 3:09 pm
which can be logically written as,
S = A xor B
K-map for output variable Carry ‘C’ :
The equation obtained from K-map is,

⇣
C = AB
Using the Boolean Expression, we can draw logic diagram as follows..
6 of 16 06/12/19, 3:09 pm
Limitations:
Adding of Carry is not possible in Half adder.
2. Full Adder:
To overcome the above limitation faced with Half adders, Full Adders are implemented.
It is a arithmetic combinational logic circuit that performs addition of three single bits.
It contains three inputs (A, B, Cin) and produces two outputs (Sum and Cout).
Where, Cin -> Carry In and Cout -> Carry Out
Truth table of Full Adder:

⇣
▲
K-map Simpli�cation for output variable Sum ‘S’ :
7 of 16 06/12/19, 3:09 pm
The equation obtained is,
S = A'B'Cin + AB'Cin' + ABC + A'BCin'
The equation can be simpli�ed as,
S = B'(A'Cin+ACin') + B(AC + A'Cin')

S = B'(A xor Cin) + B (A xor Cin)'
S = A xor B xor Cin
K-map Simpli�cation for output variable ‘Cout‘

⇣
Cout = BCin + AB + ACin
Logic Diagram of Full Adder:
8 of 16 06/12/19, 3:09 pm
3. Half Subtractor:
⇣
It is a combinational logic circuit designed to perform subtraction of two single bits.

It contains two inputs (A and B) and produces two outputs (Difference and Borrow-output).
Truth Table of Half Subtractor:
9 of 16 06/12/19, 3:09 pm
K-map Simpli�cation for output variable ‘D’ :
D = A'B + AB'
which can be logically written as,
D = A xor B
K-map Simpli�cation for output variable ‘Bout‘ :

⇣
The equation obtained from above K-map is,
Bout = A'B
Logic Diagram of Half Subtractor:
10 of 16 06/12/19, 3:09 pm
4. Full Subtractor:
It is a Combinational logic circuit designed to perform subtraction of three single bits.

It contains three inputs(A, B, Bin) and produces two outputs (D, Bout).
Where, A and B are called Minuend and Subtrahend bits.
And, Bin -> Borrow-In and Bout -> Borrow-Out
⇣
Truth Table of Full Subtractor:
11 of 16 06/12/19, 3:09 pm
K-map Simpli�cation for output variable ‘D’ :
The equation obtained from above K-map is,
D = A'B'Bin + AB'Bin' + ABBin + A'BBin'
which can be simpli�ed as,
D = B'(A'Bin + ABin') + B(ABin + A'Bin')

D = B'(A xor Bin) + B(A xor Bin)'
D = A xor B xor Bin
K-map Simpli�cation for output variable ‘Bout‘ :

⇣
12 of 16 06/12/19, 3:09 pm
Bout = BBin + A'B + A'Bin
Logic Diagram of Full Subtractor:

⇣
Applications:
1. For performing arithmetic calculations in electronic calculators and other digital devices.
2. In Timers and Program Counters.
3. Useful in Digital Signal Processing.
13 of 16 06/12/19, 3:09 pm
Recommended Posts:
Multiplexers in Digital Logic
BCD Adder in Digital Logic
Latches in Digital Logic
Encoder in Digital Logic
⇣
Counters in Digital Logic

5 variable K-Map in Digital Logic
Full Subtractor in Digital Logic
Variable Entrant Map (VEM) in Digital Logic
n-bit Johnson Counter in Digital Logic
Encoders and Decoders in Digital Logic
Magnitude Comparator in Digital Logic
Ripple Counter in Digital Logic
Binary Decoder in Digital Logic
Shift Registers in Digital Logic
Consensus Theorem in Digital Logic
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Adders and Subtractors in Digital Logic - Geeks... https://www.geeksforgeeks.org/adders-and-subt...

Courses Custom Search Hire with us!

Don't Care (X)

Adders and Subtractors in Digital Logic

Points to Remember on Combinational Logic Circuit:

1. Output depends upon the combination of inputs.

Classi�cation of Combinational Logic Circuits:

BCD to Excess-3 code and vice versa

Design of Half Adders and Full Adders:

Let us observe the addition of single bits,

Truth Table of Half Adder:

K-map for output variable Sum ‘S’ :

K-map is of Sum of products form. The equation obtained is ▲

which can be logically written as,

K-map for output variable Carry ‘C’ :

The equation obtained from K-map is,

Using the Boolean Expression, we can draw logic diagram as follows..

Truth table of Full Adder:

The equation obtained is,

S = A'B'Cin + AB'Cin' + ABC + A'BCin'

The equation can be simpli�ed as,

S = B'(A'Cin+ACin') + B(AC + A'Cin')

K-map Simpli�cation for output variable ‘Cout‘

The equation obtained is,

Cout = BCin + AB + ACin

Logic Diagram of Full Adder:

It is a combinational logic circuit designed to perform subtraction of two single bits.

Truth Table of Half Subtractor:

K-map Simpli�cation for output variable ‘D’ :

The equation obtained is,

which can be logically written as,

K-map Simpli�cation for output variable ‘Bout‘ :

The equation obtained from above K-map is,

Logic Diagram of Half Subtractor:

It is a Combinational logic circuit designed to perform subtraction of three single bits.

Truth Table of Full Subtractor:

K-map Simpli�cation for output variable ‘D’ :

The equation obtained from above K-map is,

D = A'B'Bin + AB'Bin' + ABBin + A'BBin'

which can be simpli�ed as,

D = B'(A'Bin + ABin') + B(ABin + A'Bin')

K-map Simpli�cation for output variable ‘Bout‘ :

The equation obtained is,

Bout = BBin + A'B + A'Bin

Logic Diagram of Full Subtractor:

Counters in Digital Logic

Feedback/ Suggest Improvement Add Notes Improve Article

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