8 Bit Adder

Description of Parts:

A full adder is a combinational circuit that forms the arithmetic sum of three input bits. It has two
inputs: X and Y, that represent the two significant bits to be added, and a Z input that is a carry-in from
the previous significant position. It has two outputs: S which is the sum of the two input bits which can
be 0-3 and Z to carry the value in case the output from S is 2 or 3 because the binary forms of these
require two digits for their representation.

(Mano, M. Morris., and Charles R. Kime. Logic and Computer Design Fundamentals. Singapore: Pearson /
Prentice Hall, 2008. Print.)

Waveform full-adder:
This waveform corresponds to the following truth table where n0 = A, n1 = B, n6 = S, and n7=Cout

There individual signals should correspond exactly with the activity in the waveform:

Inputs Outputs

X Y Z C S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

We take 8 of these full adders, now that we’ve shown that they work, and combine them to create an 8
bit Adder. In an 8 bit adder the full adders are connected in a cascade with a 1 carry cascading from a
least significant bit to the most significant bit.

Complete 8-bit Adder:

Technically the first Carry-In on the first full adder (also the full adder of the least significant bit) does
not have to be there. But to keep this design modular I left it in. In case I wanted to use this design
somewhere else I would not have to change the first adder to one that accepts bits.
Test Cases:

1) A few test cases were beneficial to show that it functions as desired. We already know that
individual full adders have to send carry bits to the next full adder:

2) When you add 8 bits + 1 bit, or 255 + 1, you should get only the last carry-out to light up
because its goes up to the next order of magnitude 2^n:

3) Lastly if you add all 8 bits to 8 bits together all of the outputs except for the least significant bit
should light up along with the last carry out:

4) This waveform is of the ripple effect created by adding each of the bits sequentially:
As I turn on bits n0–n15 which sequentially adds all of the bits in the 8 bit adder (i.e. bit in position 0 +
bit 2 in position 0 is n0 + n1), we see a ripple effect as the outputs (n23-n30) turn on. When it is 1 + 0
we see that the full adder’s output is on, however when it is 1+1 we see the next full adder’s output light
up and the current adder output light is off. When it is the scenario of 1+1+1 from a previous carry, we
can see both adder’s output lights come on, this is proven by the waveform.
 8-bit 4-1 Multiplexer

Description of Parts:

A multiplexer is a combinational circuit that selects information in binary from multiple input lines and
selects between them to direct the information down one output line. This selection of inputs is guided
by ‘n’ select inputs where 2^’n’ is the amount of inputs. Due to this reasoning because there are 4 inputs
in a 4-1 multiplexer there should be 2 selection inputs. These select bits are actually part of a 2-4
decoder that allows us to select which 8 bit bus input to send through the multiplexer.

(Mano, M. Morris., and Charles R. Kime. Logic and Computer Design Fundamentals. Singapore: Pearson /
Prentice Hall, 2008. Print.)

(2^ 2 (amount of select inputs) = 4 (amount of inputs))

A condensed truth table for the 4-1 Multiplexer is:

S1 S0 | Y

0 0 | I0

0 1 | I1

1 0 | I2

1 1 | I3

The 4-1 multiplexer was created with an 8 bit bus inputs and 8 bit bus output.

Two Modules were added to show comprehensively how an 8 bit bus is AND’ed and OR’ed as shown on
the following pages:
Module 1:

A module was made to show the AND operation on each bit of the 8 bit but inputs:

Waveform:

When the Enable is off the output doesn’t change, however when the enable is on we can see
that it passes the input on to the output. Only when the Enable is on and that is the function of this
module.

In action:
The 8 bit bus is expanded by an expander into single bits. Each one of these bits is then AND’ed with the
Enable. This enable is actually the input from the select inputs from the 2-4 decoder part of the
multiplexer. Once again, only one of the 8 bit buses will be enabled depending on the select inputs. This
module was made to show what actually happens when an 8 bit bus is AND’ed with a select bit.
Particularly that each one of the bits is individually AND’ed with the enable or select bit.

Module 2:

The other module was made to show the OR operation on every single bit in the 8 bit bus:

We can see that while the other buses are inactive, n3’s bus is passing its output on. Here it is in action:
Only one of these buses will be passing an input and output at a time which was chosen in the previous
module by the AND module depending on the select bits. This module OR’s every single bit between all
four of the 8 bit buses. This works because only one of the buses is active at a given time depending on
the select input because the previous AND module allows only one 8 bit bus to pass its output to this OR
module.

Complete 8-Bit 4-1 Multiplexer:

Test Cases:

Right away we see that just like in the truth table when both select inputs, S1 and S0, are off: input I0 is
passing its output.

When select S0 is on, we see input I1 is passing its output.

When select S1 is on Input I2 is passing its output.

As expected, when both select inputs are on, input I3 passes its input.
The waveform for the 4-1 multiplexer looks like this:

n4-n7 at the 8 bit bus inputs that I’ve so we can prove that the select bits indeed do choose between
them and output just one of them.

While running through the original truth table with the select bits n0 = S0 and n1= S1 we can see that
the individual inputs are being sent to n15 the output. In table form:

S1 S0 | Output

0 0 | 4

0 1 | 3

1 0 | 2

1 1 | 1